Page 1
Presettable Up/Down Counter
High-Voltage Silicon-Gate CMOS
The IW4516B Presettable Binary Up/Down Counter consists of
four synchronously clo cked D-type flip-flops (with a gating struc t ure to
provide T-type flip-flop capability) connected as counters. This
counter can be cleared by a high level on the RESET line, and can be
preset to any binary number present on the jam inputs by a high level
on the PRESET ENABLE line.
If the CARRY-IN input is held low, the counter advances up or
down on each positive-going clock transition. Synchronous cascading
is accomplished by connecting all clock inputs in parallel and
connecting the CARRY-OUT of a less significant stage to the
CARRY-IN of a more significant stage.
The IW4516B can be cascaded in the ripple mode by connecting
the CARRY-OUT to the clock of the next stage. If the UP/DOWN
input changes during a terminal count, the CARRY-OUT must be
gated with the clock, and the UP/DOWN input must change while the
clock is high. This method provides a clean clock signal to the
subsequent count i ng stage.
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
TECHNICAL DATA
IW4516B
ORDERING INFORMATION
IW4516BN Plastic
IW4516BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=V
PIN 8= GND
CC
FUNCTION TABLE
Inputs Outputs
CL CI U/D PE R Mode
X H X L L NO COUNT
L H L L COUNT UP
L L L L COUNT
DOWN
XX X HL PRESET
X X X X H RESET
X = don’t care
157
Page 2
IW4516B
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
P
P
DC Supply Voltage (Referenced to GND) -0.5 to +20 V
DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
Power Dissipation per Output Transistor 100 mW
D
±
10
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
VIN, V
T
CC
A
DC Supply Voltage (Referenced to GND) 3.0 18 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
CC
mA
mW
°
C
°
C
V
°
C
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
IN
or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
and V
IN
should be constrained to the range
OUT
CC
Unused outputs must be left open.
158
).
Page 3
IW4516B
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
IH
IL
OH
Minimum High-Level
Input Voltage
Maximum Low -Leve l
Input Voltage
Minimum High-Level
V
= 0.5 V or V
OUT
V
= 1.0 V or V
OUT
V
= 1.5 V or V
OUT
V
= 0.5 V or V
OUT
V
= 1.0 V or V
OUT
V
= 1.5 V or V
OUT
VIN=GND or V
CC
CC
CC
CC
CC
CC
CC
- 0.5V
- 1.0 V
- 1.5V
- 0.5V
- 1.0 V
- 1.5V
Output Voltage
V
OL
Maximum Low-Leve l
VIN=GND or V
CC
Output Voltage
I
IN
Maximum Input
VIN= GND or V
CC
Leakage Current
I
CC
Maximum Quiesce nt
VIN= GND or V
CC
Supply Current
(per Package)
I
OL
I
OH
Minimum Output Low
(Sink) Current
Minimum Output
High (Source) Current
VIN= GND or V
UOL=0.4 V
U
=0.5 V
OL
U
=1.5 V
OL
VIN= GND or V
UOH=2.5 V
U
=4.6 V
OH
U
=9.5 V
OH
U
=13.5 V
OH
CC
CC
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
18
5.0
10
15
20
5.0
10
15
5.0
5.0
10
15
CC
≥
14.95
Guaranteed Limit
-55°C25°C
3.5
7
11
1.5
3
4
4.95
9.95
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±
0.1
5
10
20
100
0.64
1.6
4.2
-2
-0.64
-1.6
-4.2
0.05
0.05
0.05
±
0.1
5
10
20
100
0.51
1.3
3.4
-1.6
-0.51
-1.3
-3.4
≤
125
°
C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±
1.0
150
300
600
3000
0.36
0.9
2.4
-1.15
-0.36
-0.9
-2.4
Unit
V
V
V
V
µ
A
µ
A
mA
mA
159
Page 4
IW4516B
AC ELECTRICAL CHARACTERISTICS
(CL=50pF, RL=200kΩ, Input tr=tf=20 ns)
Symbol Parameter V
t
PHL
, t
Maximum Propagati on Delay, Clock to Q
PLH
(Figure 1)
t
PHL
, t
Maximum Propagation Delay, Preset or Reset to
PLH
Q (Figure 1)
t
PHL
, t
Maximum Propagation Delay, Clock to Carry
PLH
Out (Figure 1)
t
PHL
, t
Maximum Propagation Delay, Carry In to Carry
PLH
Out (Figure 1)
t
PHL
, t
Maximum Propagation Delay, Preset or Reset to
PLH
Carry Out (Figure 1)
t
THL
, t
Maximum Output Transition Time, Any Output
TLH
(Figure 1)
C
IN
Maximum Input Capacitance - 7.5 pF
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
CC
≥
Guaranteed Limit
-55°C25°C
400
200
150
420
210
160
480
240
180
250
120
100
640
320
250
200
100
80
400
200
150
420
210
160
480
240
180
250
120
100
640
320
250
200
100
80
≤
125°C
800
400
300
840
420
320
960
480
360
500
240
200
1280
640
500
400
200
160
Unit
ns
ns
ns
ns
ns
ns
TIMING REQUIREMENTS
(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
Symbol Parameter V
t
su
Minimum Setup Time, P to Pres et Enable
(Figure 1)
t
su
Minimum Setup Time, Up/Down to Clock
(Figure 1)
t
su
Minimum Setup Time, C arry In to Clock
(Figure 1)
t
h
t
h
Minimum Hold Time, Clock to Carry In (Figure1)5.0
Minimum Hold Time, Clock to Up/Do wn
(Figure 1)
t
h
Minimum Hold Time, Preset enable to P (Figure1)5.0
V
5.0
10
15
5.0
10
15
5.0
10
15
10
15
5.0
10
15
10
15
CC
≥
Guaranteed Limit
-55°C25°C
25
10
10
60
30
30
30
30
30
70
40
40
25
10
10
60
30
30
30
30
30
70
40
40
≤
125°C
50
20
20
120
60
60
60
60
60
140
80
80
Unit
ns
ns
ns
ns
ns
ns
160
Page 5
Figure 1. Switching Waveforms
IW4516B
TIMING DIAGRAM
161
Page 6
IW4516B
EXPANDED LOGIC DIAGRAM
162
Loading...