Page 1
Strobed Hex Inverter/Buffer
High-Voltage Silicon-Gate CMOS
The IW4502B consists of six inverter/buffers with 3-state outputs.
A logic “1” on the OUTPUT ENABLE input produces a high
impedance state in all six outputs. This feature permits common busing
of the outputs, thus simplifying system design. A logic “1” on the
DIRECTION input switches all six outputs to logic “0” if the
OUTPUT ENABLE input is a logic “0”.
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
TECHNICAL DATA
IW4502B
ORDERING INFORMATION
IW4502BN Plastic
IW4502BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 16=V
PIN 8= GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
Output
Enable
LLLH
LLHL
LHXL
HXXZ
Z = high impedance
X = don’t care
Direction A Y
147
Page 2
IW4502B
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
P
P
DC Supply Voltage (Referenced to GND) -0.5 to +20 V
DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
Power Dissipation per Output Transistor 100 mW
D
±
10
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
VIN, V
T
CC
A
DC Supply Voltage (Referenced to GND) 3.0 18 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
CC
mA
mW
°
C
°
C
V
°
C
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
IN
or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
and V
IN
should be constrained to the range
OUT
CC
Unused outputs must be left open.
148
).
Page 3
IW4502B
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
IH
IL
OH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
V
=0.5 V
OUT
V
=1 V
OUT
V
=1.5
OUT
V
= V
= V
= V
CC
CC
CC
- 0.5V
- 1.0 V
- 1.5V
OUT
V
OUT
V
OUT
VIN=GND 5.0
Output Voltage
V
OL
Maximum Low-Level
VIN= V
CC
Output Voltage
I
IN
Maximum Input
VIN= GND or V
CC
Leakage Current
I
CC
Maximum Qui escent
VIN= GND or V
CC
Supply Current
(per Package)
I
OL
I
OH
I
OZ
Minimum Output Low
(Sink) Current
Minimum Output
High (Source) Current
Maximum Tree-State
Leakage Current
VIN= GND or V
CC
UOL=0.4 V
U
=0.5 V
OL
U
=1.5 V
OL
VIN= GND or V
CC
UOH=2.5 V
U
=4.6 V
OH
U
=9.5 V
OH
U
=13.5 V
OH
Output in High-Impedance
State
V
= GND or V
IN
V
= GND or V
OUT
CC
CC
V
5.0
10
15
5.0
10
15
10
15
5.0
10
15
18
5.0
10
15
20
5.0
10
15
5.0
5.0
10
15
18
CC
≥
14.95
Guaranteed Limit
-55°C25°C
3.5
7
11
1.5
3
4
4.95
9.95
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±
0.1
1
2
4
20
3.84
9.6
25.2
-2
-0.64
-1.6
-4.2
±
0.4
0.05
0.05
0.05
±
0.1
1
2
4
20
3.06
7.8
20.4
-1.6
-0.51
-1.3
-3.4
±
0.4
≤
125
°
C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±
1.0
30
60
120
600
2.16
5.4
14.4
-1.15
-0.36
-0.9
-2.4
±
12
Unit
V
V
V
V
µ
A
µ
A
mA
mA
µ
A
149
Page 4
IW4502B
AC ELECTRICAL CHARACTERISTICS
t
=20 ns)
r=tf
(CL=50pF, RL=200kΩ unless otherwise specified, Input
Symbol Parameter V
t
PHL
Maximum Propagation Delay, Input A or
Direction to Output Y (Figure 1)
t
PLH
Maximum Propagation Delay, Input A or
Direction to Output Y (Figure 1)
t
PHZ
Maximum Propagation Delay, Output Enable to
Output Y (Figure 2)
Ω
= 1 k
R
L
t
PZH
Maximum Propagation Delay, Output Enable to
Output Y (Figure 2)
Ω
= 1 k
R
L
t
PLZ
Maximum Propagation Delay, Output Enable to
Output Y (Figure 2)
Ω
= 1 k
R
L
t
PZL
Maximum Propagation Delay, Output Enable to
Output Y (Figure 2)
Ω
= 1 k
R
L
t
TLH
Maximum Output Transition Time, Any Output
(Figure 1)
t
THL
Maximum Output Transition Time, Any Output
(Figure 1)
C
IN
C
OUT
Maximum Input Capacitance - 7.5 pF
Maximum Tree-State Output Capacitance
(Output in High-Impedance State)
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
CC
Guaranteed Limit
≥
-55°C25°C
270
120
80
380
180
130
120
80
60
220
100
80
250
130
110
250
110
80
200
100
80
120
60
40
270
120
80
380
180
130
120
80
60
220
100
80
250
130
110
250
110
80
200
100
80
120
60
40
≤
125°C
540
240
160
760
360
260
240
160
120
440
200
160
500
260
220
500
220
160
400
200
160
240
120
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
-15pF
150
Page 5
IW4502B
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/6 of the Device)
151
Loading...