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14-Stage Ripple-Carry Binary
Counter/Divider and Oscillator
High-Voltage Silicon-Gate CMOS
The IW4060B consists of an oscillator section and 14 ripple-carry
binary counter stages. The oscillator configuration allows design of
either RC or crystal oscillator circuits. A RESET input is provided
which resets the counter to the all-Q’s state and disables the o scillator.
A high level on the RESET line accomplishes the reset function. All
counter stages are master-slave flip-flops. The state of the counter is
advanced one step in binary order on the negative transition of OSC In
(and OSC Out). Schmitt trigger action on the input-pulse line permits
unlimited input-pulse rise and fall times.
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
TECHNICAL DATA
IW4060B
ORDERING INFORMATION
IW4060BN Plastic
IW4060BD SOIC
TA = -55° to 125° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=V
PIN 8= GND
CC
FUNCTION TABLE
Inputs Outputs
Osc In Reset Q
L No change
L Advance to
next state
X H All Outputs
are low
X = don’t care
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IW4060B
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
P
P
DC Supply Voltage (Referenced to GND) -0.5 to +20 V
DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
Power Dissipation per Output Transistor 100 mW
D
±
10
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
VIN, V
T
CC
A
DC Supply Voltage (Referenced to GND) 3.0 18 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
CC
mA
mW
°
C
°
C
V
°
C
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
IN
or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
and V
IN
should be constrained to the range
OUT
CC
Unused outputs must be left open.
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).
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IW4060B
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
IH
IL
OH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
V
= 0.5 V or V
OUT
V
= 1.0 V or V
OUT
V
= 1.5 V V
OUT
V
= 0.5 V or V
OUT
V
= 1.0 V or V
OUT
V
= 1.5 V V
OUT
VIN=GND or V
CC
CC
CC
- 0.5V
CC
- 1.0 V
CC
- 1.5V
- 0.5V
CC
- 1.0 V
CC
- 1.5V
Output Voltage
V
OL
Maximum Low-Level
VIN=GND or V
CC
Output Voltage
I
IN
Maximum Input
VIN= GND or V
CC
Leakage Current
I
CC
Maximum Quiescent
VIN= GND or V
CC
Supply Current
(per Package)
I
OL
I
OH
Minimum Output Low
(Sink) Current
Minimum Output
High (Source) Current
VIN= GND or V
UOL=0.4 V
U
=0.5 V
OL
U
=1.5 V
OL
VIN= GND or V
UOH=2.5 V
U
=4.6 V
OH
U
=9.5 V
OH
U
=13.5 V
OH
CC
CC
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
18
5.0
10
15
20
5.0
10
15
5.0
5.0
10
15
CC
≥
14.95
Guaranteed Limit
-55°C25°C
3.5
7
11
1.5
3
4
4.95
9.95
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±
0.1
5
10
20
100
0.64
1.6
4.2
-2
-0.64
-1.6
-4.2
0.05
0.05
0.05
±
0.1
5
10
20
100
0.51
1.3
3.4
-1.6
-0.51
-1.3
-3.4
≤
125
°
C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±
1.0
150
300
600
3000
0.36
0.9
2.4
-1.15
-0.36
-0.9
-2.4
Unit
V
V
V
V
µ
A
µ
A
mA
mA
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IW4060B
AC ELECTRICAL CHARACTERISTICS
(CL=50pF, RL=200kΩ, Input tr=tf=20 ns)
Symbol Parameter V
f
max
Maximum Clock Frequency (50 % Duty Cycle)
(Figure 1)
t
PHL
, t
Maximum Propagati on Delay, Clock to Q4
PLH
(Figure 1)
t
PHL
, t
Maximum Propagat i on Delay, Qn to Q
PLH
n+1
(Figure 2)
t
PHL
Maximum Propagation Delay, Reset to Any Q
(Figure 3)
t
THL
, t
Maximum Output Transition Time, Any Output
TLH
(Figure 1)
C
IN
Maximum Input Capacitance - 7.5 pF
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
CC
≥
Guaranteed Limit
-55°C25°C
3.5
8
12
740
300
200
200
100
80
360
160
100
200
100
80
3.5
8
12
740
300
200
200
100
80
360
160
100
200
100
80
≤
125°C
1.75
1480
600
400
400
200
160
720
320
200
400
200
160
Unit
MHz
4
6
ns
ns
ns
ns
TIMING REQUIREMENTS
(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
Symbol Parameter V
t
t
tf, t
w
w
Minimum Pulse Width, Clock (Figure 1 ) 5.0
Minimum Pulse Width, Reset (Figure 3) 5.0
Maximum Input Rise and Fall Times (Figure 1) 5.0
r
V
CC
10
15
10
15
Guaranteed Limit
≥
-55°C25°C
100
40
30
120
60
40
100
40
30
120
60
40
≤
125°C
200
80
60
240
120
80
Unit
ns
ns
ns
10
Unlimited
15
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Figure 1. Switching Waveforms
IW4060B
Figure 2. Switching Waveforms Figure 3. Switching Waveforms
EXPANDED LOGIC DIAGRAM
R = HIGH DOMINATES (RESETS ALL STAGES)
*
** COUNTER ADVANCES ONE BINARY COUNT ON EACH NEGATIVE - GOING TRANSITION OF
CLOCK (AND OSC OUT)
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