Page 1
Hex Buffer/Converter
High-Voltage Silicon-Gate CMOS
The IW4050B is noninverting hex buffers and feature logic-level
conversion using only one sup p ly (vol ta ge ( V
level (V
used for logic-level conversions. These devices are intended for use as
CMOS to DTL/TTL converters.
•
•
•
•
) can exceed the VCC supply voltage when these devices are
IH
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
High-to-low level c onversion
). The input-si gnal hi gh
CC
TECHNICAL DATA
IW4050B
ORDERING INFORMATION
IW4050BN Plastic
IW4050BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PINS 13, 16 = NO CONNECTION
PIN 1 =V
PIN 8 = GND
CC
PIN ASSIGNMENT
NC = NO CONNECTION
FUNCTION TABLE
Inputs Output
AY
LL
HH
93
Page 2
IW4050B
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
P
P
DC Supply Voltage (Referenced to GND) -0.5 to +20 V
DC Input Voltage (Referenced to GND) V
IN
**
to +18 V
CC
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
Power Dissipation per Output Transistor 100 mW
D
±
10
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
**
The IW4050B has high-to-low level voltage conversion capability but not low-to-high level; therefore it is
recommended that V
IN
≥ V
CC
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
V
IN
V
OUT
T
A
**
The IW4050B has high-to-low level voltage conversion capability but not low-to-high level; therefore it is
recommended that V
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 3.0 18 V
DC Input Voltage (Referenced to GND) V
CC
**
DC Output Voltage (Referenced to GND) 0 V
Operating Temperature, All Package Types -55 +125
≥ V
IN
CC
IN
or V
OUT
)≤VCC.
and V
IN
should be constrained to the range
OUT
18 V
CC
°
V
C
CC
).
94
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IW4050B
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
IH
IL
OH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
V
= V
OUT
V
= V
OUT
V
= V
OUT
V
= 0.5V
OUT
V
= 1.0 V
OUT
V
= 1.5V
OUT
VIN= V
CC
CC
CC
CC
- 0.5V
- 1.0 V
- 1.5V
Output Voltage
V
OL
Maximum Low-Level
VIN=GND 5.0
Output Voltage
I
IN
Maximum Inp ut
VIN= GND or V
CC
Leakage Current
I
CC
Maximum Quiescen t
VIN= GND or V
CC
Supply Current
(per Package)
I
OL
I
OH
Minimum Output Low
(Sink) Current
Minimum Output
High (Source) Current
VIN= GND or V
UOL=0.4 V
U
=0.4 V
OL
U
=0.5 V
OL
U
=1.5 V
OL
VIN= GND or V
UOH=2.5 V
U
=4.6 V
OH
U
=9.5 V
OH
U
=13.5 V
OH
CC
CC
V
5.0
10
15
5.0
10
15
5.0
10
15
10
15
18
5.0
10
15
20
4.5
10
15
5.0
5.0
10
15
CC
5
Guaranteed Limit
≥
-55°C25°C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
14.95
0.05
0.05
0.05
±
0.1
1
2
4
20
3.3
4
10
26
-2.6
-0.81
-2.0
-0.65
-1.65
-5.2
3.5
7
11
1.5
3
4
4.95
9.95
0.05
0.05
0.05
±
0.1
1
2
4
20
2.6
3.2
8
24
-2.1
-4.3
≤
125
°
C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±
1.0
30
60
120
600
1.8
2.4
5.6
18
-1.55
-0.48
-1.18
-3.1
Unit
V
V
V
V
µ
A
µ
A
mA
mA
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Page 4
IW4050B
AC ELECTRICAL CHARACTERISTICS
(CL=50pF, RL=200kΩ, Input tr=tf=20 ns)
V
IN
Symbol Parameter V V
t
PLH
Maximum Propagation Delay, Input A to
Output Y (Figure 1)
5
10
10
15
15
t
PHL
Maximum Propagation Delay, Input A to
Output Y (Figure 1)
5
10
10
15
15
t
TLH
Maximum Output Transition Time, Any
Output (Figure 1)
5
10
15
t
THL
Maximum Output Transition Time, Any
Output (Figure 1)
5
10
15
C
IN
Maximum Input Capacitance - - 7.5 pF
V
CC
5
10
5
15
5
5
10
5
15
5
5
10
15
5
10
15
Guaranteed Limit
≥
-55°C25°C
140
80
90
60
80
110
55
100
30
100
160
80
60
60
40
30
140
80
90
60
80
110
55
100
30
100
160
80
60
60
40
30
≤
125°C
280
160
180
120
160
220
110
200
60
200
320
160
120
120
80
60
Unit
ns
ns
ns
ns
96
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/6 of the Device)
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