Datasheet ITF87012SVT Datasheet (Intersil)

ITF87012SVT

Data Sheet March 2000

6A, 20V, 0.035 Ohm, N-Channel,

2.5V Specified Power MOSFET
Packaging

TSOP-6

1

2

3

4

Symbol

DRAIN(1)

DRAIN(2)

GATE(3)

DRAIN(6)

DRAIN(5)

SOURCE(4)

File Number 4810.2

Features

• Ultra Low On-Resistance

-r

-r

-r

= 0.035Ω, VGS= 4.5V

DS(ON)

= 0.038Ω, VGS= 4.0V

DS(ON)

= 0.045Ω, VGS= 2.5V

DS(ON)

• 2.5 V Gate Drive Capability

• Small Profile Package

• Gate to Source Protection Diode

• Simulation Models

- Temperature Compensated PSPICE™ and SABER
Electrical Models

- Spice and SABER Thermal Impedance Models

- www.intersil.com

• Peak Current vs Pulse Width Curve

• Transient Thermal Impedance Curve vs Board Mounting
Area

• Switching Time vs R

GS

Curves

Ordering Information

PART NUMBER PACKAGE BRAND

ITF87012SVT TSOP-6 (SC-95) 012

NOTE: Whenordering, usethe entire part number. ITF87012SVTis
available only in tape and reel.

Absolute Maximum Ratings T

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain Current

Continuous (TA= 25oC, VGS = 4.5V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TA= 25oC, VGS = 4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TA= 100oC, VGS = 4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TA= 100oC, VGS = 2.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief TB370. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

NOTES:

1. TJ = 25oC to 125oC.

2. 62.5oC/W measured using FR-4 board with 0.40 in2 (258.1 mm2) copper pad at 2 second.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

= 25oC, Unless Otherwise Specified

A

DSS

DGR

GS

DM

STG

pkg

ITF87012SVT UNITS

20 V
20 V

±12V

D
D
D
D

D

L

6.0

5.5

3.5

3.0

Figure 4

2

16

-55 to 150

300
260

A
A
A
A
A

W

mW/oC

o

C

o

C

o

C

1

CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.

SABER© is a Copyright of Analogy Inc., PSPICE® is a registered trademark of MicroSim Corporation.

www.intersil.com or 321-724-7143

| Copyright © Intersil Corporation 2000

ITF87012SVT

Electrical Specifications T

= 25oC, Unless Otherwise Specified

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Ambi­ent

SWITCHING SPECIFICATIONS (VGS = 2.5V)
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charge Q
Gate Charge at 2V Q
Threshold Gate Charge Q
Gate to Source Gate Charge Q
Gate to Drain “Miller” Charge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

DSSID

DSS

GSS

GS(TH)VGS

DS(ON)ID

VDS = 20V, VGS = 0V - - 10 µA
VGS = ±12V - - ±10 uA

ID = 3.5A, VGS = 4.0V (Figure 8) - 0.029 0.038 Ω
ID = 3.0A, VGS = 2.5V (Figure 8) - 0.037 0.045 Ω

R

θJA

Pad Area = 0.40 in2(258.1 mm2) (Note 2) - - 62.5oC/W
Pad Area = 0.0163 in2 (10.54 mm2) (Figure 20) - - 198.2oC/W
Pad Area = 0.0056 in2 (3.60 mm2) (Figure 20) - - 218.4oC/W

d(ON)

d(OFF)

d(ON)

d(OFF)

g(TOT)VGS

g(2)

g(TH)

ISS
OSS
RSS

VDD = 10V, ID = 3.0A
VGS= 2.5V,

r

RGS = 15 Ω
(Figures 14, 18, 19 )

f

VDD = 10V, ID = 6.0A
VGS= 4.5V,

r

RGS = 16 Ω
(Figures 15, 18, 19 )

f

VGS = 0V to 2V - 4.0 - nC
VGS = 0V to 0.5V - 0.30 - nC

gs

gd

VDS = 10V, VGS = 0V,
f = 1MHz
(Figures 12 )

= 250µA, VGS = 0V (Figure 11) 20 - - V

= VDS, ID = 250µA (Figure 10) 0.5 - 1.5 V

= 6.0A, VGS = 4.5V (Figures 8, 9) - 0.028 0.035 Ω

-79-ns

- 315 - ns

- 154 - ns

- 188 - ns

-42-ns

- 142 - ns

- 236 - ns

- 200 - ns

= 0V to 4.5V VDD = 10V,

- 7.7 - nC
ID = 5.5A,
I

= 1.0mA

g(REF)

(Figures 13, 16, 17 )

- 1.1 - nC

- 2.7 - nC

- 655 - pF

- 227 - pF

- 118 - pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q

2

SD

rr

RR

ISD = 5.5A - 0.84 - V
ISD = 5.5A, dISD/dt = 50A/µs - 22 - ns
ISD = 5.5A, dISD/dt = 50A/µs - 6.1 - nC

Typical Performance Curves

ITF87012SVT

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

125

TA, AMBIENT TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWERDISSIPATION vs AMBIENT

TEMPERATURE

3

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJA

0.01

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.001

-5

10

-4

10

-3

10

-2

10

t, RECTANGULAR PULSE DURATION (s)

8

6

VGS= 4.5V, R

= 62.5oC/W

θJA

4

, DRAIN CURRENT (A)

D

I

2

VGS= 2.5V, R

= 218.4oC/W

θJA

0

25

50 75 100 125 150

TA, AMBIENT TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

AMBIENT TEMPERATURE

R

= 62.5oC/W

θJA

P

DM

t

1

t

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

0

10

1

10

θJA

1/t2

x R

10

θJA

2

+ T

2

A

3

10

500

100

VGS = 2.5V

10

, PEAK CURRENT (A)

DM

I

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

1

-5

10

VGS = 4.5V

-4

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

R

= 62.5oC/W

θJA

-3

10

-2

10

-1

10

0

10

10

t, PULSE WIDTH (s)

FIGURE 4. PEAK CURRENT CAPABILITY

3

TA = 25oC
FOR TEMPERATURES
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

I = I

1

150 - T

25

125

2

10

A

3

10

Typical Performance Curves (Continued)

ITF87012SVT

200

100

10

, DRAIN CURRENT (A)

OPERATION IN THIS

D

I

AREA MAY BE
LIMITED BY r

R

1

1

θJA

V

DS

DS(ON)

= 62.5oC/W

, DRAIN TO SOURCE VOLTAGE (V)

SINGLE PULSE
TJ = MAX RATED

= 25oC

T

A

100µs

1ms

10ms

10 50

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

20

15

10

, DRAIN CURRENT (A)

5

D

I

0

0 0.5 1.0 2.0

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TA = 25oC

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 4.5V
VGS = 3V

VGS = 2.5V

VGS = 2V

VGS = 1.5V

1.5

20

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 15V

V

DD

15

10

DRAIN CURRENT (A)

D,

5

I

0

0.5 2.0 2.5 3.0

TJ = 150oC

1.0 1.5
VGS, GATE TO SOURCE VOLTAGE (V)

TJ = 25oC

TJ = -55oC

FIGURE 6. TRANSFER CHARACTERISTICS

100

80

ID = 6A

60

, DRAIN TO SOURCE

ON RESISTANCE (mΩ)

DS(ON)

r

ID =3A

40

20

12345

, GATE TO SOURCE VOLTAGE (V)

V

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

1.6

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.4

1.2

1.0

ON RESISTANCE

0.8

NORMALIZED DRAIN TO SOURCE

0.6

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

VGS = 4.5V, ID = 6A

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.4

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

4

Typical Performance Curves (Continued)

1.10
ID = 250µA

1.05

ITF87012SVT

1500

1000

C

ISS

= CGS + C

GD

1.00

0.95

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.90

-80 -40 0 40 80 120 160
T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 11. NORMALIZED DRAIN TOSOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

5

VDD = 10V

4

3

2

WAVEFORMS IN

1

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

04610

2

, GATE CHARGE (nC)

Q

g

DESCENDING ORDER:

ID = 5.5A

=3A

I

D

8

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. GATECHARGE WAVEFORMS FOR CONSTANT

GATE CURRENT

C

≅ CDS+ C

OSS

C, CAPACITANCE (pF)

100

VGS= 0V, f = 1MHz

50

0.1 1.0 10 20
VDS, DRAIN TO SOURCE VOLTAGE (V)

GD

C

RSS

=

C

GD

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

500

VGS = 2.5V, VDD = 10V, ID = 3.0A

400

300

200

SWITCHING TIME (ns)

100

0

0 1020304050

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

r

t

f

t

d(ON)

t

d(OFF)

FIGURE 14. SWITCHING TIME vs GATE RESISTANCE

400

300

200

SWITCHING TIME (ns)

100

5

t

VGS = 4.5V, VDD = 10V, ID = 6A

t

0

0 1020304050

RGS, GATE TO SOURCE RESISTANCE (Ω)

d(ON)

d(OFF)

t

f

t

r

FIGURE 15. SWITCHING TIME vs GATE RESISTANCE

Test Circuits and Waveforms

V

DS

V

GS

I

g(REF)

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS

DUT

ITF87012SVT

R

L

+

V

DD

-

V

DD

V

GS

VGS= 0.5V
0

I

g(REF)

0

Q

g(TOT)

V

DS

VGS= 4.5V

Q

g(2)

VGS = 2V

Q

g(TH)

Q

gs

Q

gd

R

L

V

DS

+

-

0V

V

GS

V

GS

R

GS

DUT

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the thermal
resistance of the heat dissipating path determines the maximum
allowable de vice po wer dissipation, P
Therefore the application’ s ambient temperature , T
thermal resistance R
that T

is never e xceeded. Equation 1 mathematically

JM

(oC/W) must be reviewed to ensure

θJA

represents the relationship and serves as the basis for
establishing the rating of the part.

P

TJMTA–()

------------------------------ -=

DM

Z

θJA

In using surface mount devices such as the TSOP-6
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
complex and influenced by many factors:

, in an application.

DM

(oC), and

A

DM

(EQ. 1)

is

t

ON

t

d(ON)

t

V

DS

0

V

GS

10%

0

r

90%

10%

50%

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.

2. The number of copper layersand the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. Fornonsteadystateapplications,thepulsewidth,theduty
cycle and the transient thermal response of the part, the
board and the environment they are in.

Intersil provides thermal information to assist the designer’s
preliminary application evaluation.Figure 20 defines the R

θJA

for the device as a function of the top copper (component
side) area. This is for a horizontally positioned FR-4 board
with 1oz copper after 1000 seconds of steady state power

6

ITF87012SVT

with no air flow. This graph provides the necessary
information for calculation of the steady state junction
temperature or power dissipation. Pulse applications can be
evaluated using the Intersil device Spice thermal model or
manuallyutilizing the normalizedmaximum transientthermal
impedance curve.

Displayed on the curve are R

values listed in the Electrical

θJA

Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, P

DM

.

Thermal resistances corresponding to other copper areas can
be obtained from Figure 20 or by calculation using Equation 2.
R

is defined as the natural log of the area times a coefficient

θJA

added to a constant. The area, in square inches is the top
copper area including the gate and source pads.

R

The transient thermal impedance (Z

120.6 18.9 Area()

θJA

ln–=

) is also effected by

θJA

(EQ. 2)

varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.

Copper pad area has no perceivable eff ect on tr ansient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore ,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.

260

R

= 120.6- 18.9*ln(AREA)

240

220

C/W)

200

o

(

θJA

180

R

160

140

120

0.001
AREA, TOP COPPER AREA (in2)

FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA

θJA

218.4oC/W - 0.0056in

198.2oC/W - 0.0163in

0.01

2

2

0.1 1.0

200

160

C/W)

o

120

, THERMAL

80

θJA

Z

IMPEDANCE (

40

0

10

COPPER BOARD AREA - DESCENDING ORDER

2

0.02 in

2

0.05 in

2

0.10 in

2

0.25 in

2

0.40 in

-1

0

10

FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA

1

10

t, RECTANGULAR PULSE DURATION (s)

2

10

3

10

7

PSPICE Electrical Model

.SUBCKT ITF87012SVT 2 1 3 ; REV 25 Jan 2000

CA 12 8 11.00e-10
CB 15 14 9.50e-10
CIN 6 8 5.25e-10

ITF87012SVT

7

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

DRAIN

SOURCE

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD1 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 27.41
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 1.00e-9

LGATE 1 9 1.04e-9
LSOURCE 3 7 1.29e-10

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

GATE

1

LGATE

RLGATE

RGATE

9

DESD1
91
DESD2

ESG

EVTEMP
+

20

DPLCAP

10

RSLC2

-

6
8

EVTHRES

+

+

6

-

18
22

5

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

11

+

17
18

-

RSLC1

51

+

5

ESLC

51

-

50
RDRAIN

16
21

-

19

8

MSTRO

CIN

8

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.00e-3
RGATE 9 20 118
RLDRAIN 2 5 10
RLGATE 1 9 9 10.4
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 17.00e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD

CA

S1A

12

13

8

S1B

EGS EDS

S2A

6
8

S2B

15

CB

14

+

5
8

-

14
13

13

+

+

-

-

RBREAK

17 18

IT

8

RVTHRES

RVTEMP
19

-

VBAT

+

22

S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*175),2))}
.MODEL DBODYMOD D (IS = 3.48e-11 IKF = 0.15 XT I= 0.18 RS = 1.47e-2 TRS1 = 1.25e-3 TRS2 = 0 CJO = 3.67e-10 TT = 2.20e-8 M = 0.52)

.MODEL DBREAKMOD D (RS = 9.52e-2 TRS1 = 1.05e-3 TRS2 = 1.13e-6)
.MODEL DESD1MOD D (BV = 8.2 Tbv1= -1.87e-3 N= 12 RS = 20)
.MODEL DESD2MOD D (BV = 11.5 Tbv1= -2.01e-3 N= 8 RS = 20)
.MODEL DPLCAPMOD D (CJO = 4.91e-10 IS = 1e-30 M = 0.59)
.MODEL MMEDMOD NMOS (VTO = 1.10 KP = 2.60 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 118)
.MODEL MSTROMOD NMOS (VTO = 1.29 KP = 58 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 0.86 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1180 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 7.58e-4 TC2 = -1.43e-6)
.MODEL RDRAINMOD RES (TC1 = 2.21e-2 TC2 = 2.72e-5)
.MODEL RSLCMOD RES (TC1 = 1.21e-3 TC2 = 1.00e-5)
.MODEL RSOURCEMOD RES (TC1 = 1.00e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.01e-3 TC2 = -1.01e-6)
.MODEL RVTEMPMOD RES (TC1 = -8.40e-4 TC2 = 0)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.5 VOFF= -3.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.0 VOFF= -3.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF= 0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -1.5)

.ENDS

2

3

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

8

ITF87012SVT

SABER Electrical Model

REV 25 Jan 2000
template itf87012svt n2,n1,n3

electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 3.48e-11,ikf = 0.15,xti = 0.18,rs = 1.47e-2,trs1 = 1.25e-3,trs2 = 0,cjo = 3.67e-10,tt = 2.20e-8,m = 0.52)
dp..model dbreakmod = (rs = 9.52e-2,trs1 = 1.05e-3,trs2 = 1.13e-6)
dp..model desd1mod = (bv = 8.2,tbv1 = -1.87e-3,n1 = 12,rs = 20)
dp..model desd2mod = (bv = 11.5,tbv1 = -2.01e-3,n1 = 8,rs = 20)
dp..model dplcapmod = (cjo = 4.91e-10,is = 1e-30,m = 0.59)
m..model mmedmod = (type=_n, vto = 1.01,kp = 2.60,is = 1e-30,tox = 1)
m..model mstrongmod = (type=_n, vto = 1.29, kp = 58, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 0.86, kp = 0.10, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -3.5, voff = -3.0)

DPLCAP

10

sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3.0, voff = -3.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -1.5)

RSLC2

c.ca n12 n8 = 11.00e-10
c.cb n15 n14 = 9.50e-10
c.cin n6 n8 = 5.25e-10

dp.dbody n7 n71 = model=dbodymod
dp.dbreak n72 n11 = model=dbreakmod
dp.desd1 n91 n9 = model=desd1mod
dp.desd2 n91 n7 = model=desd2mod
dp.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1
l.ldrain n2 n5 = 1.00e-9

GATE

1

LGATE

RLGATE

RGATE

9

DESD1
91
DESD2

ESG

EVTEMP
+

18
22

20

+

-

-

6
8

EVTHRES

+

6

l.lgate n1 n9 = 1.04e-9
l.lsource n3 n7 = 1.29e-10

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1 = 7.58e-4, tc2 = -1.43e-6
res.rdrain n50 n16 = 2.00e-3, tc1 = 2.21e-2, tc2 = 2.75e-5
res.rgate n9 n20 = 118
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 10.4
res.rlsource n3 n7 = 1.29

CA

S1A

12

S1B

EGS EDS

S2A

13

14

8

13

S2B

13

+

+

6
8

-

-

res.rslc1 n5 n51 = 1e-6, tc1 = 1.21e-3, tc2 = 1.00e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 17.00e-3, tc1 = 1.00e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -8.40e-4, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -2.01e-3, tc2 = -1.01e-6

spe.ebreak n11 n7 n17 n18 = 27.41
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1
equations {

i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/175))** 2))
}
}

5

RSLC1

51

ISCL

MMED

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

-

50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5
8

-

7

RLSOURCE

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

9

SPICE Thermal Model

REV 24 Jan 2000
ITF87012SVT
Copper Area = 0.02 in

2

CTHERM1 th 8 1.10e-3
CTHERM2 8 7 5.00e-3
CTHERM3 7 6 7.00e-3
CTHERM4 6 5 9.00e-3
CTHERM5 5 4 1.10e-2
CTHERM6 4 3 4.00e-2
CTHERM7 3 2 3.00e-1
CTHERM8 2 tl 1.50

RTHERM1 th 8 0.25
RTHERM2 8 7 0.60
RTHERM3 7 6 1.25
RTHERM4 6 5 8.00
RTHERM5 5 4 10.00
RTHERM6 4 3 43.00
RTHERM7 3 2 48.00
RTHERM8 2 tl 50.00

SABER Thermal Model

Copper Area = 0.02 in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 1.10e-3
ctherm.ctherm2 8 7 = 5.00e-3
ctherm.ctherm3 7 6 = 7.00e-3
ctherm.ctherm4 6 5 = 9.00e-3
ctherm.ctherm5 5 4 = 1.10e-2
ctherm.ctherm6 4 3 = 4.00e-2
ctherm.ctherm7 3 2 = 3.00e-1
ctherm.ctherm8 2 tl = 1.50

rtherm.rtherm1 th 8 = 0.25
rtherm.rtherm2 8 7 = 0.60
rtherm.rtherm3 7 6 = 1.25
rtherm.rtherm4 6 5 = 8.00
rtherm.rtherm5 5 4 = 10.00
rtherm.rtherm6 4 3 = 43.00
rtherm.rtherm7 3 2 = 48.00
rtherm.rtherm8 2 tl = 50.00
}

2

ITF87012SVT

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

th

8

7

6

5

4

3

2

tl

JUNCTION

CTHERM1

CTHERM2

CTHERM3

CTHERM4

CTHERM5

CTHERM6

CTHERM7

CTHERM8

CASE

TABLE 1. Thermal Models

COMPONANT 0.02 in

2

0.05 in

2

0.10 in

2

0.25 in

2

0.40 in

CTHERM6 4.00e-2 4.00e-2 4.20e-2 4.00e-2 4.00e-2
CTHERM7 3.00e-1 3.50e-1 3.30e-1 3.00e-1 2.80e-1
CTHERM8 1.50 1.50 1.50 1.50 1.50
RTHERM6 43 35 35 27 27
RTHERM7 48 40 37 30 29
RTHERM8 50 45 42 45 37

10

2

MO-193AA (TSOP-6)

6 LEAD JEDEC MO-193AA TSOP PLASTIC PACKAGE
(SIMILAR TO SSOT™-6)

E

E

1

64

D

b

0.039

1.00

0.024

0.60

3

L

0.095

2.40

e

0o-8

0.037

0.95

C

0.004in

o

0.10mm

0.075

1.90

ITF87012SVT

A

1

INCHES MILLIMETERS

SYMBOL

NOTESMIN MAX MIN MAX

A 0.035 0.043 0.90 1.10

A

1

0.004 0.10
b 0.012 0.020 0.30 0.50
c 0.003 0.008 0.08 0.20

D 0.107 0.122 2.70 3.10 2
E 0.103 0.118 2.60 3.00

E

1

0.056 0.070 1.40 1.80 3
e 0.037 BSC 0.95 BSC
L 0.014 0.021 0.35 0.55 4

NOTES:

1. All dimensions are within the allowable dimensions of Rev.B of
JEDEC MO-193AA outline dated 10-99.

2. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.006 inches (0.15mm) per side.

3. Dimension "E " does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.006 inches
(0.15mm) per side.

4. "L" is the length of terminal for soldering.

5. Controlling dimension: Millimeter.

6. Revision 1 dated 2-00.

MO-193AA (TSOP-6)

8mm TAPE AND REEL

COVER TAPE

USER DIRECTION OF FEED

1.5mm DIAMETER HOLE

6.0mm

4.0mm

2.0mm

3.5mm

4.0mm

17.0mm

13.0mm

178mm

13.0mm

GENERAL INFORMATION

1. 3000 PIECES PER REEL.

2. ORDER IN MULTIPLES OF FULL REELS ONLY.

3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.

1.75mm

C

L

60mm

11

SSOT™-6 is a trademark of Fairchild Semiconductor.

ITF87012SVT

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

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P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

12

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