Datasheet ITF87008DQT Datasheet (Intersil)

ITF87008DQT

Data Sheet March 2000

7.0A, 20V, 0.023 Ohm, Dual N-Channel,

2.5V Specified Power MOSFET
Packaging

TSSOP-8

5

1

2

4

3

Symbol

DRAIN1(1)
SOURCE1(2)
SOURCE1(3)

GATE1(4)

(8) DRAIN2
(7) SOURCE2
(6) SOURCE2
(5) GATE2

File Number 4814.2

Features

• Ultra Low On-Resistance

-r

-r

-r

= 0.023Ω, VGS= 4.5V

DS(ON)

= 0.024Ω, VGS= 4.0V

DS(ON)

= 0.029Ω, VGS= 2.5V

DS(ON)

• 2.5 Volt Gate Drive Capability

• Gate to Source Protection Diode

• Simulation Models

- Temperature Compensated PSPICE™ and SABER
Electrical Models

- Spice and SABER Thermal Impedance Models

- www.intersil.com

• Peak Current vs Pulse Width Curve

• Transient Thermal Impedance Curve vs Board Mounting
Area

• Switching Time vs R

GS

Curves

Ordering Information

PART NUMBER PACKAGE BRAND

ITF87008DQT TSSOP-8 87008

NOTE: When ordering, use the entirepart number. ITF87008DQT2
is available only in tape and reel.

Absolute Maximum Ratings T

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain Current

Continuous (TA = 25oC, VGS = 4.5V) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TA = 25oC, VGS = 4.0V) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TA = 100oC, VGS = 4.0V) (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TA = 100oC, VGS = 2.5V) (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief TB370. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

NOTES:

1. TJ = 25oC to 125oC.

2. 62.5oC/W measured using FR-4 board with 0.50 in2(322.6 mm2) copper pad at 1 second.

3. 230oC/W measured using FR-4 board with 0.0022 in2 (1.44 mm2) copper pad at 1000 seconds.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

= 25oC, Unless Otherwise Specified

A

DSS

DGR

GS

DM

STG

pkg

ITF87008DQT UNITS

20 V
20 V

±12 V

D
D
D
D

D

L

7.0

7.0

2.0

2.0

Figure 4

2.0
16

-55 to 150

300
260

A
A
A
A

W

mW/oC

o

C

o

C

o

C

1

CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.

SABER© is a Copyright of Analogy Inc. PSPICE® is a registered trademark of MicroSim Corporation.

1-888-INTERSIL or 321-724-7143

| Copyright © Intersil Corporation 2000

ITF87008DQT

Electrical Specifications T

= 25oC, Unless Otherwise Specified

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

THERMAL SPECIFICATIONS

Thermal Resistance Junction to
Ambient

SWITCHING SPECIFICATIONS VGS = 2.5V
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
SWITCHING SPECIFICATIONS VGS = 4.5V
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charge Q
Gate Charge at 2V Q
Threshold Gate Charge Q
Gate to Source Gate Charge Q
Gate to Drain “Miller” Charge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

DSSID
DSS
GSS

GS(TH)VGS

DS(ON)ID

VDS = 20V, VGS = 0V - - 10 µA
VGS = ±12V - - ±10 µA

ID = 2.0A, VGS = 4.0V Figure 8 - 0.018 0.024 Ω
ID = 2.0A, VGS = 2.5V Figure 8 - 0.022 0.029 Ω

R

θJA

Pad Area = 0.50 in2(322.6 mm2) (Note 2) - - 62.5oC/W
Pad Area = 0.017 in2 (11.2 mm2) Figure 20 - - 199
Pad Area = 0.0022 in2 (1.44 mm2) Figure 20 - - 230

d(ON)

VDD = 10V, ID = 2.0A
VGS= 2.5V,

r

RGS = 12Ω

d(OFF)

d(ON)

Figures 14, 18, 19

f

VDD = 10V, ID = 7.0A
VGS= 4.5V,

r

RGS = 13Ω

d(OFF)

g(TOT)VGS

g(2)

g(TH)

ISS

Figures 15, 18, 19

f

VGS = 0V to 2.0V - 5.7 - nC
VGS = 0V to 0.5V - 0.5 - nC

gs

gd

VDS = 10V, VGS = 0V,
f = 1MHz

OSS
RSS

Figure 12

= 250µA, VGS = 0V Figure 11 20 - - V

= VDS, ID = 250µA Figure 10 0.5 - 1.5 V

= 7.0A, VGS = 4.5V Figures 8,9 - 0.017 0.023 Ω

o

C/W

o

C/W

- 110 - ns

- 475 - ns

- 180 - ns

- 265 - ns

-60-ns

- 185 - ns

- 300 - ns

- 280 - ns

= 0V to 4.5V VDD = 10V,

- 9.7 - nC
ID = 7.0A,
I

= 1.0mA

g(REF)

Figures 13, 16, 17

- 1.1 - nC

- 2.9 - nC

- 980 - pF

- 300 - pF

- 160 - pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q

2

SD
rr
RR

ISD = 7.0A - 0.83 - V
ISD = 7.0A, dISD/dt = 15A/µs - 44 - ns
ISD = 7.0A, dISD/dt = 15A/µs - 2.2 - nC

Typical Performance Curves

ITF87008DQT

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

125

TA, AMBIENT TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT

TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

1

0.5

0.2

0.1

0.05

0.02

0.1

0.01

, NORMALIZED

θJA

Z

0.01

THERMAL IMPEDANCE

0.001

-5

10

-4

10

10

-3

SINGLE PULSE

-2

10

t, RECTANGULAR PULSE DURATION (s)

8

6

VGS= 4.5V, R

= 62.5oC/W

θJA

4

, DRAIN CURRENT (A)

D

2

I

VGS= 2.5V, R

= 230oC/W

θJA

0

25

50 75 100 125 150

TA, AMBIENT TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

AMBIENT TEMPERATURE

R

θJA

P

DM

t

1

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

0

10

1

10

θJA

1/t2

x R

10

θJA

2

+ T

= 230oC/W

t

2

A

3

10

400

100

, PEAK CURRENT (A)

DM

I

VGS = 4.5V

10

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

2

-5

10

VGS = 2.5V

-4

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

R

= 230oC/W

θJA

-3

10

-2

10

-1

10

0

10

10

t, PULSE WIDTH (s)

FIGURE 4. PEAK CURRENT CAPABILITY

3

TC = 25oC
FOR TEMPERATURES
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

I = I

1

150 - T

25

125

2

10

A

3

10

Typical Performance Curves (Continued)

ITF87008DQT

200
100

10

OPERATION IN THIS
AREA MAY BE

1

, DRAIN CURRENT (A)

LIMITED BY r

D

I

R

= 230oC/W

0.1

θJA

V

DS

DS(ON)

, DRAIN TO SOURCE VOLTAGE (V)

SINGLE PULSE
TJ = MAX RATED

= 25oC

T

A

10 401

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

25

20

15

VGS = 4.5V
V

= 3.0V

GS

V

= 2.5V

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TA = 25oC

VGS = 2.0V

100µs

1ms

10ms

25

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

V

= 15V

DD

20

15

10

DRAIN CURRENT (A)

D,

I

5

0

0.5 1.0 1.5 2.0 2.5
VGS, GATE TO SOURCE VOLTAGE (V)

TJ = 150oC

TJ = -55oC

TJ = 25oC

FIGURE 6. TRANSFER CHARACTERISTICS

40

35

30

ID = 1A

ID = 7A

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

10

, DRAIN CURRENT (A)

D

I

5

VGS = 1.5V

0

0 0.5 1.0 2.0

VDS, DRAIN TO SOURCE VOLTAGE (V)

1.5

25

, DRAIN TO SOURCE

ON RESISTANCE (mΩ)

20

DS(ON)

r

15

12345

, GATE TO SOURCE VOLTAGE (V)

V

GS

FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

1.6

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.4

1.2

1.0

ON RESISTANCE

0.8

NORMALIZED DRAIN TO SOURCE

0.6

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

VGS = 4.5V, ID = 7A

1.4

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

4

FIGURE 10. NORMALIZED GATETHRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

Typical Performance Curves (Continued)

ITF87008DQT

1.10
ID = 250µA

1.05

1.00

0.95

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.90

-80 -40 0 40 80 120 160
, JUNCTION TEMPERATURE (oC)

T

J

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

5

VDD = 10V

4

3

2

WAVEFORMS IN

1

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

036912

, GATE CHARGE (nC)

Q

g

DESCENDING ORDER:

ID = 7A

= 1A

I

D

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT

GATE CURRENT

2000

C

= CGS + C

ISS

1000

C

OSS

C, CAPACITANCE (pF)

C

= C

RSS

VGS= 0V, f = 1MHz

100

0.1 1.0 10 20
VDS, DRAIN TO SOURCE VOLTAGE (V)

GD

≅ CDS+ C

GD

GD

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

600

VGS = 2.5V, VDD = 10V, ID = 2A

500

400

300

200

SWITCHING TIME (ns)

100

0

0 1020304050

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

r

t

d(OFF)

t

d(ON)

t

f

FIGURE 14. SWITCHING TIME vs GATE RESISTANCE

400

300

200

SWITCHING TIME (ns)

100

5

VGS = 4.5V, VDD = 10V, ID = 7A

t

d(OFF)

t

f

t

r

t

d(ON)

0

0 1020304050

RGS, GATE TO SOURCE RESISTANCE (Ω)

FIGURE 15. SWITCHING TIME vs GATE RESISTANCE

Test Circuits and Waveforms

V

DS

V

GS

I

g(REF)

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS

DUT

ITF87008DQT

V

R

L

+

V

DD

-

DD

Q

V

GS

VGS= 0.5V

0

I

g(REF)

Q

g(TH)

Q

gs

0

V

g(2)

Q

DS

gd

Q

g(TOT)

VGS= 4.5V

VGS = 2V

t

ON

t

d(ON)

90%

50%

t

10%

r

PULSE WIDTH

0V

R

L

V

DS

V

GS

V

GS

+

-

R

GS

DUT

V

DS

0

V

GS

10%

0

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

6

ITF87008DQT

Thermal Resistance vs Mounting Pad Area

Themaximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
an application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T

(oC), and thermal resistance R

A

is never exceeded.

JM

Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.

TJMTA–()

------------------------------ -=

P

DM

R

θJA

In using surface mount devices such as the TSSOP-8
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
complex and influenced by many factors:

1. Mounting pad area onto which the deviceis attached and
whether there is copper on one side or both sides of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.

Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the

for the device as a function of the top copper

R

θJA

(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalizedmaximum
transient thermal impedance curve.

Displayed on the curve are R

values listed in the

θJA

Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P

.

DM

Thermal resistances corresponding to other copper areas
can be obtained from Figure 20 or by calculation using
Equation 2. R

is defined as the natural log of the area

θJA

times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.

R

138.68 14.95 Area()

θJA

ln×–=

θJA

, in

DM

(oC/W)

(EQ. 1)

is

DM

(EQ. 2)

300

230oC/W - 0.0022in

250

200

C/W)

o

(

150

θJA

, R

θβ

100

R

50

Rθβ= 63.46 - 15.08 * ln(AREA)

0

0.001 0.01 0.1 1
AREA, TOP COPPER AREA (in2) PER DIE

FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA

R

= 138.68- 14.95 * ln(AREA)

θJA

2

199oC/W - 0.017in

2

While Equation 2 describes the thermal resistance of a
single die, several devices are offered with two die in the
TSSOP-8 package. The dual die TSSOP-8 package
introduces an additional thermal component, thermal
coupling resistance,

R

. Equation 3 describes Rθβ as a

θβ

function of the top copper mounting pad area.

R

θβ

63.46 15.08 Area()ln×–=

(EQ. 3)

The thermal coupling resistance vs copper area is also
graphically depicted in Figure 20. It is important to note the
thermal resistance (R
(

R

) are equivalent for both die. For example at 0.1 square

θβ

) and thermal coupling resistance

θJA

inches of copper:
R

= R

θJA1

R

= R

θβ1

and TJ2 define the junction temperature of the

T

J1

respective die. Similarly, P

θJA2

= 98oC/W

θβ2

= 173oC/W

and P2 define the power

1

dissipated in each die. The steady state junction
temperature can be calculated using Equation 4 for die 1
and Equation 5 for die 2.

Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5W and die 1 is dissipating 0W.
The ambient temperature is 70

o

C and the package is
mounted to a top copper area of 0.1 square inches per die.
Use Equation 4 to calculate T
T

.

J2

.

T

J1P1RθJAP2

R

++=

θβ

and Equation 5 to calculate

J1

T

A

(EQ. 4)

TJ1 = (0W)(173oC/W) + (0.5W)(98oC/W) + 70oC

= 119oC

T

J1

R

θβ

T

A

(EQ. 5)

T

J2P2RθJAP1

= (0.5W)(173oC/W) + (0W)(98oC/W) + 70oC

T

J2

++=

TJ2 = 156.5oC

7

ITF87008DQT

The transient thermal impedance (Z

) is also affected by

θJA

varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.

200

COPPER BOARD AREA - DESCENDING ORDER

2

0.02 in

2

0.14 in

150

C/W)

o

100

, THERMAL

θJA

Z

IMPEDANCE (

50

0

10

0.26 in

0.38 in

0.50 in

-1

2
2
2

0

10

t, RECTANGULAR PULSE DURATION (s)

FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA

Copper pad area has no perceivable eff ect on tr ansient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore ,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.

10

1

10

2

10

3

8

ITF87008DQT

PSPICE Electrical Model

.SUBCKT ITF87008DQT 2 1 3 ; REV 18 Jan 2000

CA 12 8 1.17e-9
CB 15 14 1.17e-9
CIN 6 8 8.15e-10

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 27.05
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 1.0e-9

LGATE 1 9 1.04e-9
LSOURCE 3 7 1.29e-10

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1

GATE

1

LGATE

RLGATE

RGATE

9

DESD1
91
DESD2

ESG

EVTEMP
+

20

DPLCAP

10

RSLC2

-

6
8

EVTHRES

+

+

6

-

18
22

5

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

11

+

17
18

-

RSLC1

51

+

5

ESLC

51

-

50
RDRAIN

16
21

-

19

8

MSTRO

CIN

8

RDRAIN 50 16 RDRAINMOD 2.8e-3
RGATE 9 20 118.9
RLDRAIN 2 5 10
RLGATE 1 9 9 10.4
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 12.8e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

CA

S1A

12

13

8

S1B

EGS EDS

S2A

15

14
13

S2B

13

+

+

6
8

-

-

CB

14

+

5
8

-

RBREAK

17 18

IT

8

RVTHRES

VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*185),2))}
.MODEL DBODYMOD D (IS = 2.0e-10 RS = 1.34e-2 TRS1 = 1.1e-3 TRS2 = 2.0e-6 IKF= 2.3 XTI = 0 N=1.12 CJO = 3.9e-10 TT = 8.0e-9 M = 0.43)

.MODEL DBREAKMOD D (RS = 2.3e-1 TRS1 = 4.0e-3 TRS2 = -6.0e-6)
.MODEL DESD1MOD D (BV = 11.0 Tbv1= -2.32e-3 N= 12 RS = 35)
.MODEL DESD2MOD D (BV = 11.1 Tbv1= -2.32e-3 N= 12 RS = 35)
.MODEL DPLCAPMOD D (CJO = 7.28e-10 IS = 1e-30 VJ = 0.40 M = 0.46)
.MODEL MMEDMOD NMOS (VTO = 1.11 KP = 19 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 118.9 RS = 0.09)
.MODEL MSTROMOD NMOS (VTO = 1.39 KP = 107 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u LAMBDA = 0.018)
.MODEL MWEAKMOD NMOS (VTO = 0.85 KP = 0.21 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1189 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 6.4e-4 TC2 = -9.35e-7)
.MODEL RDRAINMOD RES (TC1 = 1.4e-2 TC2 = 5.0e-6)
.MODEL RSLCMOD RES (TC1 = 4.07e-3 TC2 = 2.25e-5)
.MODEL RSOURCEMOD RES (TC1 = 1.00e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -4.0e-6)
.MODEL RVTEMPMOD RES (TC1 = -9.2e-4 TC2 = 1.7e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.8 VOFF= -1.9)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.9 VOFF= -2.8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.0 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.0)

.ENDS

7

RLSOURCE

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

9

ITF87008DQT

SABER Electrical Model

REV 18 January 2000
template ITF87008DQT n2,n1,n3

electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 2.0e-10, rs = 1.34e-2, trs1 = 1.1e-3, trs2 = 2.0e-6, ikf = 2.3, xti = 0, cjo = 3.9e-10, tt = 8.0e-9, nl = 1.12, m = 0.43)
dp..model dbreakmod = (rs = 2.3e-1, trs1 = 4.0e-3, trs2 = -6.0e-6)
dp..model desd1mod = (bv=11.0, tbv1 = -2.32e-3, nl=12, rs=35)
dp..model desd2mod = (bv=11.1, tbv1 = -2.32e-3, nl=12, rs=35)
dp..model dplcapmod = (cjo = 7.28e-10, isl = 1e-30, vj = 0.40, m = 0.46)
m..model mmedmod = (type=_n, vto = 1.11, kp = 19, is = 1e-30, tox = 1, rs = 9.0e-2)
m..model mstrongmod = (type=_n, vto = 1.39, kp = 107, is = 1e-30, tox = 1, lambda = 1.8e-2)
m..model mweakmod = (type=_n, vto = 0.85, kp = 0.21, is = 1e-30, tox = 1, rs = 1.0e-1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -2.8, voff = -1.9)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -1.9, voff = -2.8)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0)

c.ca n12 n8 = 1.17e-9
c.cb n15 n14 = 1.17e-9
c.cin n6 n8 = 8.15e-10

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.desd1 n91 n9 = model=desd1mod
dp.desd2 n91 n7 = model=desd2mod
dp.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1
l.ldrain n2 n5 = 1.0e-9

l.lgate n1 n9 = 1.04e-9
l.lsource n3 n7 = 1.29e-10

GATE

1

LGATE

RLGATE

RGATE

9

DESD1
91
DESD2

ESG

EVTEMP
+

18
22

20

-

6
8

+

-

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1 = 6.4e-4, tc2 = -9.35e-7
res.rdrain n50 n16 = 2.8e-3, tc1 = 1.40e-2, tc2 = 5.0e-6
res.rgate n9 n20 = 118.9
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 10.4

CA

S1A

12

13

8

S1B

13

res.rlsource n3 n7 = 1.29
res.rslc1 n5 n51 = 1e-6, tc1 = 4.07e-3, tc2 = 2.25e-5
res.rslc2 n5 n50 = 1e3

EGS EDS

res.rsource n8 n7 = 12.8e-3, tc1 = 1.00e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -9.2e-4, tc2 = 1.7e-6
res.rvthres n22 n8 = 1, tc1 = -1.8e-3, tc2 = -4.0e-6

spe.ebreak n11 n7 n17 n18 = 27.05
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1
equations {

i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/185))**2))
}
}

10

RSLC2

6

14
13

+

+

6
8

-

-

S2A

S2B

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

-

5

RSLC1

51

50
RDRAIN

21

MSTRO

14

5
8

ISCL

16

8

MMED

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

-

7

RLSOURCE

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

10

SPICE Thermal Model

REV 26 January 2000
ITF87008DQT
Copper Area = 0.50 in
CTHERM1 th 8 6.7e-4

CTHERM2 8 7 2.2e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 8.6e-3
CTHERM5 5 4 2.2e-2
CTHERM6 4 3 0.08
CTHERM7 3 2 0.32
CTHERM8 2 tl 1.9

2

ITF87008DQT

RTHERM1

th

JUNCTION

CTHERM1

8

RTHERM1 th 8 0.267
RTHERM2 8 7 0.893
RTHERM3 7 6 2.23
RTHERM4 6 5 14.28
RTHERM5 5 4 21.42
RTHERM6 4 3 23.0
RTHERM7 3 2 27.0
RTHERM8 2 tl 29.0

SABER Thermal Model

Copper Area = 0.50 in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 6.7e-4
ctherm.ctherm2 8 7 = 2.2e-3
ctherm.ctherm3 7 6 = 5.0e-3
ctherm.ctherm4 6 5 = 8.6e-3
ctherm.ctherm5 5 4 = 2.2e-2
ctherm.ctherm6 4 3 = 0.08
ctherm.ctherm7 3 2 = 0.32
ctherm.ctherm8 2 tl = 1.9

rtherm.rtherm1 th 8 = 0.267
rtherm.rtherm2 8 7 = 0.893
rtherm.rtherm3 7 6 = 2.23
rtherm.rtherm4 6 5 = 14.28
rtherm.rtherm5 5 4 = 21.42
rtherm.rtherm6 4 3 = 23.0
rtherm.rtherm7 3 2 = 27.0
rtherm.rtherm8 2 tl = 29.0
}

2

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

CTHERM2

7

CTHERM3

6

CTHERM4

5

CTHERM5

4

CTHERM6

3

CTHERM7

2

CTHERM8

tl

CASE

TABLE 1. THERMAL MODELS

COMPONENT 0.02 in

2

0.14 in

2

0.26 in

2

0.38 in

2

0.50 in

CTHERM6 0.07 0.05 0.06 0.07 0.08
CTHERM7 0.15 0.24 0.25 0.28 0.32
CTHERM8 0.68 1.3 1.6 2.0 1.9
RTHERM6 22.8 21 21 25 23
RTHERM7 39.5 30 32 30 27
RTHERM8 56 45 38 34 29

11

2

MO-153AA (TSSOP-8)

8 LEAD JEDEC MO-153AA TSSOP PLASTIC PACKAGE

ITF87008DQT

E

E

1

A

A

1

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.041 0.047 1.05 1.20 -

e

D

4

58

b

A

1

0.002 0.006 0.05 0.15 ­b 0.010 0.012 0.25 0.30 ­c 0.005 0.127 -

D 0.114 0.122 2.90 3.10 2
E 0.244 0.260 6.20 6.60 -

c

E

1

0.170 0.177 4.30 4.50 3
e 0.025 BSC 0.65 BSC -

L

o

0.015

0.4

0.035

0.9

0o-8

0.004 IN

0.10mm

L 0.020 0.028 0.50 0.70 4

NOTES:

1. These dimensions are within allowabledimensions of Rev.E of
JEDEC MO-153AA outline dated 10-97.

2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.006 inches (0.15mm) per side.

0.232

5.9

0.025

0.65

0.077

1.95

3. Dimension “E1” does not include inter-lead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.

4. “L” is the length of terminal for soldering.

5. Controlling dimension: Millimeter

6. Revision 2 dated: 1-00.

MO-153AA (TSSOP-8)

12mm TAPE AND REEL

330mm

20.4mm

13mm

53.5mm

13.4mm

COVER TAPE

1.5mm

DIA. HOLE

12mm

4.0mm

8.0mm

USER DIRECTION OF FEED

GENERAL INFORMATION

1. 3000 PIECES PER REEL.

2. ORDER IN MULTIPLES OF FULL REELS ONLY.

3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.

2.0mm

1.75mm

C

L

12

ITF87008DQT

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Intersil semiconductor products are sold by description only .Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

13

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