Datasheet ITF86174SQT Datasheet (Intersil)

ITF86174SQT

Data Sheet March 2000

9A, 30V, 0.016 Ohm, P-Channel, Logic
Level, Power MOSFET

Packaging

TSSOP-8

5

1

2

4

3

Symbol

DRAIN(1)

SOURCE(2)

SOURCE(3)

GATE(4)

DRAIN(8)

SOURCE(7)

SOURCE(6)

DRAIN(5)

File Number 4799.3

Features

• Ultra Low On-Resistance

-r

-r

-r

= 0.016Ω, VGS= −10V

DS(ON)

= 0.024Ω, VGS= −4.5V

DS(ON)

= 0.027Ω, VGS= −4V

DS(ON)

• Gate to Source Protection Diode

• Simulation Models

- Temperature Compensated PSPICE™ and SABER
Electrical Models

- Spice and SABER Thermal Impedance Models

- www.intersil.com

• Peak Current vs Pulse Width Curve

• Transient Thermal Impedance Curve vs Board Mounting
Area

• Switching Time vs R

GS

Curves

Ordering Information

PART NUMBER PACKAGE BRAND

ITF86174SQT TSSOP-8 86174

NOTE: When ordering, use the entire part number. ITF86174SQT2
is available only in tape and reel.

Absolute Maximum Ratings T

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain Current

Continuous (TA = 25oC, VGS = 10V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TA = 25oC, VGS = 4.5V) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TA = 100oC, VGS = 4.5V) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TA = 100oC, VGS = 4.0V) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief TB370. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

NOTES:

1. TJ = 25oC to 125oC.

2. 62.5oC/W measured using FR-4 board with 1.0in2 (645.2mm2) copper pad at 10s.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

1

= 25oC, Unless Otherwise Specified

A

CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.

SABER© is a Copyright of Analogy Inc.

ITF86174SQT UNITS

DSS

DGR

GS

D
D
D
D

DM

D

STG

L

pkg

PSPICE® is a registered trademark of MicroSim Corporation.

| 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000

-30 V

-30 V

±20 V

9.0

7.0

4.5

4.0

Figure 4

2.0
16

-55 to 150

300
260

A
A
A
A

W

mW/oC

o

C

o

C

o

C

ITF86174SQT

Electrical Specifications T

= 25oC, Unless Otherwise Specified

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

THERMAL SPECIFICATIONS

Thermal Resistance Junction to
Ambient

SWITCHING SPECIFICATIONS VGS = -4.5V
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
SWITCHING SPECIFICATIONS VGS = -10V
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charge Q
Gate Charge at -5V Q
Threshold Gate Charge Q
Gate to Source Gate Charge Q
Gate to Drain “Miller” Charge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

DSSID
DSS
GSS

GS(TH)VGS

DS(ON)ID

VDS = -30V, VGS = 0V - - -1 µA
VGS = ±20V - - ±10 µA

ID = 4.5A, VGS = -4.5V Figure 8 - 0.018 0.024 Ω
ID = 4.0A, VGS = -4.0V Figure 8 - 0.020 0.027 Ω

R

θJA

Pad Area = 1.0 in2(645.2 mm2) (Note 2) - - 62.5oC/W
Pad Area = 0.035 in2 (22.4 mm2) Figure 20 - - 165.4oC/W
Pad Area = 0.0045 in2 (2.88 mm2) Figure 20 - - 206.8oC/W

d(ON)

VDD = -15V, ID = 4.5A
VGS= -4.5V,

r

RGS = 6.8Ω

d(OFF)

d(ON)

Figures 14, 18, 19

f

VDD = -15V, ID = 9.0A
VGS= -10V,

r

RGS = 7.5Ω

d(OFF)

g(TOT)VGS

g(-5)

g(TH)

ISS

Figures 15, 18, 19

f

VGS = 0V to -5V - 22 - nC
VGS = 0V to -1V - 2 - nC

gs

gd

VDS = -25V, VGS = 0V,
f = 1MHz

OSS
RSS

Figure 12

= 250µA, VGS = 0V Figure 11 -30 - - V

= VDS, ID = 250µA Figure 10 -1.0 - -2.5 V

= 9.0A, VGS = -10V Figures 8, 9 - 0.012 0.016 Ω

-19-ns

-64-ns

-40-ns

-48-ns

-13-ns

-52-ns

-67-ns

-62-ns

= 0V to -10V VDD = -15V,

-39-nC
ID = 7.0A,
I

= -1.0mA

g(REF)

Figures 13, 16, 17

- 5.7 - nC

- 8.8 - nC

- 2000 - pF

- 475 - pF

- 215 - pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q

2

SD
rr
RR

ISD = -9.0A - -0.8 - V
ISD = -9.0A, dISD/dt = 100A/µs - 26 - ns
ISD = -9.0A, dISD/dt = 100A/µs - 14 - nC

Typical Performance Curves

ITF86174SQT

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

125

TA, AMBIENT TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT

TEMPERATURE

3

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJA

Z

0.01

THERMAL IMPEDANCE

0.001

-5

10

-4

10

10

-3

SINGLE PULSE

-2

10

t, RECTANGULAR PULSE DURATION (s)

-10

-8
VGS= -10V, R

= 62.5oC/W

θJA

-6

-4

, DRAIN CURRENT (A)

D

I

-2

VGS= -4.0V, R

= 187.7oC/W

θJA

0

25

50 75 100 125 150

TA, AMBIENT TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

AMBIENT TEMPERATURE

R

θJA

P

DM

t

1

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-1

10

0

10

1

10

θJA

1/t2

x R

10

θJA

2

= 62.5oC/W

t

2

+ T

A

3

10

-800

-100

, PEAK CURRENT (A)

DM

I

TRANSCONDUCTANCE
MAY LIMIT CURRENT

-10
IN THIS REGION

-5

-5

10

VGS = -4.0V

-4

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

R

= 62.5oC/W

θJA

-3

10

-2

10

-1

10

0

10

10

t, PULSE WIDTH (s)

FIGURE 4. PEAK CURRENT CAPABILITY

3

TC = 25oC
FOR TEMPERATURES

ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

I = I

1

150 - T

25

125

2

10

A

3

10

Typical Performance Curves (Continued)

ITF86174SQT

-500

-100

-10

, DRAIN CURRENT (A)

D

I

-1

R

= 62.5oC/W

θJA

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

DS(ON)

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

SINGLE PULSE
TJ = MAX RATED
TA = 25oC

-10 -60-1

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

-40

-30

-20

= -10V

V

GS

VGS = -5V
V

= -4.5V

GS

= -4V

V

GS

VGS = -3.5V

VGS = -3V

100µs

1ms

10ms

-40

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= -15V

DD

-30

-20

DRAIN CURRENT (A)

-10

D,

I

0

-1.5 -2.0 -2.5 -3.0 -3.5

TJ = 150oC

TJ = -55oC

TJ = 25oC

VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 6. TRANSFER CHARACTERISTICS

30

ID = -9A

25

20

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

, DRAIN CURRENT (A)

-10

D

I

TA = 25oC

0

0 -0.5 -1.0 -1.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

, DRAIN TO SOURCE

ON RESISTANCE (mΩ)

DS(ON)

r

ID = -1A

15

10

-3 -5 -7 -9

-2 -4 -6 -8 -10
, GATE TO SOURCE VOLTAGE (V)

V

GS

FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

1.6

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.4

1.2

1.0

ON RESISTANCE

0.8

NORMALIZED DRAIN TO SOURCE

0.6

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

VGS = -10V, ID = -9A

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = -250µA

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

4

FIGURE 10. NORMALIZED GATETHRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

Typical Performance Curves (Continued)

1.10
ID = -250µA

1.05

1.00

ITF86174SQT

3000

1000

C

OSS

≅ CDS+ C

GD

C

ISS

= CGS + C

GD

0.95

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.90

-80 -40 0 40 80 120 160
, JUNCTION TEMPERATURE (oC)

T

J

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

-10
VDD = -15V

-8

-6

-4

WAVEFORMS IN

-2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

010203040

, GATE CHARGE (nC)

Q

g

DESCENDING ORDER:

ID = -9A

= -1A

I

D

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMSFOR CONSTANT

GATE CURRENT

C, CAPACITANCE (pF)

C

= C

RSS

VGS= 0V, f = 1MHz

100

-0.1 -1.0 -10 -30
VDS, DRAIN TO SOURCE VOLTAGE (V)

GD

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

200

VGS = -4.5V, VDD = -15V, ID = -4.5A

t

150

100

SWITCHING TIME (ns)

50

0

0 1020304050

RGS, GATE TO SOURCE RESISTANCE (Ω)

r

t

d(ON)

t

f

t

d(OFF)

FIGURE 14. SWITCHING TIME vs GATE RESISTANCE

300

250

200

150

100

SWITCHING TIME (ns)

5

VGS = -10V, VDD = -15V, ID = -9A

t

f

t

d(OFF)

t

r

50

0

0 1020304050

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

d(ON)

FIGURE 15. SWITCHING TIME vs GATE RESISTANCE

Test Circuits and Waveforms

ITF86174SQT

I

g(REF)

Q

V

DS

R

L

V

GS

DUT

-

V

DD

+

0

VGS = -1V

V

DD

0

I

g(REF)

gs

Q

g(TH)

-V

GS

Q

gd

VGS = -5V

Q

g(-5)

Q

g(TOT)

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS

t

ON

t

R

L

V

DS

V

GS

-

+

0

d(ON)

t

r

10%

V

DS

t

d(OFF)

t

OFF

VGS = -10V

t

f

10%

0V

R

GS

-V

GS

DUT

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM

Thermal Resistance vs Mounting Pad Area

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines the
maximum allowable de vice po w er dissipation, P
application. Therefore the application’ s ambient temperature ,
T

(oC), and thermal resistance R

A

to ensure that T

is never e xceeded. Equation 1

JM

(oC/W) must be reviewed

θJA

mathematically represents the relationship and serves as the
basis for establishing the rating of the part.

P

TJMTA–()

------------------------------ -=

DM

Z

θJA

In using surface mount devices such as the TSSOP-8
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
complex and influenced by many factors:

DM

, in an

DM

(EQ. 1)

is

V

DS

0

V

GS

90%

10%

50%

PULSE WIDTH

90%

50%

90%

1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.

2. The number of copper layersandthe thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. Fornon steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.

Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the

for the device as a function of the top copper

R

θJA

(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the

6

ITF86174SQT

necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalizedmaximum
transient thermal impedance curve.

Displayed on the curve are R

values listed in the Electrical

θJA

Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, P

DM

.

Thermal resistances corresponding to other copper areas can
be obtained from Figure 23 or by calculation using Equation 2.
R

is defined as the natural log of the area times a coefficient

θJA

added to a constant. The area, in square inches is the top
copper area including the gate and source pads.

R

The transient thermal impedance (Z

97.5 20.2 Area()

θJA

ln×–=

) is also effected by

θJA

(EQ. 2)

varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.

Copper pad area has no perceivable eff ect on tr ansient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore ,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.

240

C/W)

o

(

R

220

200
180

160

θJA

140
120

100

80

0.001

206.8oC/W - 0.0045in

0.01

AREA, TOP COPPER AREA (in2)

FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA

R

= 97.5 - 20.2*ln(AREA)

θJA

2

165.4oC/W - 0.035in

0.1 1.0

2

150

120

C/W)

o

90

, THERMAL

60

θJA

Z

IMPEDANCE (

30

0

10

COPPER BOARD AREA - DESCENDING ORDER

2

0.04in

2

0.28in

2

0.52in

2

0.76in

2

1.00in

-1

10

0

t, RECTANGULAR PULSE DURATION (s)

FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA

10

1

10

2

10

3

7

ITF86174SQT

PSPICE Electrical Model

.SUBCKT ITF86174SQT 2 1 3 ; REV 14 December 1999

CA 12 8 1.65e-9
CB 15 14 1.65e-9
CIN 6 8 1.82e-9

+

-

11

7

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

RVTEMP
19

-

VBAT

+

22

DRAIN

2

SOURCE

3

DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 6 DPLCAPMOD

EBREAK 5 11 17 18 -34.95
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1

IT 8 17 1
LDRAIN 2 5 1.0e-9

LGATE 1 9 1.04e-9
LSOURCE 3 7 1.29e-10

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

GATE

1

LGATE

RLGATE

RGATE

9

DESD1
91
DESD2

DPLCAP

EVTEMP

-

18
22

20

ESG

10

8
6

RSLC2

EVTHRES

+

6

+

5

+-

RSLC1

51

+

5

ESLC

51

-

50
RDRAIN

16

21

-

19

8

MSTRO

CIN

8

EBREAK

MWEAK

MMED

DBREAK

RSOURCE

17
18

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.50e-3
RGATE 9 20 3.63
RLDRAIN 2 5 10
RLGATE 1 9 9 10.4
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 7.90e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

CA

S1A

12

13

8

S1B

EGS EDS

S2A

S2B

15

CB

14

+

5
8

-

14
13

13

+

+

6
8

-

-

RBREAK

17 18

IT

8

RVTHRES

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),2))}
.MODEL DBODYMOD D (IS = 2.75e-12 RS = 4.90e-3 TRS1 = 1.30e-3 TRS2 = -8.50e-6 XTI = 4 IKF = 3.4 CJO = 1.25e-9 TT = 6.5e-10 VJ=0.65 M = 0.43)

.MODEL DBREAKMOD D (RS = 1.50e-1 TRS1 = 1.00e-3 TRS2 = 1.00e-6)
.MODEL DESD1MOD D (BV=18.45 TBV1=-1.43E-3 TBV2=0 RS=200 N=13)
.MODEL DESD2MOD D (BV=18.45 TBV1=-1.43E-3 TBV2=0 RS=200 N=13)
.MODEL DPLCAPMOD D (CJO = 9.05e-10 IS = 1e-30 N=10 VJ=0.372 M = 0.34)
.MODEL MMEDMOD PMOS (VTO = -1.94 KP = 8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.63 RS = 0.1)
.MODEL MSTROMOD PMOS (VTO = -2.20 KP = 65 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u LAMBDA=0.15)
.MODEL MWEAKMOD PMOS (VTO = -1.51 KP = 0.35 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 36.3 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 7.10e-4 TC2 = -1.02E-6)
.MODEL RDRAINMOD RES (TC1 = 1.60e-2 TC2 = 3.00e-5)
.MODEL RSLCMOD RES (TC1 = 2.00e-3 TC2 = -3.00e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = 2.10e-3 TC2 = 6.20e-6)
.MODEL RVTEMPMOD RES (TC1 = -5.00e-4 TC2 = 1.20e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 6.2 VOFF= 3.1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.1 VOFF= 6.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.0 VOFF= -0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 1.0)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

8

ITF86174SQT

SABER Electrical Model

REV 14 December 1999
template ITF86174SQT n2,n1,n3

electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 2.75e-12, cjo = 1.25e-9, tt = 6.5e-10, vj=0.65, m = 0.43, rs = 4.90e-3, trs1 = 1.30e-3, trs2 = -8.50e-6, xti=4, ikf=3.4)
dp..model dbreakmod = (rs = 1.5e-1, trs1 = 1.00e-3, trs2 = 1.00e-6)
dp..desd1mod = (bv=18.45, tbv1=-1.43e-3, tbv2=0, rs=200, nl=13)
dp..desd2mod = (bv=18.45, tbv1=-1.43e-3, tbv2=0, rs=200, nl=13)
dp..model dplcapmod = (cjo = 9.05e-10, isl = 1e-30, nl = 10, vj=0.372, m = 0.34)
m..model mmedmod = (type=_p, vto = -1.94, kp = 8, is = 1e-30, tox = 1, rs=0.1)
m..model mstrongmod = (type=_p, vto = -2.20, kp = 65, is = 1e-30, tox = 1, lambda=0.15)
m..model mweakmod = (type=_p, vto = -1.35, kp = 0.35, is = 1e-30, tox = 1 rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 6.2, voff = 3.1)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = 3.1, voff = 6.2)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 1.0, voff = -0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 1.0)

c.ca n12 n8 = 1.65e-9
c.cb n15 n14 = 1.65e-9
c.cin n6 n8 = 1.82e-9

dp.dbody n5 n7 = model=dbodymod
dp.dbreak n7 n11 = model=dbreakmod

DPLCAP

dp.dplcap n10 n6 = model=dplcapmod
dp.desd1 n91 n9 = model=desd1mod
dp.desd2 n91 n7 = model=desd2mod

i.it n8 n17 = 1

GATE

1

l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.04e-9
l.lsource n3 n7 = 1.29e-10

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

LGATE

RLGATE

91

RGATE

9

DESD1

DESD2

EVTEMP

-

18
22

20

+

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

S1A

res.rbreak n17 n18 = 1, tc1 = 7.10e-4, tc2 = -1.02e-6
res.rdrain n50 n16 = 1.50e-3, tc1 = 1.60e-2, tc2 = 3.00e-5
res.rgate n9 n20 = 3.63
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 10.4
res.rlsource n3 n7 = 1.29
res.rslc1 n5 n51 = 1e-6, tc1 = 2.00e-3, tc2 = -3.00e-6

CA

12

13

8

S1B

13

res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 7.90e-3, tc1 = 0, tc2 = 0

EGS EDS

res.rvtemp n18 n19 = 1, tc1 = -5.00e-4, tc2 = 1.20e-6
res.rvthres n22 n8 = 1, tc1 = 2.10e-3, tc2 = 6.20e-6

spe.ebreak n11 n7 n17 n18 = -34.95
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n5 n10 n8 n6 = 1
spe.evtemp n6 n20 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1
equations {

i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2))
}
}

ESG

-

10

RSLC2

6

S2A

14
13

S2B

+

+

6
8

-

-

+

8
6

EVTHRES

+

19

8

CIN

15

CB

-

+

5
8

-

5

RSLC1

51

50
RDRAIN

21

MSTRO

14

ISCL

16

8

EBREAK

MMED

RSOURCE

IT

8

+

17
18

-

11

MWEAK

DBREAK

RBREAK

17 18

RVTHRES

7

RLSOURCE

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

9

SPICE Thermal Model

REV 27 December 1999
ITF86174SQT
Copper Area = 1.0 in
CTHERM1 th 8 1.5e-3

CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 2.0e-2
CTHERM5 5 4 5.0e-2
CTHERM6 4 3 0.2
CTHERM7 3 2 0.5
CTHERM8 2 tl 3.0

2

ITF86174SQT

RTHERM1

RTHERM2

th

JUNCTION

CTHERM1

8

CTHERM2

RTHERM1 th 8 0.15
RTHERM2 8 7 0.50
RTHERM3 7 6 1.25
RTHERM4 6 5 8.0
RTHERM5 5 4 12.0
RTHERM6 4 3 12.0
RTHERM7 3 2 18.0
RTHERM8 2 tl 25.0

SABER Thermal Model

Copper Area = 1.0 in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 1.5e-3
ctherm.ctherm2 8 7 = 5.0e-3
ctherm.ctherm3 7 6 = 1.0e-2
ctherm.ctherm4 6 5 = 2.0e-2
ctherm.ctherm5 5 4 = 5.0e-2
ctherm.ctherm6 4 3 = 0.2
ctherm.ctherm7 3 2 = 0.5
ctherm.ctherm8 2 tl = 3.0

rtherm.rtherm1 th 8 = 0.15
rtherm.rtherm2 8 7 = 0.50
rtherm.rtherm3 7 6 = 1.25
rtherm.rtherm4 6 5 = 8.0
rtherm.rtherm5 5 4 = 12.0
rtherm.rtherm6 4 3 = 12.0
rtherm.rtherm7 3 2 = 18.0
rtherm.rtherm8 2 tl = 25.0
}

2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

7

CTHERM3

6

CTHERM4

5

CTHERM5

4

CTHERM6

3

CTHERM7

2

CTHERM8

tl

CASE

TABLE 1. THERMAL MODELS

COMPONENT 0.04in

2

0.28in

2

0.52in

2

0.76in

2

1.0in

CTHERM6 0.12 0.20 0.28 0.19 0.20
CTHERM7 0.25 0.48 0.45 0.39 0.50
CTHERM8 1.3 2.3 2.2 2.7 3.0
RTHERM6 26 20 15 11 12
RTHERM7 39 24 21 21 18
RTHERM8 49.5 36.8 39 29.5 25

10

2

MO-153AA (TSSOP-8)

8 LEAD JEDEC MO-153AA TSSOP PLASTIC PACKAGE

ITF86174SQT

E

E

1

A

A

1

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.041 0.047 1.05 1.20 -

e

D

4

58

b

A

1

0.002 0.006 0.05 0.15 ­b 0.010 0.012 0.25 0.30 ­c 0.005 0.127 -

D 0.114 0.122 2.90 3.10 2
E 0.244 0.260 6.20 6.60 -

c

E

1

0.170 0.177 4.30 4.50 3
e 0.025 BSC 0.65 BSC -

L

o

0.015

0.4

0.035

0.9

0o-8

0.004 IN

0.10mm

L 0.020 0.028 0.50 0.70 4

NOTES:

1. These dimensions are within allowabledimensions of Rev.E of
JEDEC MO-153AA outline dated 10-97.

2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed

0.006 inches (0.15mm) per side.

0.232

5.9

0.025

0.65

0.077

1.95

3. Dimension “E1” does not include inter-lead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.

4. “L” is the length of terminal for soldering.

5. Controlling dimension: Millimeter

6. Revision 2 dated: 1-00.

MO-153AA (TSSOP-8)

12mm TAPE AND REEL

330mm

20.4mm

13mm

53.5mm

13.4mm

COVER TAPE

1.5mm

DIA. HOLE

12mm

4.0mm

8.0mm

USER DIRECTION OF FEED

GENERAL INFORMATION

1. 3000 PIECES PER REEL.

2. ORDER IN MULTIPLES OF FULL REELS ONLY.

3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.

2.0mm

1.75mm

C

L

11

ITF86174SQT

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

12

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]