Datasheet ISPGDX80VA-5T100I, ISPGDX80VA-5T100, ISPGDX80VA-3T100, ISPGDX80VA-9T100I, ISPGDX80VA-7T100I Datasheet (Lattice Semiconductor Corporation)

ispGDX

TM

80VA

• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY

— Advanced Architecture Addresses Programmable

PCB Interconnect, Bus Interface Integration and

Jumper/Switch Replacement
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP

Switch Emulation
— Space-Saving PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan

Test

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 3.3V Core Power Supply

— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay
— 250MHz Maximum Clock Frequency
— TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels (Individually Programmable)
— Low-Power: 16.5mA Quiescent Icc
— 24mA IOL Drive with Programmable Slew Rate

Control Option
— PCI Compatible Drive Capability
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology

• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES
— 3.3V In-System Programmable Using Boundary Scan

Test Access Port (TAP)

— Change Interconnects in Seconds

• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs

— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (two) or

Programmable Clocks/Clock Enables from I/O Pins (20)
— Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns)
— Programmable Wide-MUX Cascade Feature

Supports up to 16:1 MUX
— Programmable Pull-ups, Bus Hold Latch and Open

Drain on I/O Pins
— Outputs Tri-state During Power-up (“Live Insertion”

Friendly)

• DESIGN SUPPORT THROUGH LATTICE’S ispGDX
DEVELOPMENT SOFTWARE

— MS Windows or NT / PC-Based or Sun O/S
— Easy Text-Based Design Entry
— Automatic Signal Routing
— Program up to 100 ISP Devices Concurrently
— Simulator Netlist Generation for Easy Board-Level

Simulation

In-System Programmable

3.3V Generic Digital Crosspoint

Functional Block DiagramFeatures

ISP

Control

I/O Pins C

I/O Pins A

Boundary

Scan

Control

I/O

Cells

I/O Pins D

Global Routing

Pool

(GRP)

I/O Pins B

I/O

Cells

Description

The ispGDXVA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface require­ments including:

• Multi-Port Multiprocessor Interfaces

• Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)

• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)

• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces

The devices feature fast operation, with input-to-output
signal delays (Tpd) of 3.5ns and clock-to-output delays of

3.5ns.
The architecture of the devices consists of a series of

programmable I/O cells interconnected by a Global Rout­ing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs

TM

Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. September 2000
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

gdx80va_02

1

Description (Continued)

Specifications ispGDX80VA

found in each I/O cell. Each output has individual, pro­grammable I/O tri-state control (OE), output latch clock
(CLK), clock enable (CLKEN), and two multiplexer con­trol (MUX0 and MUX1) inputs. Polarity for these signals
is programmable for each I/O cell. The MUX0 and MUX1
inputs control a fast 4:1 MUX, allowing dynamic selection
of up to four signal sources for a given output. A wider
16:1 MUX can be implemented with the MUX expander
feature of each I/O and a propagation delay increase of

2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs
can be driven directly from selected sets of I/O pins.
Optional dedicated clock input pins give minimum clock­to-output delays. CLK and CLKEN share the same set of
I/O pins. CLKEN disables the register clock when
CLKEN = 0.

Through in-system programming, connections between
I/O pins and architectural features (latched or registered
inputs or outputs, output enable control, etc.) can be
defined. In keeping with its data path application focus,
the ispGDXVA devices contain no programmable logic
arrays. All input pins include Schmitt trigger buffers for
noise immunity. These connections are programmed
into the device using non-volatile E

2

CMOS technology.
Non-volatile technology means the device configuration
is saved even when the power is removed from the
device.

In addition, there are no pin-to-pin routing constraints for

any

1:1 or 1:n signal routing. That is,

I/O pin configured
as an input can drive one or more I/O pins configured as
outputs.

The device pins also have the ability to set outputs to
fixed HIGH or LOW logic levels (Jumper or DIP Switch
mode). Device outputs are specified for 24mA sink and
12mA source current (at JEDEC LVTTL levels) and can
be tied together in parallel for greater drive. On the
ispGDXVA, each I/O pin is individually programmable for

3.3V or 2.5V output levels as described later. Program­mable output slew rate control can be defined
independently for each I/O pin to reduce overall ground
bounce and switching noise.

All I/O pins are equipped with IEEE1149.1-compliant
Boundary Scan Test circuitry for enhanced testability. In
addition, in-system programming is supported through
the Test Access Port via a special set of private com­mands.

The ispGDXVA I/Os are designed to withstand “live
insertion” system environments. The I/O buffers are
disabled during power-up and power-down cycles. When
designing for “live insertion,” absolute maximum rating
conditions for the Vcc and I/O pins must still be met.

Table 1. ispGDXVA Family Members

I/O Pins 160
I/O-OE Inputs* 40
I/O-CLK / CLKEN Inputs* 40
I/O-MUXsel1 Inputs* 40
I/O-MUXsel2 Inputs* 40
Dedicated Clock Pins** 4

EPEN 1
TOE
BSCAN Interface 4

RESET

Pin Count/Package 208-Pin PQFP

* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to
25% of the I/Os.
** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and
CLKEN3 respectively in all devices.

ispGDX80VA

80
20
20
20
20

2
1

1
4
1

100-Pin TQFP

ispGDXV/VA Device

ispGDX160V/VA

1

1

208-Ball fpBGA

272-Ball BGA

ispGDX240VA

240

60
60
60
60

4
1

1
4
1

388-Ball fpBGA

2

Architecture

Specifications ispGDX80VA

The ispGDXVA architecture is different from traditional
PLD architectures, in keeping with its unique application
focus. The block diagram is shown below. The program-

The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped

together with one group per side.
mable interconnect consists of a single Global Routing
Pool (GRP). Unlike ispLSI devices, there are no pro­grammable logic arrays on the device. Control signals for
OEs, Clocks/Clock Enables and MUX Controls must
come from designated sets of I/O pins. The polarity of
these signals can be independently programmed in each
I/O cell.

Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
In-system programming is accomplished through the
standard Boundary Scan protocol.

I/O Architecture

Each I/O cell contains a 4:1 dynamic MUX controlled by

two select lines as well as a 4x4 crossbar switch con-

trolled by software for increased routing flexiability (Figure

1). The four data inputs to the MUX (called M0, M1, M2,

and M3) come from I/O signals in the GRP and/or

adjacent I/O cells. Each MUX data input can access one

quarter of the total I/Os. For example, in an 80-I/O

ispGDXVA, each data input can connect to one of 20 I/O

pins. MUX0 and MUX1 can be driven by designated I/O

pins called MUXsel1 and MUXsel2. Each MUXsel input

covers 25% of the total I/O pins (e.g. 20 out of 80). MUX0

and MUX1 can be driven from either MUXsel1 or MUXsel2.

Figure 1. ispGDXVA I/O Cell and GRP Detail (80 I/O Device)

Logic “1”

Logic “0”

I/OCell 0

80 I/O Inputs

I/O Cell 79

I/O Cell 1

•

•

•

•

•

•

I/O Cell 38

I/O Cell 39

40 I/O Cells

80 Input GRP

Inputs Vertical

Outputs Horizontal

E2CMOS

Programmable

Interconnect

I/O Group A
I/O Group B
I/O Group C
I/O Group D

• • • • • •

Y0-Y3
Global

Clocks /

Clock_Enables

From MUX Outputs

of 2 Adjacent I/O Cells

N+2

N+1

N-1

N-2

Global

Reset

4x4

Crossbar

Switch

From MUX Outputs

of 2 Adjacent I/O Cells

40 I/O Cells

ispGDXVA architecture enhancements over ispGDX (5V)

4-to-1 MUX

M0
M1
M2
M3

MUX1MUX0

I/O Cell 78

To 2 Adjacent

I/O Cells above

To 2 Adjacent

I/O Cells below

I/O Cell 41

I/O Cell 40

•

•

•

•

•

•

Bypass Option

Register
or Latch

A

D

B

CLK

CLK_EN

Reset

Prog.

Prog.

Bus Hold

Pull-up

Latch

(VCCIO)

C

Q

R

Prog. Open Drain

2.5V/3.3V Output

Prog. Slew Rate

Boundary
Scan Cell

I/O
Pin

I/O Cell N

3

Specifications ispGDX80VA

I/O MUX Operation

MUX1 MUX0 Data Input Selected

00 M0
01 M1
11 M2
10 M3

Flexible mapping of MUXselx to MUXx allows the user to
change the MUX select assignment after the ispGDXVA
device has been soldered to the board. Figure 1 shows
that the I/O cell can accept (by programming the appro­priate fuses) inputs from the MUX outputs of four adjacent
I/O cells, two above and two below. This enables cascad­ing of the MUXes to enable wider (up to 16:1) MUX
implementations.

The I/O cell also includes a programmable flow-through
latch or register that can be placed in the input or output
path and bypassed for combinatorial outputs. As shown
in Figure 1, when the input control MUX of the register/
latch selects the “A” path, the register/latch gets its inputs
from the 4:1 MUX and drives the I/O output. When
selecting the “B” path, the register/latch is directly driven
by the I/O input while its output feeds the GRP. The
programmable polarity Clock to the latch or register can
be connected to any I/O in the I/O-CLK/CLKEN set (one­quarter of total I/Os) or to one of the dedicated clock input
pins (Yx). The programmable polarity Clock Enable input
to the register can be programmed to connect to any of
the I/O-CLK/CLKEN input pin set or to the global clock
enable inputs (CLKENx). Use of the dedicated clock
inputs gives minimum clock-to-output delays and mini­mizes delay variation with fanout. Combinatorial output
mode may be implemented by a dedicated architecture
bit and bypass MUX. I/O cell output polarity can be
programmed as active high or active low.

allow adjacent I/O cell outputs to be directly connected

without passing through the global routing pool. The

relationship between the [N+i] adjacent cells and A, B, C

and D inputs will vary depending on where the I/O cell is

located on the physical die. The I/O cells can be grouped

into “normal” and “reflected” I/O cells or I/O “hemi-

spheres.” These are defined as:

Device Normal I/O Cells Reflected I/O Cells

ispGDX80VA

ispGDX160V/VA

ispGDX240VA B29-B0, A59-A0,

B9-B0, A19-A0,

D19-D10

B19-B0, A39-A0,

D39-D20

D59-D30

B10-B19, C0-C19,

D0-D9

B20-B39, C0-C39,

D0-D19

B30-B59, C0-C59,

D0-D29

Table 2 shows the relationship between adjacent I/O

cells as well as their relationship to direct MUX inputs.

Note that the MUX expansion is circular and that I/O cell

B10, for example, draws on I/Os B9 and B8, as well as

B11 and B12, even though they are in different hemi-

spheres of the physical die. Table 2 shows some typical

cases and all boundary cases. All other cells can be

extrapolated from the pattern shown in the table.

Figure 2. I/O Hemisphere Configuration of

ispGDX80VA

I/O cell 0 I/O cell 79

A0

D19

D10 D9

D0

C19C0

MUX Expander Using Adjacent I/O Cells

The ispGDXVA allows adjacent I/O cell MUXes to be
cascaded to form wider input MUXes (up to 16 x 1)
without incurring an additional full Tpd penalty. However,
there are certain dependencies on the locality of the
adjacent MUXes when used along with direct MUX
inputs.

Adjacent I/O Cells

Expansion inputs MUXOUT[n-2], MUXOUT[n-1],
MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable
for each I/O cell MUX. These expansion inputs share the
same path as the standard A, B, C and D MUX inputs, and

I/O cell index increases in this direction

A19

B0

B9 B10

I/O cell 39

B19

I/O cell 40

Direct and Expander Input Routing

Table 2 also illustrates the routing of MUX direct inputs

that are accessible when using adjacent I/O cells as

inputs. Take I/O cell D13 as an example, which is also

shown in Figure 3.

4

I/O cell index increases in this direction

Specifications ispGDX80VA

Figure 3. Adjacent I/O Cells vs. Direct Input Path for
ispGDX80VA, I/O D13

ispGDX80VA I/O Cell

I/O Group A
D11 MUX Out
I/O Group B
D12 MUX Out

I/O Group C
D14 MUX Out

I/O Group D
D15 MUX Out

4 x 4

Crossbar

Switch

.m0
.m1
.m2
.m3

S0S1

D13

It can be seen from Figure 3 that if the D11 adjacent I/O
cell is used, the I/O group “A” input is no longer available
as a direct MUX input.

The ispGDXVA can implement MUXes up to 16 bits wide
in a single level of logic, but care must be taken when
combining adjacent I/O cell outputs with direct MUX
inputs. Any particular combination of adjacent I/O cells as
MUX inputs will dictate what I/O groups (A, B, C or D) can
be routed to the remaining inputs. By properly choosing
the adjacent I/O cells, all of the MUX inputs can be
utilized.

Special Features

Slew Rate Control

All output buffers contain a programmable slew rate

control that provides software-selectable slew rate op-

tions.

Open Drain Control

All output buffers provide a programmable Open-Drain

option which allows the user to drive system level reset,

interrupt and enable/disable lines directly without the

need for an off-chip Open-Drain or Open-Collector buffer.

Wire-OR logic functions can be performed at the printed

circuit board level.

Pull-up Resistor

All pins have a programmable active pull-up. A typical

resistor value for the pull-up ranges from 50kΩ to 80kΩ.

Output Latch (Bus Hold)

All pins have a programmable circuit that weakly holds

the previously driven state when all drivers connected to

the pin (including the pin's output driver as well as any

other devices connected to the pin by external bus) are

tristated.

Table 2. Adjacent I/O Cells (Mapping of
ispGDX80VA)

Data C/

MUXOUT

D7
D8
D9

D9

B5
B6
B7

B8

Reflected

I/O Cells

Normal

I/O Cells

B10
B11
B12
B13

D6
D7
D8

D9
D10
D11
D12
D13

B6

B7

B8

B9

Data A/

MUXOUT

B12
B13
B14
B15

D8

D9
D10
D11

D8

D9
D10
D11

B4

B5

B6

B7

Data B/

MUXOUT

B11
B12
B13
B14

D10

D10
D11
D12

B9
B10
B11
B12

D5

D6

D7

D8
D11
D12
D13
D14

B7

B8

B9
B10

Data D/

MUXOUT

B8
B9

B10
B11

D4
D5
D6

D7
D12
D13
D14
D15

B8

B9
B10
B11

User-Programmable I/Os

The ispGDX80VA features user-programmable
I/Os supporting either 3.3V or 2.5V output voltage level
options. The ispGDX80VA uses a VCCIO pin to provide
the 2.5V reference voltage when used.

PCI Compatible Drive Capability

The ispGDX80VA supports PCI compatible drive capa­bility for all I/Os.

5

Applications

Specifications ispGDX80VA

The ispGDXVA Family architecture has been developed
to deliver an in-system programmable signal routing
solution with high speed and high flexibility. The devices
are targeted for three similar but distinct classes of end­system applications:

Programmable, Random Signal
Interconnect (PRSI)

This class includes PCB-level programmable signal rout­ing and may be used to provide arbitrary signal swapping
between chips. It opens up the possibilities of program­mable system hardware. It is characterized by the need
to provide a large number of 1:1 pin connections which
are statically configured, i.e., the pin-to-pin paths do not
need to change dynamically in response to control in­puts.

Programmable Data Path (PDP)

This application area includes system data path trans­ceiver, MUX and latch functions. With today’s 32- and
64-bit microprocessor buses, but standard data path glue
components still relegated primarily to eight bits, PCBs
are frequently crammed with a dozen or more data path
glue chips that use valuable real estate. Many of these
applications consist of “on-board” bus and memory inter­faces that do not require the very high drive of standard
glue functions but can benefit from higher integration.
Therefore, there is a need for a flexible means to inte­grate these on-board data path functions in an analogous
way to programmable logic’s solution to control logic
integration. Lattice’s CPLDs make an ideal control logic
complement to the ispGDXVA in-system programmable
data path devices as shown below.

Figure 4. ispGDXVA Complements Lattice CPLDs

Address

Inputs

(from µP)

Control

Inputs

(from µP)

Data Path

Bus #1

Programmable Switch Replacement (PSR)

Includes solid-state replacement and integration of me­chanical DIP Switch and jumper functions. Through
in-system programming, pins of the ispGDXVA devices
can be driven to HIGH or LOW logic levels to emulate the
traditional device outputs. PSR functions do not require
any input pin connections.

These applications actually require somewhat different
silicon features. PRSI functions require that the device
support arbitrary signal routing on-chip between any two
pins with no routing restrictions. The routing connections
are static (determined at programming time) and each
input-to-output path operates independently. As a result,
there is little need for dynamic signal controls (OE,
clocks, etc.). Because the ispGDXVA device will inter­face with control logic outputs from other components
(such as ispLSI or ispMACH) on the board (which fre­quently change late in the design process as control logic
is finalized), there must be no restrictions on pin-to-pin
signal routing for this type of application.

PDP functions, on the other hand, require the ability to
dynamically switch signal routing (MUXing) as well as
latch and tri-state output signals. As a result, the pro­grammable interconnect is used to define
routes that are then selected dynamically by control
signals from an external MPU or control logic. These
functions are usually formulated early in the conceptual
design of a product. The data path requirements are
driven by the microprocessor, bus and memory architec­ture defined for the system. This part of the design is the
earliest portion of the system design frozen, and will not
usually change late in the design because the result
would be total system and PCB redesign. As a result, the
ability to accommodate

arbitrary

any pin-to-any pin re­routing is not a strong requirement as long as the designer
has the ability to define his functions with a reasonable
degree of freedom initially.

possible

signal

ispMACH

System

Clock(s)

ispLSI/
Device

Control

Outputs

Buffers / RegistersState Machines

ispGDXVA

Device

Buffers / RegistersDecoders

Data Path

Bus #2

ISP/JTAG

Interface

Configuration

(Switch)
Outputs

As a result, the ispGDXVA architecture has been defined
to support PSR and PRSI applications (including bidirec­tional paths) with no restrictions, while PDP applications
(using dynamic MUXing) are supported with a minimal
number of restrictions as described below. In this way,
speed and cost can be optimized and the devices can still
support the system designer’s needs.

The following diagrams illustrate several ispGDXVA ap­plications.

6

Applications (Continued)

Specifications ispGDX80VA

Figure 5. Address Demultiplex/Data Buffering

XCVR

Control Bus

MUXed Address Data Bus

I/OA I/OB

OEA OEB

Address

Latch

DQ

CLK

Buffered
Data

To Memory/
Peripherals

Address

Figure 6. Data Bus Byte Swapper

XCVR

I/OA

I/OB

OEA OEB

XCVR

I/OA I/OB

OEA OEB

D0-7

XCVR

I/OA I/OB

OEA OEB

XCVR

I/OA I/OB

OEA OEB

Control Bus

D0-7

Data Bus A

D8-15 D8-15

Data Bus B

Designing with the ispGDXVA

As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.

For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.

The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O A0-A19 (80 I/O device), it is not
possible to use I/O A0 and I/O A9 in the same MUX
function. As previously discussed, data path functions
will be assigned early in the design process and these
restrictions are reasonable in order to optimize speed
and cost.

User Electronic Signature

The ispGDXVA Family includes dedicated User Elec­tronic Signature (UES) E2CMOS storage to allow users
to code design-specific information into the devices to
identify particular manufacturing dates, code revisions,
or the like. The UES information is accessible through
the boundary scan programming port via a specific com­mand. This information can be read even when the
security cell is programmed.

Figure 7. Four-Port Memory Interface

4-to-1

16-Bit MUX

Bidirectional

Port #1
OE1

Port #2
OE2

Bus 4

Bus 3

Bus 2

Bus 1

Note: All OE and SEL lines driven by external arbiter logic (not shown).

Port #3
OE3

Port #4
OE4

Memory

Port

OEM

SEL0

SEL1

To
Memory

Security

The ispGDXVA Family includes a security feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.

7

Specifications ispGDX80VA

Absolute Maximum Ratings

1,2

Supply Voltage Vcc................................. -0.5 to +5.4V

Input Voltage Applied............................... -0.5 to +5.6V

Off-State Output Voltage Applied ............ -0.5 to +5.6V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150 °C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.

DC Recommended Operating Conditions

MIN. MAX. UNITS

3.00

3.00 3.60 V

2.3

3.60

3.60

Table 2-0005/gdxva

V

V

V
V

CC

CCIO

SYMBOL

PARAMETER

Supply Voltage

I/O Reference Voltage

Commercial
Industrial

= 0°C to +70°C

T

A

T

= -40°C to +85°C

A

Capacitance (TA=25oC, f=1.0 MHz)

SYMBOL

C

1

C

2

I/O Capacitance
Dedicated Clock Capacitance

PARAMETER PACKAGE TYPE

TQFP

UNITSTYPICAL TEST CONDITIONS

7TQFP
8

pf
pf

V = 3.3V, V = 2.0V

CC

V = 3.3V, V = 2.0V

CC Y

I/O

Table 2-0006/gdxva

Erase/Reprogram Specifications

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles 10,000 — Cycles

8

Switching Test Conditions

V

CCIO

R

1

R

2

C

L

*

Device
Output

Test

Point

*C

L

includes Test Fixture and Probe Capacitance.

0213D

Input Pulse Levels
Input Rise and Fall Time

Input Timing Reference Levels
Output Timing Reference Levels
Output Load

3-state levels are measured 0.5V from steady-state active level.

Output Load Conditions (See Figure 8)

3.3V 2.5V

TEST CONDITION R1

A 35pF

Active High

B

Active Low
Active High to Z

at V -0.5V

C

D 35pF

OH

Active Low to Z
at V +0.5V

OL

Slow Slew

R1 R2

153Ω

∞

153Ω

∞

153Ω

∞

GND to V

< 1.5ns 10% to 90%

V
V

See Figure 8

156Ω

134Ω
134Ω

∞

134Ω

∞
∞

∞

156Ω

∞

156Ω

∞

CCIO(MIN)

CCIO(MIN)
CCIO(MIN)

/2
/2

R2 CL

144Ω
144Ω

∞

144Ω

∞
∞

Table 2-0004A/gdxva

35pF
35pF

Specifications ispGDX80VA

Figure 8. Test Load

5pF

5pF

DC Electrical Characteristics for 3.3V Range

Over Recommended Operating Conditions

SYMBOL

V

CCIO

V

IL

V

IH

V

OL

V

OH

I/O Reference Voltage 3.0 –– 3.6 V
Input Low Voltage
Input High Voltage

Output Low Voltage

Output High Voltage

1. Typical values are at VCC = 3.3V and TA = 25°C.

PARAMETER

VOH ≤ V
VOH ≤ V

VCC = V

V

CC

= V

CONDITION MIN. TYP. MAX. UNITS

or V

OUT

or V

OUT

CC (MIN)

CC (MIN)

≤ V

OUT
OUT

≤ V

OL (MAX)
OL(MAX)

IOL = +100µA
I

= +24mA

OL

I

= -100µA

OH

I

= -12mA

OH

-0.3

2.0

–
––0.55 V

2.8

2.4 ––V

1

–

0.8

–

5.25

–

0.2

–

–

Table 2-0007/gdxva

V
V
V

V

9

DC Electrical Characteristics for 2.5V Range

Over Recommended Operating Conditions

Specifications ispGDX80VA

SYMBOL

V

CCIO

V

IL

V

IH

V

OL

V

OH

PARAMETER

I/O Reference Voltage
Input Low Voltage
Input High Voltage

Output Low Voltage

Output High Voltage

V

OH(MIN)

V

OH(MIN)

V

CCIO=MIN

V

CCIO=MIN

V

CCIO=MIN

V

CCIO=MIN

CONDITION MIN. TYP. MAX. UNITS

≤ V
≤ V

, I
, I

, I
, I

OUT
OUT

= 100µA

OL

= 8mA

OL

= -100µA

OH

= -8mA

OH

or V
or V

OUT
OUT

≤ V
≤ V

OL(MAX)

OL(MAX)

2.3

-0.3

1.7

––0.2 V
––0.6 V

2.1 ––V

1.8

––

2.7

–

0.7

–

5.25

–

–

2.5V/gdxva

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

IIL
IIH

IPU
IBHLS

Input or I/O Low Leakage Current 0V ≤ V
Input or I/O High Leakage Current

I/O Active Pullup Current
Bus Hold Low Sustaining Current

IBHHS Bus Hold High Sustaining Current -40 ––µA
IBHLO Bus Hold Low Overdrive Current ––550 µA
IBHHO Bus Hold High Overdrive Current ––-550 µA
IBHT
IOS
ICCQ

ICC

Bus Hold Trip Points

1

Output Short Circuit Current ––-250 mA

4

Quiescent Power Supply Current – 12 – mA
Dynamic Power Supply Current

per Input Switching

PARAMETER

IN

(V

-0.2) ≤ VIN ≤ V

CCIO

V

≤ VIN ≤ 5.25V

CCIO

0V ≤ VIN ≤ V
V

= V

IN

IL (MAX)

= V

V

IN

IH (MIN)

0V ≤ V

IN

0V ≤ V

IN

V

= 3.3V, V

CC

V

= 0.5V, V

IL

One input toggling at 50% duty cycle,
outputs open.

CONDITION MIN. TYP.2MAX. UNITS

≤ V

IL (MAX)

CCIO

IL (MAX)

–
–
–
–

–
–
–
–

40 ––

≤ V

CCIO

≤ V

CCIO

= 0.5V, TA = 25°C

OUT

= V

IH

CC

V

IL

– V

– See

Note 3

-10
10
50

-200

IH

–

mA/

MHz

V
V
V

V

µA
µA
µA
µA
µA

V

Maximum Continuous I/O Pin Sink

ICONT

5

Current Through Any GND Pin

1. One output at a time for a maximum of one second. V

–

= 0.5V was selected to avoid test problems by

OUT

––160 mA

tester ground degradation. Characterized, but not 100% tested.

2. Typical values are at V

= 3.3V and T

CC

= 25°C.

A

3. ICC / MHz = (0.002 x I/O cell fanout) + 0.022.
e.g. An input driving four I/O cells at 40MHz results in a dynamic I

of approximately ((0.002 x 4) + 0.022) x 40 = 1.20mA.

CC

4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals.

5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin.

10

DC Char_gdx80va

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispGDX80VA

1

PARAMETER

2

tpd

2

tsel

TEST
COND.

fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3

2

tgco1

2

tgco2

2

tco1

2

tco2

2

ten

2

tdis

2

ttoeen

2

ttoedis
twh
twl
trst
trw
tsl
tsk

1. All timings measured with one output switching, fast output slew rate setting, except tsl.

2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.

#

A
A

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

A
A
A
A
B
C
B
C

–
–
–
–

D
A

Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)

1

Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)

2

Clock Frequency, Max. Toggle

3

Clock Frequency with External Feedback

4

Input Latch or Register Setup Time Before Y

5

Input Latch or Register Setup Time Before I/O Clock

6

Output Latch or Register Setup Time Before Y

7

Output Latch or Register Setup Time Before I/O Clock

8

Global Clock Enable Setup Time Before Y

9

Global Clock Enable Setup Time Before I/O Clock

10

I/O Clock Enable Setup Time Before Y

11

Input Latch or Reg. Hold Time (Yx)

12

Input Latch or Reg. Hold Time (I/O Clock)

13

Output Latch or Reg. Hold Time (Y

14

Output Latch or Reg. Hold Time (I/O Clock)

15

Global Clock Enable Hold Time (Y

16

Global Clock Enable Hold Time (I/O Clock)

17

I/O Clock Enable Hold Time (Y

18

Output Latch or Reg. Clock (from Y

19

Input Latch or Register Clock (from Y

20

Output Latch or Register Clock (from I/O pin) to Output Delay

21

Input Latch or Register Clock (from I/O pin) to Output Delay

22

Input to Output Enable

23

Input to Output Disable

24

Test OE Output Enable

25

Test OE Output Disable

26

Clock Pulse Duration, High

27

Clock Pulse Duration, Low

28

Register Reset Delay from RESET Low

29

Reset Pulse Width

30

Output Delay Adder for Output Timings Using Slow Slew Rate

31

Output Skew (tgco1 Across Chip)

32

DESCRIPTION

x

)

x

)

x

)

x

) to Output Delay

x

) to Output Delay

x

1

( )

tsu3+tgco1

x

x

x

-3

MIN. MAX.

3.5

–

3.5

–

–

250

3.0

2.5

2.5

2.0

2.5

1.5

3.0

0.0

0.5

0.0

1.0

0.0

1.0

0.0

–
–
–
–
–
–
–
–

2.0

2.0

–

5.0

–
–

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

3.5

6.0

4.0

7.0

5.0

5.0

6.0

6.0

–
–

8.0

–

3.5

0.5

166.7

-5

MIN. MAX.

5.0

–

5.0

–

–

143

–

111

–

4.0

–

3.0

–

4.0

–

3.0

–

2.5

–

1.5

–

4.5

–

0.0

–

1.5

–

0.0

–

1.5

–

0.0

–

1.5

–

0.0

5.0

–

8.5

–

6.0

–

9.5

–

6.0

–

6.0

–

6.0

–

6.0

–

–

3.5

–

3.5

14.0

–

10.0

–

5.0

–

0.5

–

UNITS

MHz
MHz

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

11

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispGDX80VA

1

PARAMETER

2

tpd

2

tsel

TEST
COND.

fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3

2

tgco1

2

tgco2

2

tco1

2

tco2

2

ten

2

tdis

2

ttoeen

2

ttoedis
twh
twl
trst
trw
tsl
tsk

1. All timings measured with one output switching, fast output slew rate setting, except tsl.

2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.

#

A
A

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

A
A
A
A
B
C
B
C

–
–
–
–

D
A

Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)

1

Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)

2

Clock Frequency, Max. Toggle

3

Clock Frequency with External Feedback

4

Input Latch or Register Setup Time Before Y

5

Input Latch or Register Setup Time Before I/O Clock

6

Output Latch or Register Setup Time Before Y

7

Output Latch or Register Setup Time Before I/O Clock

8

Global Clock Enable Setup Time Before Y

9

Global Clock Enable Setup Time Before I/O Clock

10

I/O Clock Enable Setup Time Before Y

11

Input Latch or Reg. Hold Time (Yx)

12

Input Latch or Reg. Hold Time (I/O Clock)

13

Output Latch or Reg. Hold Time (Y

14

Output Latch or Reg. Hold Time (I/O Clock)

15

Global Clock Enable Hold Time (Y

16

Global Clock Enable Hold Time (I/O Clock)

17

I/O Clock Enable Hold Time (Y

18

Output Latch or Reg. Clock (from Y

19

Input Latch or Register Clock (from Y

20

Output Latch or Register Clock (from I/O pin) to Output Delay

21

Input Latch or Register Clock (from I/O pin) to Output Delay

22

Input to Output Enable

23

Input to Output Disable

24

Test OE Output Enable

25

Test OE Output Disable

26

Clock Pulse Duration, High

27

Clock Pulse Duration, Low

28

Register Reset Delay from RESET Low

29

Reset Pulse Width

30

Output Delay Adder for Output Timings Using Slow Slew Rate

31

Output Skew (tgco1 Across Chip)

32

DESCRIPTION

x

)

x

)

x

)

x

) to Output Delay

x

) to Output Delay

x

1

( )

tsu3+tgco1

x

x

x

-7

MIN. MAX.

–

7.0

–

7.0

100

–

80

–

5.5

–

4.5

–

5.5

–

4.5

–

3.5

–

2.5

–

6.5

–

0.0

–

2.5

–

0.0

–

2.5

–

0.0

–

2.5

–

0.0

–

–

7.0

–

11.0

–

9.0

–

13.0

–

8.5

–

8.5

–

8.5

–

8.5

5.0

–

5.0

–

–

18.0

14.0

–

–

7.0

–

0.5

-9

MIN. MAX.

9.0

–

9.0

–

–

83

7.0

6.0

7.0

6.0

4.0

3.0

8.5

0.0

3.0

0.0

3.0

0.0

3.0

0.0

–
–
–
–
–
–
–
–

6.0

6.0

–

–
–

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

9.0

13.5

11.5

15.7

10.5

10.5

10.5

10.5

–
–

22.0

–

9.0

1.0

62.5

18.0

UNITS

MHz
MHz

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

12

External Timing Parameters (Continued)

Specifications ispGDX80VA

ispGDX80VA timings are specified with a GRP load
(fanout) of four I/O cells. The figure below shows the ∆
GRP Delay with increased GRP loads. These deltas

ispGDX80VA Maximum ∆ GRP Delay vs. I/O Cell Fanout

1.6

1.4

1.2

1.0

0.8

0.6

∆ GRP Delay (ns)

0.4

0.2

0.0
0 4 10 20 30 40 50 60 70

I/O Cell Fanout

apply to any signal path traversing the GRP (MUXA-D,
OE, CLK/CLKEN, MUXsel0-1). Global Clock signals
which do not use the GRP have no fanout delay adder.

13

Specifications ispGDX80VA

Internal Timing Parameters

1

Over Recommended Operating Conditions

PARAMETER # DESCRIPTION

Inputs
t

io

32 Input Buffer Delay — 0.4 — 0.9 ns

GRP
t

grp

33 GRP Delay — 1.1 — 1.1 ns

MUX
t

muxd

t

muxexp

t

muxs

t

muxsio

t

muxsg

t

muxselexp

34 I/O Cell MUX A/B/C/D Data Delay — 1.0 — 1.5 ns
35 I/O Cell MUX A/B/C/D Expander Delay — 1.5 — 2.0 ns
36 I/O Cell Data Select — 1.0 — 1.5 ns
37 I/O Cell Data Select (I/O Clock) — 1.5 — 3.0 ns
38 I/O Cell Data Select (Yx Clock) — 1.5 — 2.0 ns
39 I/O Cell MUX Data Select Expander Delay — 1.5 — 2.0 ns

Register
t

iolat

t

iosu

t

ioh

t

ioco

t

ior

t

cesu

t

ceh

40 I/O Latch Delay — 1.0 — 1.0 ns
41 I/O Register Setup Time Before Clock — 0.8 — 2.0 ns
42 I/O Register Hold Time After Clock — 1.7 — 1.5 ns
43 I/O Register Clock to Output Delay — 1.2 — 0.5 ns
44 I/O Reset to Output Delay — 1.0 — 1.5 ns
45 I/O Clock Enable Setup Time Before Clock — 2.3 — 2.0 ns
46 I/O Clock Enable Hold Time After Clock — 0.2 — 0.5 ns

Data Path
t

fdbk

t

iobp

t

ioob

t

muxcg

t

muxcio

t

iodg

t

iodio

47 I/O Register Feedback Delay — 0.6 — 0.9 ns
48 I/O Register Bypass Delay — 0.0 — 0.0 ns
49 I/O Register Output Buffer Delay — 0.0 — 0.0 ns
50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) — 1.5 — 2.0 ns
51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) — 1.5 — 3.0 ns
52 I/O Register I/O MUX Delay (Yx Clock) — 3.5 — 4.0 ns
53 I/O Register I/O MUX Delay (I/O Clock) — 3.5 — 5.0 ns

Outputs
t

ob

t

obs

t

oeen

t

oedis

t

goe

t

toe

54 Output Buffer Delay — 1.0 — 1.5 ns
55 Output Buffer Delay (Slow Slew Option) — 4.5 — 6.5 ns
56 I/O Cell OE to Output Enable — 3.5 — 4.0 ns
57 I/O Cell OE to Output Disable — 3.5 — 4.0 ns
58 GRP Output Enable and Disable Delay — 0.0 — 0.0 ns
59 Test OE Enable and Disable Delay — 2.5 — 2.0 ns

Clocks
t

ioclk

t

gclk

t

gclkeng

t

gclkenio

t

ioclkeng

60 I/O Clock Delay — 0.3 — 2.0 ns
61 Global Clock Delay — 1.3 — 2.0 ns
62 Global Clock Enable (Yx Clock) — 1.5 — 2.5 ns
63 Global Clock Enable (I/O Clock) — 1.0 — 3.5 ns
64 I/O Clock Enable (Yx Clock) — 0.5 — 2.5 ns

Global Reset

t

gr

65 Global Reset to I/O Register Latch — 6.0 — 11.0 ns

1. Internal Timing Parameters are not tested and are for reference only .

2. Refer to the Timing Model in this data sheet for further details.

1

-3 -5

MIN. MAX. MIN. MAX. UNITS

14

Specifications ispGDX80VA

Internal Timing Parameters

1

Over Recommended Operating Conditions

PARAMETER # DESCRIPTION

Inputs
t

io

32 Input Buffer Delay — 1.4 — 1.9 ns

GRP
t

grp

33 GRP Delay — 1.1 — 1.1 ns

MUX
t

muxd

t

muxexp

t

muxs

t

muxsio

t

muxsg

t

muxselexp

34 I/O Cell MUX A/B/C/D Data Delay — 2.0 — 2.5 ns
35 I/O Cell MUX A/B/C/D Expander Delay — 2.5 — 3.0 ns
36 I/O Cell Data Select — 2.0 — 2.5 ns
37 I/O Cell Data Select (I/O Clock) — 4.5 — 6.0 ns
38 I/O Cell Data Select (Yx Clock) — 2.5 — 3.0 ns
39 I/O Cell MUX Data Select Expander Delay — 2.5 — 3.0 ns

Register
t

iolat

t

iosu

t

ioh

t

ioco

t

ior

t

cesu

t

ceh

40 I/O Latch Delay — 1.0 — 1.0 ns
41 I/O Register Setup Time Before Clock — 3.2 — 4.4 ns
42 I/O Register Hold Time After Clock — 2.3 — 2.6 ns
43 I/O Register Clock to Output Delay — 0.5 — 0.5 ns
44 I/O Reset to Output Delay — 1.5 — 1.5 ns
45 I/O Clock Enable Setup Time Before Clock — 2.5 — 2.0 ns
46 I/O Clock Enable Hold Time After Clock — 1.0 — 2.0 ns

Data Path
t

fdbk

t

iobp

t

ioob

t

muxcg

t

muxcio

t

iodg

t

iodio

47 I/O Register Feedback Delay — 1.2 — 1.3 ns
48 I/O Register Bypass Delay — 0.3 — 0.6 ns
49 I/O Register Output Buffer Delay — 0.6 — 0.7 ns
50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) — 2.5 — 3.0 ns
51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) — 4.5 — 6.0 ns
52 I/O Register I/O MUX Delay (Yx Clock) — 5.0 — 6.0 ns
53 I/O Register I/O MUX Delay (I/O Clock) — 7.0 — 9.0 ns

Outputs
t

ob

t

obs

t

oeen

t

oedis

t

goe

t

toe

54 Output Buffer Delay — 2.2 — 2.9 ns
55 Output Buffer Delay (Slow Slew Option) — 9.2 — 11.9 ns
56 I/O Cell OE to Output Enable — 6.0 — 7.5 ns
57 I/O Cell OE to Output Disable — 6.0 — 7.5 ns
58 GRP Output Enable and Disable Delay — 0.0 — 0.0 ns
59 Test OE Enable and Disable Delay — 2.5 — 3.0 ns

Clocks
t

ioclk

t

gclk

t

gclkeng

t

gclkenio

t

ioclkeng

60 I/O Clock Delay — 3.2 — 4.4 ns
61 Global Clock Delay — 2.7 — 3.4 ns
62 Global Clock Enable (Yx Clock) — 3.7 — 5.4 ns
63 Global Clock Enable (I/O Clock) — 5.7 — 8.4 ns
64 I/O Clock Enable (Yx Clock) — 4.2 — 6.4 ns

Global Reset

t

gr

65 Global Reset to I/O Register Latch — 13.7 — 16.4 ns

1. Internal Timing Parameters are not tested and are for reference only .

2. Refer to the Timing Model in this data sheet for further details.

1

-7 -9

MIN. MAX. MIN. MAX. UNITS

15

Switching Waveforms

Specifications ispGDX80VA

MUXSEL (I/O INPUT)

DATA (I/O INPUT)

COMBINATORIAL
I/O OUTPUT

OE (I/O INPUT)

COMBINATORIAL
I/O OUTPUT

CLK
(I/O INPUT)

VALID INPUT

t

sel

VALID INPUT

t

pd

Combinatorial Output

dis

t

en

t

I/O Output Enable/Disable

wh

t

wl

t

Clock Width

DATA
(I/O INPUT)

CLK

REGISTERED
I/O OUTPUT

CLKEN

RESET

REGISTERED
I/O OUTPUT

VALID INPUT

1/fmax

h

t

gco

t

co

t

ceh

su

tt

(external fdbk)

t

suce

Registered Output

t

rw

t

rst

Reset

ispGDXVA Timing Model

OE

MUX Expander Input

A
B
C
D

MUX0
MUX1

GRP

tgrp #33

CLKEN
CLK

Y0,1,2,3

tioclkeg #64

tioclk #60

tgclk #61

tmuxd #34
tmuxs #36
tmuxio #37
tmuxg #38
tmuxcg #50
tmuxcio #51

tiod #52, #53

tio #32

tgoe #58

tmuxexp #35

tmuxselexp #39

tiolat #40
tiosu #41
tioh #42
tioco #43
tior #44
tcesu #45
tceh #46

MUX Expander Output

tiobp #48

Q

D

CLKEN

CLK

tfdbk #47

tioob #49

tgr #65

TOE

ttoe #59

I/O Pin

tob #54
tobs #55
toeen #56
toedis #57

RESET

0902/gdxv/va

Y0,1,2,3, Enable

tgclkeng #62
tgclkenio #63

16

ispGDX Development System

Specifications ispGDX80VA

The ispGDX Development System supports ispGDX
design using a simple language syntax and an easy-to­use Graphical User Interface (GUI) called Design
Manager. From creation to In-System Programming, the
ispGDX system is an easy-to-use, self-contained design
tool delivered on CD-ROM media.

Features

• Easy-to-use Text Entry System

• ispGDX Design Compiler

- Design Rule Checker

- I/O Connectivity Checker

- Automatic Compiler Function

• Industry Standard JEDEC File for Programming

• Min / Max Timing Report

• Interfaces To Popular Timing Simulators

• User Electronic Signature (UES) Support

• Detailed Log and Report Files For Easy Design Debug

• On-Line Help

• Windows® 3.1x, Windows 95, Windows 98 and Win-

dows NT® Compatible Graphical User Interface

• SUN O/S, Command Line Driven version available

PC Version

With the ispGDX GUI for the PC, command line entry is
not required. The tools run under Microsoft Windows 3.1,
Windows 95, Windows 98 and Windows NT. When the
ispGDX software is invoked, the Design Manager and an
accompanying message window are displayed. The
Design Manager consists of the Menu Bar, Tool Bar,

Status Bar and the work area. The figure below shows
these elements of the ispGDX GUI.

The Menu Bar displays topics related to functions used in
the design process. Access the various drop-down menus
and submenus by using the mouse or “hot” keys. The
menu items available in the ispGDX system are FILE,
EDIT, DEVICE, INVOKE, INTERFACES, VIEW, WIN­DOW and HELP.

The Tool Bar is a quick and easy way to perform many of
the functions found in the menus with a single click of the
mouse. File, Edit, Undo, Redo, Find, Print Download and
Compiler are just some of the Icons found in the ispGDX
Tool Bar. For instance, the Compiler Icon performs the
same function as the Invoke => Compiler menu com­mands, including design analysis and rule checking and
the fitting operation.

The Status Bar displays action prompts and the line and
column numbers reflect the location of the cursor within
the message window or the work area.

Workstation Version

The ispGDX software is also available for use under the
Sun O/S 4.1.x or Solaris 2.4 or 2.5. The Sun version of the
ispGDX software is invoked from the command line
under the UNIX operating system. A GUI is not supported
in this environment.

In the UNIX environment, the ispGDX Design File (GDF)
must be created using a text editor. Once the GDF has
been created, invoke the ispGDX workstation software
from the UNIX command line. The following is an ex­ample of how to invoke ispGDX software.

Lattice’s ispGDX Development System Interface

Usage:

ispGDX
[-i input_file]
[-of[edif|orcad|viewlogic|verilog|vhdl]]
[-p part name]
[-r par_file]

Where:

-i input_file ispGDX design file

-of [edif | orcad | viewlogic | Output format
verilog | vhdl]

-p part_name ispGDX part number

-r par_file Read parameters from
parameter file

17

Type Dot Ext. Description

MUX
Input

MUX

Selection

Control

MUX

Output

.M0 MUXA Data input to 4:1 MUX
.M1 MUXB Data input to 4:1 MUX

MUX0 Selection input to 4:1 MUX
MUX1 Selection input to 4:1 MUX

.M2 MUXC Data Input to 4:1 MUX
.M3

.S0
.S1

MUXD Data input to 4:1 MUX

.CLK Clock for a register

.CE Clock enable for register clock

.A Adjacent MUX output of an I/O cell

.EN Latch enable for a latch signal
.OE Output enable for 3-state output

or bidirectional signal

ispGDXV Dot Ext

ispGDX Development System (Continued)

Specifications ispGDX80VA

The GDF File

The GDF file is a simple text description of the design
function, device and pin parameters. The file has four
parts: device selection, set and constant statements, a
pin section and a connection section. A sample file looks
like this:

// 32-Bit Data 3 to 1 Mux

DESIGN datamux;

PART ispGDX160V-7Q208;
PARAM SECURITY ON;
PARAM OPENDRAIN ON; // USE OPEN DRAIN

// OPTION

PARAM PULL HOLD; // USE BUS HOLD

// LATCH OPTION

SET BUS_A [dataA31..dataA0];
SET BUS_B [dataB31..dataB0];
SET BUS_C [dataC31..dataC0];
SET BUS_D [dataD31..dataD0];

INPUT BUS_A {A31..A0};
INPUT BUS_B {B31..B0};
INPUT BUS_C {C31..C0};
OUTPUT BUS_D {D31..D0};

This example shows a simple, but complete, 32-bit 3:1
MUX design. Once completed, the compiler takes over.

Powerful Syntax

Lattice’s ispGDX Design System uses simple, but power­ful, syntax to easily define a design. The !(bang) operator
controls pin polarity and can be used in both the pin and
connection sections of the design definition. Dot exten­sions define data inputs, select controls for the 4:1
multiplexor, and control inputs of sequential elements
and tri-state buffers. Dot extensions are .M# (MUX Input),
.S# (MUX Select), and control functions, such as .CLK,
.EN, .OE and .A (shown in adjacent table). Pin Attributes
are assigned in the pin section of the GDF as well.
SLOWSLEW selects the slow slew rate for an output
buffer. The Pull parameter can be used to select the
internal pull-up or bus hold latch. OPEN drain can be
used to select open drain operation. The COMB attribute
distinguishes the structure for bidirectional pins. If COMB
is used, the input register, or latch, of an output buffer will
be applied to bidirectional pins.

Please consult the ispGDX Development System Manual
for full details.

ispGDX GDF File Dot Extensions

INPUT [oe] {B37};
INPUT [clk] {B36};

INPUT [sel1] {B38};
INPUT [sel0] {B39};

BEGIN

BUS_D.m0 = BUS_A;
BUS_D.m1 = BUS_B;

END

BUS_D.m2 = BUS_C;
BUS_D.m3 = VCC; // Default all

BUS_D.s1 = sel1;
BUS_D.s0 = sel0;

BUS_D.oe = oe;
BUS_D.clk = clk;

// outputs to VCC

18

ispGDX Development System (Continued)

Specifications ispGDX80VA

The ispGDX Design System Compiler

After the GDF file is created, the compiler checks the
syntax and provides helpful hints and the location of any
syntax errors. The compiler performs design rule checks,
such as, clock and enable designations, the use of input/
output/BIDI usage, and the proper use of attributes. I/O
connectivity is also checked to ensure polarity, MUX
selection controls, and connections are properly made.
Compilation is completed automatically and report and
programming files are saved.

Reports Generated

When the ispGDX system compiles a design and gener­ates the specified netlists, the following output files are
created:

Report Files:

.log Compiler History
.rpt Compiler Report
.mfr Maximum Frequency Timing Report
.tsu Set-up and Hold Timing Report
.tco Clock to Out Timing Report
.tpt Timing Report

Third-Party Timing Simulation

The ispGDX Design System will generate simulation
netlists as specified by a user. The simulation netlist
formats available are: EDIF, Verilog (OVI compliant),
VHDL (VITAL compliant), Viewlogic, and OrCAD.

For In-System Programming, Lattice’s ispGDX devices
may be programmed, alone or in a chain with up to 100
other Lattice ISP devices, using Lattice’s ISP Daisy
Chain Download software. This powerful Windows-based
tool can be launched from the Tool Bar or by Invoking the
Download option from the drop down menu within the
ispGDX Design System. ISP Daisy Chain Download
version 7.1 or above supports the ispGDX Family de­vices.

Simulation File:

.sim Post-Route Simulation With LAC Format

Netlists:

.edo EDIF Output
.vlo Verilog Output
.ifo OrCAD Output
.vho VHDL non-VITAL with Maximum Delays Output
.vhn VHDL non-VITAL with Maximum Delays Output
.vto VHDL VITAL Output

Download:

.jed JEDEC Device Programming File

19

In-System Programmability

Specifications ispGDX80VA

All necessary programming of the ispGDXVA is done via
four TTL level logic interface signals. These four signals
are fed into the on-chip programming circuitry where a
state machine controls the programming.

On-chip programming can be accomplished using an
IEEE 1149.1 boundary scan protocol. The IEEE 1149.1­compliant interface signals are Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS) control. The EPEN pin is also used to enable or
disable the JTAG port.

The embedded controller port enable pin (EPEN) is used
to enable the JTAG tap controller and in that regard has
similar functionality to a TRST pin. When the pin is driven
high, the JTAG TAP controller is enabled. This is also true

Figure 9. ispJTAG Device Programming Interface

TDO

TDI

TMS

TCK

ispJTAG
Programming
Interface

EPEN

when the pin is left unconnected, in which case the pin is
pulled high by the permanent internal pullup. This allows
ISP programming and BSCAN testing to take place as
specified by the Instruction Table.

When the pin is driven low, the JTAG TAP controller is
driven to a reset state asynchronously. It stays there
while the pin is held low. After pulling the pin high the
JTAG controller becomes active. The intent of this fea­ture is to allow the JTAG interface to be directly controlled
by the data bus of an embedded controller (hence the
name Embedded Port Enable). The EPEN signal is used
as a “device select” to prevent spurious programming
and/or testing from occuring due to random bit patterns
on the data bus. Figure 9 illustrates the block diagram for
the ispJTAG interface.

ispGDX

80VA

Device

ispLSI

Device

ispMACH

Device

20

ispGDX

80VA

Device

ispGDX

80VA

Device

Boundary Scan

Specifications ispGDX80VA

The ispGDXVA devices provide IEEE1149.1a test capa­bility and ISP programming through a standard Boundary
Scan Test Access Port (TAP) interface.

The boundary scan circuitry on the ispGDXVA Family
operates independently of the programmed pattern. This

Figure 10. Boundary Scan Register Circuit for I/O Pins

SCANIN

(from previous

cell

BSCAN

Registers

DQ DQ

DQ

BSCAN
Latches

DQ

allows customers using boundary scan test to have full
test capability with only a single BSDL file.

The ispGDXVA devices are identified by the 32-bit JTAG
IDCODE register. The device ID assignments are listed
in Table 4.

HIGHZ

EXTEST

TOE

Normal

Function

EXTEST

PROG_MODE

Normal

Function

OE

0
1

0
1

I/O Pin

Shift DR

Clock DR

DQ

Update DR

Reset

SCANOUT
(to next cell)

Table 3. I/O Shift Register Order

DEVICE

ispGDX80VA TDI, TOE, RESET, Y1, Y0, I/O B10 .. B19, I/O C0 .. C19, I/O D0 .. D9, I/O B9 .. B0, I/O A19.. A0,

I/O D19 .. D10, TDO

I/O SHIFT REGISTER ORDER

I/O Shift Reg Order/ispGDXVA

Table 4. ispGDX80VA Device ID Codes

DEVICE

ispGDX80VA 0001, 0000, 0011, 0101, 0000, 0000, 0100, 0011

32-BIT BOUNDARY SCAN ID CODE

ID Code/GDX80VA

21

Boundary Scan (Continued)

Specifications ispGDX80VA

The ispJTAG programming is accomplished by execut­ing Lattice private instructions under the Boundary Scan
State Machine.

Downlowad (ispDCD™), ispCODE ‘C’ routines or any
third-party programmers. Contact Lattice Technical Sup­port to obtain more detailed programming information.

Details of the programming sequence are transparent to
the user and are handled by Lattice ISP Daisy Chain

Figure 11. Boundary Scan Register Circuit for Input-Only Pins

Input Pin

SCANIN

DQ

(from previous

cell

Shift DR

Clock DR

Figure 12. Boundary Scan State Machine

Test-Logic-Reset

1

0

Run-Test/Idle

0

Select-DR-Scan

1

0

Capture-DR

0

Shift-DR

1

Exit1-DR

0

0

1

SCANOUT
(to next cell)

Select-IR-Scan

1

0

Capture-IR

0

Shift-IR

1

Exit1-IR

0

111

0

1

Pause-DR

0

Exit2-DR

Update-DR

0

Pause-IR

1

Exit2-IR

1

Update-IR

0

0101

0

1

1

22

Specifications ispGDX80VA

Boundary Scan (Continued)

Figure 13. Boundary Scan Waveforms and Timing Specifications

TMS

TDI

TCK

TDO

Data to be

captured

Data to be

driven out

T

btch

T

btsu

T

btcl

T

btvo

T

btcsu

Data Captured

T

btuov

T

bth

T

btcp

T

btco

Valid Data Valid Data

T

btch

T

btuco

Valid Data Valid Data

T

btoz

T

btuoz

Symbol Parameter Min Max Units

t

btcp

t

btch

t

btcl

t

btsu

t

bth

t

rf

t

btco

t

btoz

t

btvo

t

btcpsu

t

btcph

t

btuco

t

btuoz

t

btuov

TCK [BSCAN test] clock pulse width 100 – ns
TCK [BSCAN test] pulse width high 50 – ns
TCK [BSCAN test] pulse width low 50 – ns
TCK [BSCAN test] setup time 20 – ns
TCK [BSCAN test] hold time 25 – ns
TCK [BSCAN test] rise and fall time 50 – mV/ns
TAP controller falling edge of clock to valid output – 25 ns
TAP controller falling edge of clock to data output disable – 25 ns
TAP controller falling edge of clock to data output enable – 25 ns
BSCAN test Capture register setup time 20 – ns
BSCAN test Capture register hold time 25 – ns
BSCAN test Update reg, falling edge of clock to valid output – 50 ns
BSCAN test Update reg, falling edge of clock to output disable – 50 ns
BSCAN test Update reg, falling edge of clock to output enable – 50 ns

23

Specifications ispGDX80VA

Signal Descriptions

Signal Name Description

I/O Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs,

each may be independently latched, registered or tristated. They can also each assume one other
control function (OE, CLK/CLKEN, and MUXsel as described in the text).

RESET / I/O D10 This pin can be configured by the user through software to act as a RESET pin or as an I/O (I/O D10)

The default is RESET. If programmed to act as RESET, this pin is an active LOW Input Pin and resets
all I/O Register outputs when LOW.

Y1/CLKEN1/TOE, Input Pins – These can be either Global Clocks or Clock Enables. In addition, Y1 is multiplexed with
Y0/CLKEN0 TOE. Each pin can drive any or all I/O cell registers. The Test Output Enable (TOE) pin tristates all I/O

pins when LOW

EPEN Input Pin – JTAG TAP Controller Enable Pin. When high, JTAG operation is enabled. When low,

JTAG TAP controller is driven to reset.
TDI Input Pin – Serial data input during ISP programming or Boundary Scan mode.
TCK Input Pin – Serial data clock during ISP programming or Boundary Scan mode.
TMS Input Pin – Control input during ISP programming or Boundary Scan mode.
TDO Output Pin – Serial data output during ISP programming or Boundary Scan mode.
GND Ground (GND)
VCC Vcc – Supply voltage (3.3V).
VCCIO Input – This pin is used if optional 2.5V output is to be used. Every I/O can independently select either

3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin

must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw

current from this supply.

24

Signal Locations: ispGDX80VA

Signal 100-Pin TQFP

RESET /I/O D10 90
Y0/CLKEN0 38
Y1/CLKEN1/TOE 87
EPEN 35
TDI 39
TCK 36
TMS 86
TDO 85
GND 6, 18, 29, 45, 56, 68, 79, 95
VCC 12, 37, 62, 88
VCCIO 89

I/O Locations: ispGDX80VA

Specifications ispGDX80VA

I/O Control 100

Signal Signal TQFP
I/O A0 CLK 1

I/O A1 OE 2
I/O A2 MUXsel1 3
I/O A3 MUXsel2 4
I/O A4 CLK 5

GND
I/O A5 OE 7
I/O A6 MUXsel1 8
I/O A7 MUXsel2 9
I/O A8 CLK 10
I/O A9 OE 11

VCC
I/O A10 MUXsel1 13
I/O A11 MUXsel2 14
I/O A12 CLK 15
I/O A13 OE 16
I/O A14 MUXsel1 17

GND
I/O A15 MUXsel2 19
I/O A16 CLK 20
I/O A17 OE 21
I/O A18 MUXsel1 22
I/O A19 MUXsel2 23

I/O B0 CLK 24

I/O Control 100

Signal Signal TQFP

I/O B1 OE 25
I/O B2 MUXsel1 26
I/O B3 MUXsel2 27
I/O B4 CLK 28

GND
I/O B5 OE 30
I/O B6 MUXsel1 31
I/O B7 MUXsel2 32
I/O B8 CLK 33
I/O B9 OE 34

VCC

I/O B10 MUXsel1 40
I/O B11 MUXsel2 41
I/O B12 CLK 42
I/O B13 OE 43
I/O B14 MUXsel1 44

GND

I/O B15 MUXsel2 46
I/O B16 CLK 47
I/O B17 OE 48
I/O B18 MUXsel1 49
I/O B19 MUXsel2 50

I/O C0 CLK 51
I/O C1 OE 52

I/O Control 100

Signal Signal TQFP

I/O C2 MUXsel1 53
I/O C3 MUXsel2 54
I/O C4 CLK 55

GND
I/O C5 OE 57
I/O C6 MUXsel1 58
I/O C7 MUXsel2 59
I/O C8 CLK 60
I/O C9 OE 61

VCC
I/O C10 MUXsel1 63
I/O C11 MUXsel2 64
I/O C12 CLK 65
I/O C13 OE 66
I/O C14 MUXsel1 67

GND
I/O C15 MUXsel2 69
I/O C16 CLK 70
I/O C17 OE 71
I/O C18 MUXsel1 72
I/O C19 MUXsel2 73

I/O D0 CLK 74
I/O D1 OE 75
I/O D2 MUXsel1 76

I/O Control 100

Signal Signal TQFP

I/O D3 MUXsel2 77
I/O D4 CLK 78

GND
I/O D5 OE 80
I/O D6 MUXsel1 81
I/O D7 MUXsel2 82
I/O D8 CLK 83
I/O D9 OE 84

VCC

VCCIO

I/O D10* MUXsel1 90

I/O D11 MUXsel2 91
I/O D12 CLK 92
I/O D13 OE 93
I/O D14 MUXsel1 94

GND

I/O D15 MUXsel2 96
I/O D16 CLK 97
I/O D17 OE 98
I/O D18 MUXsel1 99
I/O D19 MUXsel2 100

*I/O D10 is multiplexed with RESET. The functionality is programmable and selected through software.
Note: VCC and GND Pads Shown for Reference

25

Pin Configuration: ispGDX80VA

ispGDX80VA 100-Pin TQFP Pinout Diagram

Specifications ispGDX80VA

Control

CLK

OE
MUXsel1
MUXsel2

CLK

OE
MUXsel1
MUXsel2

CLK

OE
MUXsel1

MUXsel2

CLK

OE
MUXsel1

MUXsel2

CLK

OE
MUXsel1
MUXsel2

CLK

OE

Data

I/O A0
I/O A1
I/O A2
I/O A3
I/O A4

GND
I/O A5
I/O A6
I/O A7
I/O A8
I/O A9

VCC
I/O A10
I/O A11
I/O A12
I/O A13
I/O A14

GND
I/O A15
I/O A16
I/O A17
I/O A18
I/O A19

I/O B0
I/O B1

TMS

TDO

OE

CLK

I/O D9

I/O D8

OE

MUXsel2

MUXsel1

I/O D7

I/O D6

I/O D5

OE

Control

MUXsel2

Data

I/O D19

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

CLK

MUXsel1

I/O D18

9998979695949392919089888786858483828180797877

100

26272829303132333435363738394041424344454647484950

MUXsel2

I/O D17

I/O D16

I/O D15

OE

CLK

MUXsel1

GND

I/O D14

MUXsel2

I/O D13

I/O D12

I/O D11

MUXsel1

RESET/I/O D10

VCC

VCCIO

Y1/CLKEN1/TOE

ispGDX80VA

Top View

CLK

GND

I/O D4

MUXsel2

MUXsel1

I/O D3

I/O D2

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

Data

I/O D1
I/O D0
I/O C19
I/O C18
I/O C17
I/O C16
I/O C15
GND
I/O C14
I/O C13
I/O C12
I/O C11
I/O C10
VCC
I/O C9
I/O C8
I/O C7
I/O C6
I/O C5
GND
I/O C4
I/O C3
I/O C2
I/O C1
I/O C0

Control

OE

CLK
MUXsel2
MUXsel1

OE

CLK
MUXsel2

MUXsel1

OE

CLK
MUXsel2
MUXsel1

OE

CLK
MUXsel2
MUXsel1

OE

CLK
MUXsel2
MUXsel1

OE

CLK

Data

I/O B2

I/O B3

Control

MUXsel1

MUXsel2

GND

I/O B4

CLK

I/O B5

I/O B6

OE

MUXsel1

I/O B7

I/O B8

I/O B9

OE

CLK

MUXsel2

TCK

EPEN

TDI

VCC

I/O B10

Y0/CLKEN0

MUXsel1

26

I/O B11

I/O B12

I/O B13

OE

CLK

MUXsel2

GND

I/O B14

I/O B15

MUXsel1

MUXsel2

I/O B16

I/O B17

I/O B18

OE

CLK

MUXsel1

I/O B19

MUXsel2

Part Number Description

Specifications ispGDX80VA

ispGDX 80VA X XXXX X

Device Family

Grade

Blank = Commercial

Device Number

I = Industrial

Speed

3 = 3.5ns Tpd

Package

T100 = 100-Pin TQFP
5 = 5.0ns Tpd
7 = 7.0ns Tpd
9 = 9.0ns Tpd

0212/gdx80va

Ordering Information

COMMERCIAL

FAMILY ORDERING NUMBER PACKAGEtpd (ns)

100-Pin TQFP3.5 ispGDX80VA-3T100

ispGDXVA

INDUSTRIAL

FAMILY ORDERING NUMBER PACKAGEtpd (ns)

ispGDXVA

Note: The ispGDX80VA devices are dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster,
e.g. ispGDX80VA-3T100-5I.

100-Pin TQFP5 ispGDX80VA-5T100
100-Pin TQFP7 ispGDX80VA-7T100

Table 2-0041A/gdx80va

100-Pin TQFP5 ispGDX80VA-5T100I
100-Pin TQFP7 ispGDX80VA-7T100I
100-Pin TQFP9 ispGDX80VA-9T100I

Table 2-0041/gdx80va

27