Datasheet ISL9N7030BLS3ST, ISL9N7030BLP3 Datasheet (Fairchild Semiconductor)

E

Data Sheet January2002

30V, 0.009 Ohm, 75A, N-Channel Logic Level UltraFET® Trench Power MOSFETs

This devi ce em ploys a new advanced trench MO SFET technology and features low gate charge while maintaining low on-resistance.

Optimized for switching ap plications, this device improves the overa ll effi ci enc y of DC/D C converters and allows operation to higher switching frequencies.

Packaging

ISL9N7030BLS3ST

JEDEC TO-263AB

DRAIN

(FLANGE)

ISL9N7030BLP3

JEDEC TO-220AB

SOURCE

DRAIN

GAT

ISL9N7030BLP3, ISL9N7030BLS3ST

PWM

Optimized

Features

•Fast Switching

•r

•Qg Total 24nC (Typ), VGS = 5V

•Q

•C

Symbol

= 0.0064Ω (Typ), V

DS(ON)

= 0.010Ω (Typ), V

DS(ON)

(Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11nC

gd

(Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2600pF

ISS

GS

= 10V

= 4.5V

D

G

GATE

SOURCE

DRAIN

(FLANGE)

S

Ordering Information

PART NUMBER PACKAGE BRAND

ISL9N7030BLP3 TO-220AB 7030BL ISL9N7030BLS3ST TO-263AB (Tape and Reel) 7030BL

Absolute Maximum Ratings

SYMBOL PARAMETER ISL9N7030BLP3, I SL9N703 0BLS3ST UNITS

V

DSS

V

DGR

V

I

DM

P

, T

T

J

T

THERMAL SPECIFICATIONS

R R R

NOTE:

1. T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

Drain to Source Voltage (Note 1) 30 V Drain to Gate Voltage (RGS = 20kΩ) (Note 1) 30 V Gate to Source Voltage ±20 V

GS

Drain Current

I

D

I

D

I

D

STG

L

pkg

θJC θJA θJA

= 25oC to 150oC.

J

Continuous (T Continuous (T Continuous (T Pulsed Drain Current

Power Dissipation

Derate Above 25 Operating and Storage Temperature -55 to 175 Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s

Package Body for 10s, See T e chbrief TB334

Thermal Resistance Junction to Case, TO-220, TO-263 1.5 Thermal Resistance Junction to Ambient, TO-220, TO-263 62 Thermal Resistance Junction to Ambient, TO-263, 1in2 copper pad area 43

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

C C C

TC = 25oC, Unless Otherwise Specified

= 25oC, VGS = 10V) (Figure 2) = 100oC, VGS = 4.5V) (Figure 2) = 25oC, VGS = 10V, R

o

C

For severe environments, see our Automotive products.

= 43oC/W)

θJA

75 48 15

Figure 4

100

0.67

300 260

A A A A

W

W/oC

o

C

o

C

o

C

o

C/W

o

C/W

o

C/W

ISL9N7030BLP3, ISL9N703 0BLS3ST

Electrical Specifications

TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V Drain to Source On Resistance r

SWITCHING SPECIFICATIONS (V

GS

= 4.5V) Turn-On Time t Turn-On Delay Time t Rise Time t Turn-Off Delay Time t Fall Time t Turn-Off Time t SWITCHING SPECIFICATIONS (V

GS

= 10V) Turn-On Time t Turn-On Delay Time t Rise Time t Turn-Off Delay Time t Fall Time t Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charge at 10V Q Total Gate Charge at 5V Q Threshold Gate Charge Q Gate to Source Gate Charge Q Gate to Drain “Miller” Charge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C

DSSID

DSS

VDS = 25V, VGS = 0V - - 1 µA V

GSS

GS(TH)VGS

DS(ON)ID

ON

VGS = ±20V - - ±100 nA

I

D

VDD = 15V, ID = 15A V

d(ON)

d(OFF)

OFF

ON

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(5)

g(TH)

ISS OSS RSS

(Figures 13, 17, 18)

r

f

VDD = 15V, ID = 15A, V (Figures 14, 17, 18)

r

f

VGS = 0V to 5V - 24 37 nC VGS = 0V to 1V - 2.6 4.0 nC

gs

gd

VDS = 15V, VGS = 0V, f = 1MHz (Figure 11)

= 250µA, VGS = 0V (Figure 10) 30 - - V

= 25V, VGS = 0V, TC = 150oC - - 250 µA

DS

= VDS, ID = 250µA (Figure 9 1 - 3 V = 75A, VGS = 10V (Figures 7, 8) - 0.007 0.009 Ω = 48A, VGS = 4.5V (Figure 7) - 0.010 0.012 Ω

- - 122 ns

= 4.5V, RGS = 6.2Ω

GS

-15-ns

-67-ns

-35-ns

-32-ns

- - 100 ns

- - 71 ns

= 10V, R

GS

= 6.2Ω,

-8-ns

-40-ns

-64-ns

-31-ns

- - 142 ns

= 0V to 10V VDD = 15V,

I

= 48A,

D

= 1.0mA

I

g(REF)

(Figures 12, 15, 16)

-4568nC

-7-nC

-8-nC

- 2600 - pF

- 520 - pF

- 225 - pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

I

Source to Drain Diode Voltage V

Reverse Recovery Time t Reverse Recovered Charge Q

SD

rr

RR

= 48A - - 1.25 V

SD

= 20A - - 1.0 V

I

SD

ISD = 48A, dISD/dt = 100A/µs--26ns ISD = 48A, dISD/dt = 100A/µs--14nC

Typical Performance Curves

5

ISL9N7030BLP3, ISL9N703 0BLS3ST

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125

150

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATI ON vs CASE

TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

80

60

40

, DRAIN CURRENT (A)

20

D

I

0

25 50 75 100 125 150 17

VGS = 4.5V

VGS = 10V

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

, NORMALIZED Z

0.1

+ T

P

DM

t

1

t

C

0

10

2

1

10

θJC

THERMAL IMPEDANCE

0.01

SINGLE PULSE

-5

10

-4

10

-3

10

NOTES: DUTY FACTOR: D = t PEAK TJ = PDM x Z

-2

10

1/t2

x R

θJC

-1

10

t, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

, PEAK CURRENT (A) I

DM

1000

100

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

50

-5

10

VGS = 10V

VGS = 5V

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

TC = 25oC

FOR TEMPERATURES ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

0

10

150

C

1

10

FIGURE 4. PEAK CURRENT CAPABILITY

5

0

ISL9N7030BLP3, ISL9N703 0BLS3ST

Typical Performance Curves

150

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

125

100

75

50

, DRAIN CURRENT (A)

D

I

25

= 15V

V

DD

TJ = 175oC

TJ = 25oC

0

1234

VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 5. TRANSFER CHARACTERISTICS FIGURE 6. SATURATION CHARACTERISTICS

25

ID = 50A

20

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

T

= 25oC

C

(Continued)

TJ = -55oC

150

T

= 25oC

C

125

100

75

50

, DRAIN CURRENT (A)

D

I

25

0

0 0.5 1.0 1.5 2.

VDS, DRAIN TO SOURCE VOLTAGE (V)

2.0

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

1.5

VGS = 10V

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

VGS = 4.5V

VGS = 3.5V

VGS = 3V

15

, DRAIN TO SOURCE

DS(ON)

r

ID = 14A

ON RESIST ANCE (mΩ)

10

5

24681

ID = 75A

VGS, G ATE TO SOURCE VOLTAGE (V)

FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

1.2

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 -40 0 40 80 120 160 20

TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

1.0

ON RESISTANCE

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 20

TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 75A

FIGURE 8. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.2

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 20 TJ, JUNCTION TEMPERATURE (oC)

ID = 250µA

FIGURE 9. NORMALIZED GATE THRESHOLD VOL TAGE vs

JUNCTION TEMPERATURE

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

0 0

0

V

I

ISL9N7030BLP3, ISL9N703 0BLS3ST

Typical Performance Curves

(Continued)

4000

1000

C

RSS

= C

C

ISS

GD

= C

GS

+ C

GD

C

OSS

≅ C

DS

+ C

GD

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

100

0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

250

VGS = 4.5V, VDD = 15V, ID = 15A

200

150

100

SWITCHING TIME (ns)

50

t

d(OFF)

t

r

t

f

t

d(ON)

10

V

= 15V

DD

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

3

0

0 1020304050

WAVEFORMS IN DESCENDING ORDER:

= 48A

I

D

ID = 14A

Qg, GATE CHARGE (nC)

NOTE: Refer to Fairchild Application Not e s AN7254 and AN7260.

FIGURE 12. GA TE CHARGE W A VEFORMS FOR CONSTANT

GATE CURRENT

350

VGS = 10V, VDD = 15V, ID = 15A

300

250

200

150

100

SWITCHING TIME (ns)

50

t

d(OFF)

t

f

t

r

t

d(ON)

0

0 102030405

RGS, GATE TO SOURCE RESISTANCE (Ω)

0

0 102030405

RGS, G ATE TO SOURCE RESISTANCE (Ω)

FIGURE 13. SWITCHING TIME vs GATE RESISTANCE FIGURE 14. SWITCHING TIME vs GA TE RESISTANCE

Test Circuits and Waveforms

V

DS

R

L

V

GS

+

V

DD

-

DUT

I

g(REF)

FIGURE 15. GATE CHARGE TEST CIRCUIT FIGURE 16. GATE CHARGE WAVEFORMS

V

DD

V

GS

0

g(REF)

0

V

= 1V

GS

Q

g(TOT)

V

DS

Q

g(5)

VGS = 5V

Q

g(TH)

Q

gs

Q

gd

V

= 10

GS

1)

)

R

F

A

ISL9N7030BLP3, ISL9N703 0BLS3ST

Test Circuits and Waveforms

V

GS

R

GS

V

GS

(Continued)

V

DS

R

DUT

L

+

V

DD

-

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. SWITCHING TIME WAVEFORM

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable d evice power dissipation, P application. Therefore the application’s ambient temperature, T

(oC), and thermal resistance R

A

to ensure that T

is never exceeded. Equation 1

JM

(oC/W) must be review ed

θJA

mathematically represents the relationship and serves as the basis for establishing the rating of the part.

TJMT

–()

P

DM

A

------------------ ------------ -=

Z

θJA

In using surf ace m oun t devices such as the TO-263 package, the environment in which it is applied will have a significant influen ce on the part’s current and m axi m um power dissipation ratings. Precise determination of P complex an d influenced by many factors:

DM

, in an

DM

(EQ.

is

t

ON

t

d(ON)

t

V

DS

90%

0

V

GS

10%

0

r

10%

50%

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impeda nc e curve.

Displayed on the curve are R

values listed in the Electrical

θJA

Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, P

DM

.

Thermal resistances corresponding to other copper areas can be obtained from Figure 19 or by calculation using Equation 2. R

is defined as the natural log of the area times a coefficient

θJA

added to a constant. The area, in square inches is the top copper area including the gate and source pads.

θJA

26.51

19.84

----------------------------------------+=

0.262 A rea

+()

(EQ. 2

1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board.

80

R

= 26.51+ 19.84/(0.262+Area)

θJA

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks .

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applica tions , the pulse width, the

60

C/W)

o

(

θJA

R

40

duty cycle and the transient thermal response of the part, the board and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application ev al uati on. Figure 19 defines the R

for the device as a function of the top

θJA

copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 s econds

20

0.1 AREA, TOP COPPER AREA (in2)

110

IGURE 19. THERMAL RESISTANCE vs MOUNTING PAD ARE

of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temper ature or pow er dissipation. Pu lse application s

ISL9N7030BLP3, ISL9N703 0BLS3ST

PSPICE Electrical Model

.SUBCKT ISL9N7030BL 2 1 3 ; rev Dec2000

CA 12 8 1.5e-9 CB 15 14 1.75e-9 CIN 6 8 2.35e-9

DBODY 7 5 DBODYMOD DBREAK 5 11 D B REAK MOD DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 32.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1

IT 8 17 1 LDRAIN 2 5 1e-9

LGATE 1 9 4.58e-9 LSOURCE 3 7 1.47e-9

GATE

1

MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.5e-3 RGATE 9 20 3.4 RLDRAIN 2 5 10 RLGATE 1 9 45.8 RLSOURCE 3 7 14.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.55e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTE MPMOD 1

S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

LGATE

RLGATE

RGATE

9

CA

-

ESG

+

EVTEMP +

-

18 22

20

S1A

12

13

8

S1B

EGS EDS

6 8

13

10

RSLC2

6

14 13

+

6 8

-

DPLCAP

EVTHRES

+

19

8

S2A

S2B

15

CB

CIN

-

+

-

5

51

5

51

21

MSTRO

14

5 8

RSLC1

+

ESLC

-

50 RDRAIN

16

8

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

LDRAIN

RLDRAIN

11

+

17 18

DBODY

DRAIN

2

-

LSOURCE

7

RLSOURCE

RVTEMP 19

SOURCE

3

-

VBAT

+

22

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),5))} .MODEL DBODYMOD D (IS = 1.9e-11 N=1.075 RS = 4.2e-3 TRS1 = 9e-4 TRS2 = 1e-6 XTI=2.2 CJO = 1.1e-9 TT = 8e-11 M = 0.49)

.MODEL DBREAKMOD D (RS = 1.7e- 1TRS1 = 1e- 3TRS2 = -8.9e-6) .MODEL DPLCAPMOD D (CJO = 8.2e-1 0IS = 1e-3 0N = 10 M = 0.45) .MODEL MMEDMOD NMOS (VTO = 1.9 KP = 3 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.4) .MODEL MSTR OM OD NMOS (VTO = 2.35KP = 90 I S = 1e-3 0 N= 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKM OD NMOS (VTO = 1 .6 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 34 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1e- 3TC2 = -7e-7) .MODEL RDRAINMOD RES (TC1 = 7e-3 TC2 = 1e-5) .MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.7e-3 TC2 = -1e-5) .MODEL RVTEMPMOD RES (TC1 = -1.8e- 3TC2 = 1e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF= -0.8) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.8 VOFF= -4.0) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.3 VOFF= 0.2) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.3)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Special ist Conference Records, 1991, writ ten by William J. Hepp and C. Frank Wheatley.

ISL9N7030BLP3, ISL9N703 0BLS3ST

SABER Electrical Model

REV Dec 2000 template ISL 9N7030BL n2, n1,n3

electrical n2,n1,n3 { var i iscl dp..model dbodymod = (i sl = 1.9e-11, nl=1.075 , rs = 4.2e-3, trs1 = 9e-4, trs2 = 1e- 6, xti=2.2, cjo = 1.1e-9, tt = 8e-11, m = 0.49,) dp..model dbreakmod = (rs =0.17, trs1 = 1e-3, trs2 = - 8.9e-6) dp..model dplcapmod = (cjo = 8.2e-10, isl=10e-30, nl=10, m=0.45) m..model mmedmod = (type=_n, vto = 1.9, kp=3, is=1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.35, kp = 90, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.6, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -0.8) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -0.8, voff = -4.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3)

c.ca n12 n8 = 1.5e-9 c.cb n15 n14 = 1.75e-9 c.cin n6 n8 = 2.35e-9

dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9

l.lgate n1 n9 = 4.58e-9 l.lsource n3 n7 = 1.47e-9

GATE

LGATE

1

RLGATE

RGATE

9

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n1 7 n1 8 = 1, tc1 = 1e-3, tc2 = -7e-7 res.rdrain n50 n16 = 2.5e-3, tc1 = 7e-3, t c2 = 1e-5

12

res.rgate n9 n20 = 3.4 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 45.8 res.rlsource n3 n7 = 14.7 res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-6

CA

res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.55e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = -1e-6 res.rvthres n22 n8 = 1, tc1 = -2.7e-3, tc2 = -1e-5

spe.ebreak n11 n7 n17 n18 = 32.7 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = mod e l=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc =1

ESG

EVTEMP +

18 22

20

S1A

13

S1B

EGS EDS

DPLCAP

10

RSLC2

-

6 8

EVTHRES

+

6

-

S2A

14 13

8

S2B

13

+

6 8

-

5

RSLC1

51

ISCL

MMED

DBREAK

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

17 18

-

50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5 8

-

LSOURCE

7

RLSOURCE

RVTEMP 19

-

VBAT

+

22

LDRAIN

RLDRAIN

DBODY

DRAIN

2

SOURCE

3

equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e-6/200))** 5)) } }

SPICE Thermal Model

REV 23 Sept 2000

ISL9N7030BL

CTHERM1 th 6 2.0e-4 CTHERM2 6 5 3.0e-3 CTHERM3 5 4 3.4e-3 CTHERM4 4 3 4.0e-3 CTHERM5 3 2 1.0e-2 CTHERM6 2 tl 5.0e-2

RTHERM1 th 6 1.5e-3 RTHERM2 6 5 5.5e-3 RTHERM3 5 4 5.2e-2 RTHERM4 4 3 3.5e-1 RTHERM5 3 2 3.8e-1 RTHERM6 2 tl 4.1e-1

ISL9N7030BLP3, ISL9N703 0BLS3ST

RTHERM1

RTHERM2

JUNCTION

th

CTHERM1

6

CTHERM2

5

SABER Thermal Model

SABER thermal model ISL9N7030BL template thermal_model th tl

thermal_c th, tl { ctherm.ctherm1 th 6 = 2.0e-4 ctherm.ctherm2 6 5 = 3.0e-3 ctherm.ctherm3 5 4 = 3.4e-3 ctherm.ctherm4 4 3 = 4.0e-3 ctherm.ctherm5 3 2 = 1.0e-2 ctherm.ctherm6 2 tl = 5.0e-2

rtherm.rtherm1 th 6 = 1.5e-3 rtherm.rtherm2 6 5 = 5.5e-3 rtherm.rtherm3 5 4 = 5.2e-2 rtherm.rtherm4 4 3 = 3.5e-1 rtherm.rtherm5 3 2 = 3.8e-1 rtherm.rtherm6 2 tl = 4.1e-1 }

RTHERM3

RTHERM4

RTHERM5

RTHERM6

CTHERM3

4

CTHERM4

3

CTHERM5

2

CTHERM6

tl

CASE

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Advance Information

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No Identification Needed

Formative or In Design

First Production

Full Production

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

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This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Obsolete

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Rev. H4

Datasheet ISL9N7030BLS3ST, ISL9N7030BLP3 Datasheet (Fairchild Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual