±
θ
θ
θ
θ
ISL9N322AP3/ISL9N322AS3ST
January 2002
ISL9N322AP3/ISL9N322AS3ST
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
General Description
This device employs a new advanced trench MOSFET
Features
• Fast switching
technology and features low gate charge while maintaining
low on-resistance.
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
Applications
• DC/DC converters
DRAIN
(FLANGE)
GATE
SOURCE
•r
•r
•Q
•Q
•C
DRAIN
(FLANGE)
= 0.018 Ω (Typ), V
DS(ON)
= 0.028 Ω (Typ), V
DS(ON)
(Typ) = 9nC, V
g
(Typ) = 3nC
gd
(Typ) = 970pF
ISS
SOURCE
DRAIN
GATE
GS
= 5V
GS
GS
= 10V
= 4.5V
D
G
S
TO-263AB TO-220AB
MOSFET Maximum Ratings
T
= 25°C unless otherwise noted
A
Symbol Parameter Ratings Units
V
DSS
V
GS
Drain to Source Voltage 30 V
Gate to Source Voltage
Drain Current
Continuous (T
I
D
Continuous (T
Continuous (T
= 25
C
= 100
C
= 25
C
o
C, V
o
C, V
= 10V)
GS
o
C, V
= 4.5V) 20 A
GS
= 10V, R
GS
o
= 43
C/W) 9 A
JA
Pulsed Figure 4 A
P
D
T
, T
J
STG
Power dissipation
Derate above 25
o
C
Operating and Storage Temperature -55 to 175
20 V
35 A
50
0.33
W/
W
o
C
o
C
Thermal Characteristics
R
JC
R
JA
R
JA
Thermal Resistance Junction to Case TO-220, TO-263 3
Thermal Resistance Junction to Ambient TO-220, TO-263 62
Thermal Resistance Junction to Ambient TO-263, 1in
2
copper pad area 43
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
N322AS ISL9N322AS3ST TO-263AB 330mm 24mm 800 units
N322AP ISL9N322AP3 TO-220AB Tube N/A 50 units
©2002 Fairchild Semiconductor Corporation
o
C/W
o
C/W
o
C/W
Rev. B, January 2002
µ
±
Ω
T
Electrical Characteristics
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
B
I
DSS
I
GSS
VDSS
Drain to Source Breakdown Voltage I
Zero Gate Voltage Drain Current
Gate to Source Leakage Current V
= 250 µ A, V
D
V
= 25V - - 1
DS
V
= 0V T
GS
= ± 20V - -
GS
= 0V 30 - - V
GS
o
= 150
C
- - 250
100 nA
On Characteristics
V
GS(TH)
r
DS(ON)
Gate to Source Threshold Voltage V
Drain to Source On Resistance
= V
GS
I
= 35A, V
D
I
= 20A, V
D
, I
= 250 µ A1-3V
DS
D
= 10V - 0.018 0.022
GS
= 4.5V - 0.028 0.033
GS
Dynamic Characteristics
C
C
C
Q
Q
Q
Q
Q
ISS
OSS
RSS
g(TOT)
g(5)
g(TH)
gs
gd
Input Capacitance
Output Capacitance - 205 - pF
Reverse Transfer Capacitance - 80 - pF
Total Gate Charge at 10V V
Total Gate Charge at 5V V
Threshold Gate Charge V
Gate to Source Gate Charge - 3.5 - nC
V
= 15V, V
DS
f = 1MHz
= 0V to 10V
GS
= 0V to 5V - 9 14 nC
GS
= 0V to 1V - 1.0 1.5 nC
GS
GS
= 0V,
V
DD
I
D
I
g
= 15V
= 20A
= 1.0mA
- 970 - pF
18 27 nC
Gate to Drain “Miller” Charge - 3.0 - nC
µ
ISL9N322AP3/ISL9N322AS3ST
A
(V
(V
= 4.5V)
GS
= 10V)
GS
Switching Characteristics
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Turn-On Time
Turn-On Delay Time - 11 - ns
Rise Time - 47 - ns
Turn-Off Delay Time - 24 - ns
Fall Time - 28 - ns
Turn-Off Time - - 78 ns
Switching Characteristics
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Turn-On Time
Turn-On Delay Time - 7 - ns
Rise Time - 29 - ns
Turn-Off Delay Time - 45 - ns
Fall Time - 27 - ns
Turn-Off Time - - 108 ns
Unclamped Inductive Switching
t
AV
Avalanche Time I
Drain-Source Diode Characteristics
V
SD
t
rr
Q
RR
Source to Drain Diode Voltage
Reverse Recovery Time I
Reverse Recovered Charge I
- - 87 ns
V
DD
V
GS
= 15V, I
= 4.5V, R
= 9A
D
GS
= 16 Ω
- - 54 ns
V
= 15V, I
DD
V
= 10V, R
GS
= 2.7A, L = 3mH 180 - -
D
I
= 20A - - 1.25 V
SD
I
= 10A - - 1.0 V
SD
= 20A, dI
SD
= 20A, dI
SD
= 9A
D
= 16 Ω
GS
/dt = 100A/ µ s- - 25 ns
SD
/dt = 100A/ µ s- - 17 nC
SD
s
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
ISL9N322AP3/ISL9N322AS3ST
Typical Characteristic
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 175
TC, CASE TEMPERATURE (oC)
125
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
150
40
VGS = 10V
30
20
, DRAIN CURRENT (A)
10
D
I
0
25 50 75 100 125 150 175
VGS = 4.5V
TC, CASE TEMPERATURE (oC)
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
0.1
, NORMALIZED
θJA
Z
THERMAL IMPEDANCE
0.01
-5
10
500
VGS = 10V
100
, PEAK CURRENT (A)
DM
I
VGS = 5V
30
-5
10
SINGLE PULSE
-4
10
-3
10
t, RECTANGULAR PULSE DURATION (s)
-2
10
NOTES:
DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z
-1
10
Figure 3. Normalized Maximum Transient Thermal Impedance
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-4
10
-3
10
-2
10
t, PULSE WIDTH (s)
10
TC = 25oC
FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:
I = I
-1
25
P
DM
t
1
2
x R
+ T
θJA
θJA
0
10
o
C DERATE PEAK
175 - T
C
150
0
10
t
2
A
1
10
1
10
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
Typical Characteristic (Continued)
ISL9N322AP3/ISL9N322AS3ST
80
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
= 15V
V
DD
60
40
, DRAIN CURRENT (A)
D
I
20
TJ = 175oC
0
123456
VGS, GATE TO SOURCE VOLTAGE (V)
TJ = 25oC
TJ = -55oC
80
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
60
VGS = 10V
40
, DRAIN CURRENT (A)
20
D
I
0
0 0.5 1.0 1.5 2.0 2.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics Figure 6. Saturation Characteristics
50
40
ID = 20A
30
, DRAIN TO SOURCE
20
ON RESISTANCE (mΩ)
DS(ON)
r
10
246810
ID = 35A
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.5
ON RESISTANCE
1.0
NORMALIZED DRAIN TO SOURCE
0.5
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
VGS = 5V
VGS = 4.5V
VGS = 3.5V
VGS = 10V, ID = 35A
Figure 7. Drain to Source On Resistance vs Gate
Voltage and Drain Current
1.2
1.0
0.8
NORMALIZED GATE
0.6
THRESHOLD VOLTAGE
0.4
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.2
ID = 250µA
1.1
1.0
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
0.9
-80 -40 0 40 80 120 160 200
T
, JUNCTION TEMPERATURE (oC)
J
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Typical Characteristic (Continued)
ISL9N322AP3/ISL9N322AS3ST
2000
C
= CGS + C
ISS
GD
1000
C
≅ C
+ C
OSS
GS
GD
C
= C
RSS
GD
C, CAPACITANCE (pF)
100
V
= 0V, f = 1MHz
GS
50
0.1 1
VDS, DRAIN TO SOURCE VOLTAGE (V)
10 30
Figure 11. Capacitance vs Drain to Source
Voltage
100
VGS = 4.5V, VDD = 15V, ID = 9A
80
60
40
SWITCHING TIME (ns)
20
0
0 1020304050
t
d(OFF)
t
d(ON)
RGS, GATE TO SOURCE RESISTANCE (Ω)
t
r
t
f
10
VDD = 15V
8
6
4
2
, GATE TO SOURCE VOLTAGE (V)
GS
V
0
0 5 10 15 20
WAVEFORMS IN
DESCENDING ORDER:
ID = 35A
I
= 20A
D
Qg, GATE CHARGE (nC)
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
150
VGS = 10V, VDD = 15V, ID = 9A
t
d(OFF)
100
t
f
50
SWITCHING TIME (ns)
0
0 1020304050
RGS, GATE TO SOURCE RESISTANCE (Ω)
t
t
r
d(ON)
Figure 13. Switching Time vs Gate Resistance Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
V
DS
L
I
VARY tP TO OBTAIN
REQUIRED PEAK I
V
GS
R
AS
G
+
V
DD
-
AS
DUT
t
0V
P
I
AS
0
0.01Ω
Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
BV
DSS
t
P
t
AV
V
DS
V
DD
Test Circuits and Waveforms (Continued)
V
DS
R
L
V
GS
+
V
DD
-
DUT
I
g(REF)
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
V
0
I
g(REF)
0
DD
V
GS
V
= 1V
GS
Q
g(TH)
Q
gs
Q
g(TOT)
V
DS
Q
g(5)
Q
gd
VGS = 5V
ISL9N322AP3/ISL9N322AS3ST
V
= 10V
GS
V
DS
R
L
V
GS
R
GS
V
GS
DUT
+
V
DD
-
V
DS
0
V
GS
10%
0
t
d(ON)
90%
t
ON
50%
10%
t
r
PULSE WIDTH
t
d(OFF)
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
90%
t
OFF
50%
t
f
90%
10%
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance R
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
TJMTA–()
P
-------------------------------=
DM
Z
θJA
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally
for the device as a function of the top
θJA
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
(oC/W)
θJA
(EQ. 1)
C/W)
o
(
θJA
R
Figure 21. Thermal Resistance vs Mounting
ISL9N322AP3/ISL9N322AS3ST
80
R
= 26.51+ 19.84/(0.262+Area)
θJA
60
40
20
0.1
AREA, TOP COPPER AREA (in2)
Pad Area
110
Displayed on the curve are R
Electrical Specifications table. The points were chosen to
values listed in the
θJA
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. R
times a coefficient added to a constant. The area, in square
is defined as the natural log of the area
θJA
inches is the top copper area including the gate and source
pads.
R
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
θJA
26.51
19.84
-------------------------------------+=
0.262 Area+()
(EQ. 2)
PSPICE Electrical Model
.SUBCKT ISL9N322AP3 2 1 3 ; rev April 2001
CA 12 8 7e-10
CB 15 14 7e-10
CIN 6 8 9.1e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 32.08
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 4.53e-9
GATE
1
LGATE
RLGATE
LSOURCE 3 7 5.38e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.2e-3
RGATE 9 20 2.59
RLDRAIN 2 5 10
RLGATE 1 9 45.3
RLSOURCE 3 7 53.8
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.3e-2
RGATE
9
CA
ESG
EVTEMP
+
18
22
20
S1A
12
S1B
EGS EDS
DPLCAP
10
RSLC2
6
8
EVTHRES
+
+
6
-
S2A
13
14
8
13
S2B
13
+
+
6
8
-
-
5
RSLC1
51
+
5
ESLC
51
50
RDRAIN
16
21
-
19
8
MSTRO
CIN
15
CB
8
14
+
5
8
-
MMED
DBREAK
EBREAK
MWEAK
RSOURCE
RBREAK
17 18
IT
8
RVTHRES
11
+
17
18
-
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*110),6))}
.MODEL DBODYMOD D (IS = 8.3e-12 N = 1.08 RS = 9.9e-3 TRS1 = 8.9e-4 TRS2 = 1e-6 XTI = 2.7 CJO = 6.2e-10 TT = 7e-11 M
= 0.62)
.MODEL DBREAKMOD D (RS = 6e-1 TRS1 = 1e-3 TRS2 = -8.5e-6)
.MODEL DPLCAPMOD D (CJO = 3.1e-10 IS = 1e-30 N = 10 M = 0.46)
.MODEL MMEDMOD NMOS (VTO = 1.95 KP = 3.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.59)
.MODEL MSTROMOD NMOS (VTO = 2.32 KP = 35 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.6 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 25.9 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = -7e-7)
.MODEL RDRAINMOD RES (TC1 = 3.4e-2 TC2 = 1e-4)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.2e-3 TC2 = -8e-6)
.MODEL RVTEMPMOD RES (TC1 = -2e-3 TC2 = 1.05e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF = -1.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF = -4.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF = 0.3)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.3 VOFF = -0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
7
RVTEMP
19
-
+
22
LDRAIN
RLDRAIN
DBODY
LSOURCE
RLSOURCE
VBAT
DRAIN
2
SOURCE
3
ISL9N322AP3/ISL9N322AS3ST
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
SABER Electrical Model
REV April 2001
template ISL9N322AP3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 8.3e-12, n1 = 1.08 rs = 9.9e-3, trs1 = 8.9e-4, trs2 = 1e-6, xti = 2.7, cjo = 6.2e-10, tt = 7e-11, m = 0.62)
dp..model dbreakmod = (rs = 6e-1, trs1 = 1e-3, trs2 = -8.5e-6)
dp..model dplcapmod = (cjo = 3.1e-10, isl =10e-30, nl =10, m = 0.46)
m..model mmedmod = (type=_n, vto = 1.95, kp = 3.5, is = 1e-30, tox =1)
m..model mstrongmod = (type=_n, vto = 2.32, kp = 35, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.6, kp = 0.05, is = 1e-30, tox = 1, rs = 0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -1.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -4.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.3)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -0.5)
c.ca n12 n8 = 7e-10
DPLCAP
10
c.cb n15 n14 = 7e-10
c.cin n6 n8 = 9.1e-10
RSLC2
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
LGATE
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 4.53e-9
l.lsource n3 n7 = 5.38e-9
GATE
1
RLGATE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
RGATE
9
ESG
EVTEMP
+
18
22
20
+
-
6
8
EVTHRES
+
6
-
19
8
CIN
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -7e-7
res.rdrain n50 n16 = 1.2e-3, tc1 = 3.4e-2, tc2 = 1e-4
res.rgate n9 n20 = 2.59
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 45.3
res.rlsource n3 n7 = 53.8
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
CA
S1A
12
13
8
S1B
EGS EDS
S2A
15
14
13
S2B
13
CB
+
+
6
8
-
-
+
res.rsource n8 n7 = 1.3e-2, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -2e-3, tc2 = 1.05e-6
res.rvthres n22 n8 = 1, tc1 = -2.2e-3, tc2 = -8e-6
spe.ebreak n11 n7 n17 n18 = 32.08
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/110))** 6))
}
}
5
5
8
-
RSLC1
51
ISCL
50
RDRAIN
16
21
MSTRO
8
14
MMED
RSOURCE
8
DBREAK
11
MWEAK
EBREAK
RBREAK
17 18
IT
RVTHRES
+
-
17
18
7
RLSOURCE
RVTEMP
19
-
+
22
LDRAIN
RLDRAIN
DBODY
LSOURCE
VBAT
DRAIN
2
SOURCE
3
ISL9N322AP3/ISL9N322AS3ST
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
ISL9N322AP3/ISL9N322AS3ST
SPICE Thermal Model
REV 23 April 2001
ISL9N322AP3T
CTHERM1 th 6 1.3e-3
CTHERM2 6 5 1.5e-3
CTHERM3 5 4 1.6e-3
CTHERM4 4 3 1.7e-3
CTHERM5 3 2 5.8e-3
CTHERM6 2 tl 2e-2
RTHERM1 th 6 3.5e-3
RTHERM2 6 5 4.5e-3
RTHERM3 5 4 6.2e-2
RTHERM4 4 3 6.8e-1
RTHERM5 3 2 8.1e-1
RTHERM6 2 tl 8.3e-1
SABER Thermal Model
SABER thermal model ISL9N322AP3T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.3e-3
ctherm.ctherm2 6 5 = 1.5e-3
ctherm.ctherm3 5 4 = 1.6e-3
ctherm.ctherm4 4 3 = 1.7e-3
ctherm.ctherm5 3 2 = 5.8e-3
ctherm.ctherm6 2 tl = 2e-2
rtherm.rtherm1 th 6 = 3.5e-3
rtherm.rtherm2 6 5 = 4.5e-3
rtherm.rtherm3 5 4 = 6.2e-2
rtherm.rtherm4 4 3 = 6.8e-1
rtherm.rtherm5 3 2 = 8.1e-1
rtherm.rtherm6 2 tl = 8.3e-1
}
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
JUNCTION
th
CTHERM1
6
CTHERM2
5
CTHERM3
4
CTHERM4
3
CTHERM5
RTHERM6
2
CTHERM6
tl
CASE
©2002 Fairchild Semiconductor Corporation Rev. B, January 2002
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Rev. H4
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