Datasheet ISL9N312AD3ST, ISL9N312AD3 Datasheet (Fairchild Semiconductor)

June 2002

ISL9N312AD3 / ISL9N312AD3ST

N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs

ISL9N312AD3 / ISL9N312AD3ST

General Description

This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.

Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.

Applications

• DC/DC converters

Features

• Fast switching

•r

•r

•Q

•Q

•C

= 0.010Ω (Typ), VGS = 10V

DS(ON)

= 0.017Ω (Typ), VGS = 4.5V

DS(ON)

(Typ) = 13nC, VGS = 5V

g

(Typ) = 4.5nC

gd

(Typ) = 1450pF

ISS

D

D

G

S

D-PAK

TO-252

(TO-252)

MOSFET Maximum Ratings T

Symbol Parameter Ratings Units

V

DSS

V

GS

I

D

P

D

T

, T

J

STG

Drain to Source Voltage 30 V
Gate to Source Voltage ±20 V
Drain Current
Continuous (T
Continuous (T
Continuous (T
Pulsed Figure 4 A
Power dissipation

Derate above 25
Operating and Storage Temperature -55 to 175

= 25oC, VGS = 10V)

C

= 100oC, VGS = 4.5V) 32 A

C

= 25oC, VGS = 10V, R

C

o

C

G DS

= 25°C unless otherwise noted

A

= 52oC/W) 11 A

θJA

I-PAK

(TO-251AA)

G

S

50 A

75

0.5

W

W/oC

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

Thermal Resistance Junction to Case TO-251, TO-252 2
Thermal Resistance Junction to Ambient TO-251, TO-252 100
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 52

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

N312AD ISL9N312AD3ST TO-252AA 330mm 16mm 2500 units
N312AD ISL9N312AD3 TO-251AA Tube NA 50 units

©2002 Fairchild Semiconductor Corporation

ISL9N312AD3 / ISL9N312AD3ST Rev C

o

C/W

o

C/W

o

C/W

ISL9N312AD3 / ISL9N312AD3ST

Electrical Characteristics T

= 25°C unless otherwise noted

C

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V

V

= 25V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150

V

GS

o

- - 250

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA1-3V

I

= 50A, VGS = 10V - 0.010 0.012

Drain to Source On Resistance

D

= 32A, VGS = 4.5V - 0.017 0.020

I

D

Dynamic Characteristics

C
C
C
Q
Q
Q
Q
Q

ISS
OSS
RSS

g(TOT)
g(5)
g(TH)
gs
gd

Input Capacitance
Output Capacitance - 300 - pF
Reverse Transfer Capacitance - 120 - pF
Total Gate Charge at 10V VGS = 0V to 10V
Total Gate Charge at 5V VGS = 0V to 5V - 13 20 nC
Threshold Gate Charge VGS = 0V to 1V - 1.5 2.3 nC
Gate to Source Gate Charge - 4.3 - nC
Gate to Drain “Miller” Charge - 4.5 - nC

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 15 - ns
Rise Time - 60 - ns
Turn-Off Delay Time - 25 - ns
Fall Ti me - 30 - ns
Turn-Off Time - - 83 ns

(VGS = 4.5V)

= 15V, VGS = 0V,

V

DS

f = 1MHz

V

= 15V, ID = 11A

DD

V

= 4.5V, RGS = 11Ω

GS

V

DD

I

= 32A

D

= 1.0mA

I

g

= 15V

- 1450 - pF

-2538nC

- - 115 ns

µA

Ω

Switching Characteristics (V

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 8 - ns
Rise Time - 30 - ns
Turn-Off Delay Time - 45 - ns
Fall Ti me - 30 - ns
Turn-Off Time - - 115 ns

GS

= 10V)

Unclamped Inductive Switching

t

AV

Avalanche Time ID = 2.9A, L = 3.0mH 195 - - µs

Drain-Source Diode Characteristics

V

SD

t

rr

Q

RR

Source to Drain Diode Voltage
Reverse Recovery Time ISD = 32A, dISD/dt = 100A/µs- - 20 ns

Reverse Recovered Charge ISD = 32A, dISD/dt = 100A/µs- - 7 nC

- - 57 ns

= 15V, ID = 11A

V

DD

= 10V, RGS = 11Ω

V

GS

I

= 32A - - 1.25 V

SD

= 15A - - 1.0 V

I

SD

ISL9N312AD3 / ISL9N312AD3ST Rev C©2002 Fairchild Semiconductor Corporation

ISL9N312AD3 / ISL9N312AD3ST

Typical Characteristic T

= 25°C unless otherwise noted

C

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

-4

10

SINGLE PULSE

10

60

40

20

, DRAIN CURRENT (A)

D

I

0

150

25 50 75 100 125 150 175

Figure 2. Maximum Contin uous Drain Current vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

10

VGS = 10V

VGS = 4.5V

TC, CASE TEMPERATURE (oC)

Case Temperature

P

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

θJC

10

DM

1/t2

0

x R

θJC

t

+ T

1

t

2

C

1

10

, PEAK CURRENT (A)
I

DM

1000

100

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

30

-5

10

Figure 3. Normalized Maximum Transient Thermal Impedance

VGS = 10V

VGS = 5V

-4

10

-3

10

-2

10

10

t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

TC = 25oC
FOR TEMPERATURES

o

ABOVE 25
CURRENT AS FOLLOWS:

-1

I = I

25

C DERATE PEAK

175 - T

150

0

10

ISL9N312AD3 / ISL9N312AD3ST Rev C©2002 Fairchild Semiconductor Corporation

C

1

10

ISL9N312AD3 / ISL9N312AD3ST

Typical Characteristic (Continued) T

100

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 15V

V

DD

75

50

, DRAIN CURRENT (A)

25

D

I

0

123456

VGS, GATE TO SOURCE VOLTAGE (V)

Figure 5. Transfer Ch aracteri stics Figure 6. Saturation Character istics

25

ID = 14A

20

15

ID = 32A
ID = 50A

TJ = -55oC

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TJ = 175oC

TJ = 25oC

= 25°C unless otherwise noted

C

100

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 25oC

T

C

75

50

, DRAIN CURRENT (A)

25

D

I

0

0 0.5 1.0 1.5 2.0

2.0

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.5

V

= 10V

GS

= 4.5V

V

GS

= 4V

V

GS

VGS = 3V

VDS, DRAIN TO SOURCE VOLTAGE (V)

, DRAIN TO SOURCE

10

ON RESISTANCE (mΩ)

DS(ON)

r

5

246810

, GATE TO SOURCE VOLTAGE (V)

V

GS

Figure 7. Drain to Source On Resis tanc e vs Ga te

Voltage and Drain Current

1.2

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 0 40 80 120 160 200-40

TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

Figure 9. Normalized Gate Thres hold Volta ge v s

Junction Temperature

1.0

ON RESISTANCE

NORMALIZED DRAIN TO SOURCE

0.5

-80

-40

-40

TJ, JUNCTION TEMPERATURE (oC)

0

40 80

VGS = 10V, ID = 50A

120 160 200

Figure 8. Normalized Drain to Source On

Resistance vs Junction Temperature

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200

T

, JUNCTION TEMPERATURE (oC)

J

Figure 10. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

ISL9N312AD3 / ISL9N312AD3ST Rev C©2002 Fairchild Semiconductor Corporation

ISL9N312AD3 / ISL9N312AD3ST

Typical Characteristic (Continued) T

2000

C

= CGS + C

ISS

1000

C

≅ C

OSS

C

= C

RSS

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

100

0.1 1 10

Figure 11. Capacitance vs Drain to Source

200

VGS = 4.5V, VDD = 15V, ID = 11A

150

GD

+ C

DS

GD

GD

VDS, DRAIN TO SOURCE VOLTAGE (V)

Voltage

= 25°C unless otherwise noted

C

10

V

= 15V

DD

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

30

0

0102030

Figure 12. Gate Charge Waveforms for Constant

200

VGS = 10V, VDD = 15V, ID = 11A

t

r

150

WAVEFORMS IN
DESCENDING ORDER:

Qg, GATE CHARGE (nC)

Gate Currents

I

= 32A

D

ID = 14A

t

d(OFF)

100

t

f

t

50

SWITCHING TIME (ns)

0

0

10 20 30 40 50

d(OFF)

t

d(ON)

RGS, GATE TO SOURCE RESISTANCE (Ω)

100

50

SWITCHING TIME (ns)

0

0 1020304050

t

f

RGS, GATE TO SOURCE RESISTANCE (Ω)

Figure 13. Switching Time vs Gate Resistance Figure 14. Switching Time vs Gate Resistance

Test Circuits and Waveforms

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

V

DS

L

I

AS

R

AS

G

+

V

DD

-

DUT

I

AS

0

0.01Ω

BV

DSS

t

P

t

AV

V

DS

t

d(ON)

V

t

r

DD

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

ISL9N312AD3 / ISL9N312AD3ST Rev C©2002 Fairchild Semiconductor Corporation

Test Circuits and Waveforms (Continued)

V

DS

R

L

V

GS

+

V

DD

-

DUT

I

g(REF)

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

DD

V

0

I

g(REF)

0

GS

V

GS

= 1V

Q

g(TOT)

V

DS

Q

g(5)

Q

g(TH)

Q

gs

Q

gd

VGS = 5V

ISL9N312AD3 / ISL9N312AD3ST

V

= 10V

GS

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

ISL9N312AD3 / ISL9N312AD3ST Rev C©2002 Fairchild Semiconductor Corporation

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and thermal resistance R

A

is never exceeded.

JM

DM

θJA

, in an

(oC/W)

serves as the basis for establishing the rating of the part.

P

DM

TJMTA–()

------------------- ----------=

Z

θJA

(EQ. 1)

C/W)

o

(

θJA

R

125

100

ISL9N312AD3 / ISL9N312AD3ST

R

= 33.32 + 23.84/(0.268+Area)

θJA

75

50

In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
complex and influenced by many factors:

DM

is

1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.

25

0.01 0.1 1 10
AREA, TOP COPPER AREA (in2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

Displayed on the curve are R
Electrical Specifications table. The points were chosen to

values listed in the

θJA

depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P

.

DM

Thermal resistances corresponding to other copper area s
can be obtained from Figure 21 or by calculation using
Equation 2. R
times a coefficient added to a constant. The area, in square

is defined as the natural log of the area

θJA

inches is the top copper area including the gate and source
pads.

R

θJA

=

33.32

23.84

-------------------------------------+

0.268 Area+()

(EQ. 2)

ISL9N312AD3 / ISL9N312AD3ST Rev C©2002 Fairchild Semiconductor Corporation

PSPICE Electrical Model

.SUBCKT ISL9N312AD3ST 2 1 3 ; rev May 2001

CA 12 8 9e-10
CB 15 14 9e-10
CIN 6 8 1.35e-9

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 31.6
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 1e-9

LGATE 1 9 5.61e-9
LSOURCE 3 7 1.98e-9

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTRO M OD
MWEAK 16 21 8 8 MWEA KM O D

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2e-3
RGATE 9 20 1.76
RLDRAIN 2 5 10
RLGATE 1 9 56.1
RLSOURCE 3 7 19.8
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.8e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

-

ESG

+

EVTEMP

+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

6
8

13

10

RSLC2

6

14
13

+

+

6
8

-

-

DPLCAP

EVTHRES
+

19

S2A

S2B

ISL9N312AD3 / ISL9N312AD3ST

+

17
18

-

RLDRAIN

DBODY

LSOURCE

7

RLSOURCE

RVTEMP
19

­VBAT

+

22

LDRAIN

5

RSLC1

51

+

5

ESLC

51

­50

RDRAIN

16

21

-

8

MSTRO

CIN

15

CB

14

+

5
8

-

8

MMED

DBREAK

11

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

DRAIN

2

SOURCE

3

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*160),5))}
.MODEL DBODYMOD D (IS = 1.1e-11 N = 1.075 RS = 7.2e-3 TRS1 = 5e-4 TRS2 = 1e-6 CJO = 6.9e-10 TT = 8e-11 M = 0.49)

.MODEL DBREAKMOD D (RS = 0.95 TRS1 = 1e-3 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 5e-10 IS = 1e-30 N = 10 M = 0.46)
.MODEL MMEDMOD NMOS (VTO = 1.99 KP = 6 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.76)
.MODEL MSTROMOD NMOS (VTO = 2.35 KP = 55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.62 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 17.6 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.1e-3 TC2 = -2e-6)
.MODEL RDRAINMOD RES (TC1 = 1.6e-2 TC2 = 1e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 2.5e-5)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.1e-3 TC2 = -1e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.8e-3 TC2 = 1e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF= -3)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.3 VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.3)

.ENDS
NOTE: For further discussi on of the PSPI CE model, cons ult A New PSPICE Sub-Circuit f or the Po wer MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 199 1, written by William J. Hepp and C. Frank
Wheatley.

ISL9N312AD3 / ISL9N312AD3ST Rev C©2002 Fairchild Semiconductor Corporation

SABER Electrical Model

REV May 2001
template ISL9N312AD3ST n2,n1,n3

electrical n2,n1, n3
{
var i iscl
dp..model dbodym od = (isl = 1.1e-11, nl = 1.075, rs = 7.2e-3, trs1 = 5e-4, trs2 = 1e-6, cjo = 6.9e-10 , m=0.49, tt = 8e-11)
dp..model dbreak mod = (rs = 0.95, trs1 = 1e-3, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 5e-10, isl=10e-30, nl=10, m=0.46)
m..model mmedmod = (type=_n, vto = 1.99, kp=6, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.35, kp = 55, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.62, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -3, voff = -1)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1, voff = -3)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3)

c.ca n12 n8 = 9e-10

10

c.cb n15 n14 = 9e-10
c.cin n6 n8 = 1.35e-9

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9

l.lgate n1 n9 = 5.61e-9
l.lsource n3 n7 = 1.98e-9

GATE

1

LGATE

RLGATE

RGATE

9

ESG

EVTEMP

+

18
22

20

­6

8

+

-

m.mmed n16 n6 n8 n8 = model=mmedm od, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model= mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1 = 1.1e-3, tc2 = -2e-6
res.rdrain n50 n16 = 2e-3, tc1 = 1.6e-2, tc2 = 1e-5
res.rgate n9 n20 = 1.7 6
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 56.1
res.rlsource n3 n7 = 19.8
res.rslc1 n5 n51 = 1e - 6, tc 1 = 1e -3 , tc 2 = 2.5e-5
res.rslc2 n5 n50 = 1e3

12

CA

S1A

13

8

S1B

13

+

+

EGS EDS

res.rsource n8 n7 = 6. 8e-3, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -2.1e-3, tc2 = -1e-5

spe.ebreak n11 n7 n17 n18 = 31.6
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

RSLC2

6

S2A

14
13

S2B

6
8

-

-

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

5
8

-

5

RSLC1

51

50
RDRAIN

21

MSTRO

14

ISCL

16

8

MMED

DBREAK

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

17
18

-

RLDRAIN

7

RLSOURCE

RVTEMP
19

-

+

22

LDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

ISL9N312AD3 / ISL9N312AD3ST

equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n 5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/160))** 5))
}
}

ISL9N312AD3 / ISL9N312AD3ST Rev C©2002 Fairchild Semiconductor Corporation

ISL9N312AD3 / ISL9N312AD3ST

SPICE Thermal Model

REV 23 May 2001

ISL9N312T

CTHERM1 th 6 1e-3
CTHERM2 6 5 1.5e-3
CTHERM3 5 4 1.9e-3
CTHERM4 4 3 3e-3
CTHERM5 3 2 8.5e-3
CTHERM6 2 tl 3.5e-2

RTHERM1 th 2.2e-3
RTHERM2 6 3e-3
RTHERM3 5 4 5e-2
RTHERM4 4 3 4.8e-1
RTHERM5 3 2 5e-1
RTHERM6 2 tl 6e-1

SABER Thermal Model

SABER thermal model ISL9N3 12T
template thermal_model th tl

thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1e-3
ctherm.ctherm2 6 5 = 1.5e-3
ctherm.ctherm3 5 4 = 1.9e-3
ctherm.ctherm4 4 3 = 3e-3
ctherm.ctherm5 3 2 = 8.5e-3
ctherm.ctherm6 2 tl = 3.5e-2

rtherm.rtherm1 th 6 = 2.2e-3
rtherm.rtherm2 6 5 = 3e-3
rtherm.rtherm3 5 4 = 5e-2
rtherm.rtherm4 4 3 = 4.8e-1
rtherm.rtherm5 3 2 = 5e-1
rtherm.rtherm6 2 tl = 6e-1
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

RTHERM6

CTHERM6

tl

CASE

ISL9N312AD3 / ISL9N312AD3ST Rev C©2002 Fairchild Semiconductor Corporation

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Advance Information Formative or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

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Rev. H7