Datasheet ISL95810 Datasheet (intersil)

®

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ISL95810

Single Digitally Controlled Potentiometer (XDCP™)

Data Sheet September 19, 2006

Low Noise, Low Power I2C Bus, 256 Taps

The ISL95810 integrates a digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the I

2

C
bus interface. The potentiometer has an associated volatile
Wiper Register (WR) and a non-volatile Initial Value Register
(IVR), that can be directly written to and re ad by th e use r.
The content of the WR controls the position of the wiper. At
power-up the device recalls the contents of the DCP’s IVR to
the WR.

The DCP can be used as three-terminal potentiometer or as
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.

Ordering Information

PART

PART NUMBER

ISL95810WIU8* AIU 10 -40 to +85 8 Ld MSOP
ISL95810WIU8Z

(Note)
ISL95810WIRT8Z*

(Note)
ISL95810UIU8* AIT 50 -40 to +85 8 Ld MSOP
ISL95810UIU8Z*

(Note)
ISL95810UIRT8 AIT -40 to +85 8 Ld 3 x 3 TDFN
ISL95810UIRT8Z*

(Note)

*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.

MARKING

APN -40 to +85 8 Ld MSOP

APO -40 to +85 8 Ld 3 x 3 TDFN

AOK -40 to +85 8 Ld MSOP

APP -40 to +85 8 Ld 3 x 3 TDFN

R

TOTAL

(kΩ)

TEMP

RANGE (°C) PACKAGE

(Pb-free)

(Pb-free)

(Pb-free)

(Pb-free)

FN8090.2

Features

• 256 resistor taps - 0.4% resoluti o n

2

•I

C serial interface

• Wiper resistance: 70Ω typical @ 3.3V

• Non-volatile storage of wiper position

• Standby current 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ, 10kΩ total resistance

• High reliability

- Endurance: 200,000 data changes per bit per register

- Register data retention: 50 years @ T ≤ +75°C

• 8 Ld MSOP and 8 Ld TDFN packaging

• Pb-free plus anneal available (RoHS compliant)

Pinouts

ISL95810

(8 LD MSOP)

TOP VIEW

WP

SCL

SDA

GND

SCL
SDA

GND RW

WP

1
2
3
4

ISL95810

(8 LD TDFN)

TOP VIEW

1
2
3
4

8

V

CC

7

RH

6

RL
RW

5

V

8

CC

7

RH

6

RL

5

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
XDCP is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

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ISL95810

VCC

RH

SDA

SCL

WP

I2C AND

CONTROL

WIPER

REGISTER

NON-VOLATILE

REGISTER

GND

Pin Descriptions

TSSOP PIN SYMBOL DESCRIPTION

1WPHardware write protection. Active low. Prevents any “Write” operation of the I2C interface.

2

2SCLI
3 SDA Serial data I/O for the I
4 GND Ground
5 RW “Wiper” terminal of the DCP
6 RL “Low” terminal of the DCP
7 RH “High” terminal of the DCP
8V

CC

C interface clock

Power supply

2

C interface

RW

RL

2

FN8090.2

September 19, 2006

ISL95810

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at Any Digital Interface Pin

with Respect to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at Any DCP Pin with

Respect to V

. . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3

SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

SS

CC

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

W

C

H/CL/CW

I

LkgDCP

VOLTAGE DIVIDER MODE (0V @ RL; V

(Note 6) Integral Non-Linearity -1 1 LSB (Note 2)

INL

DNL

(Note 5) Differential Non-Linearity Monotonic over all tap positions W option -0.75 -0.75 LSB (Note 2)

RH to RL Resistance W, U versions respectively 10, 50 kΩ

to RL Resistance Tolerance -20 +20 %

R

H

Wiper Resistance VCC = 3.3V @ +25°C

Wiper current = V

Potentiometer Capacitance
(Note 13)

Leakage on DCP Pins (Note 13) Voltage at pin from GND to V

@ RH; measured at RW, unloaded)

CC

ZSerror (Note 3) Zero-Scale Error W option 0 1 7 LSB

U option 0 0.5 2

FSerror

(Note 4) Full-Scale Error W option -7 -1 0 LSB (Note 2)

U option -2 -0.5 0

TC

(Note 7, 13) Ratiometric Temperature

V

Coefficient

DCP Register set to 80 hex ±4 ppm/°C

RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)

(Note 11) Integral Non-Linearity DCP register set between 20 hex and FF hex.

RINL

Monotonic over all tap positions

(Note 5) Differential Non-Linearity DCP register set between 20 hex

RDNL

and FF hex. Monotonic over all tap
positions

Roffset

(Note 9) Offset W option 0 1 7 MI (Note 8)

U option 0 0.5 2 MI

TC

R

(Note 12, 13)

Resistance Temperature Coefficient DCP register set between 20 hex and FF hex ±45 ppm/°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

TYP

(Note 1) MAX UNIT

70 200 Ω

CC/RTOTAL

10/10/25 pF

CC

0.1 1 µA

U option -0.5 -0.5 LSB

-1 1 MI (Note 8)

W option -0.75 -0.75 MI (Note 8)
U option -0.5 -0.5 MI

(Note 2)
(Note 2)

(Note 8)

(Note 8)

Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

I

(Note 15) VCC Supply Current

CC1

(Note 15) VCC Supply Current

I

CC2

(Note 15) VCC Current (Standby) V

I

SB

(Volatile write/read)

(Nonvolatile Write)

f

= 400kHz; SDA = Open; (for I2C, Active,

SCL

Read and Volatile Write States only)
f

= 400kHz; SDA = Open; (for I2C, Active,

SCL

Nonvolatile Write State only)

= +5.5V, I2C Interface in Standby State 5 µA

CC

= +3.6V, I2C Interface in Standby State 2 µA

V

CC

3

TYP

(Note 1) MAX UNITS

1mA

3mA

FN8090.2

September 19, 2006

ISL95810

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

I

LkgDig

(Note 13) DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to

t

DCP

Leakage Current, at Pins SDA, SCL,

Pins

and WP

Vpor Power-On Recall Voltage Minimum V

V

Ramp VCC Ramp Rate 0.2 V/ms

CC

(Note 13) Power-Up Delay VCC above Vpor, to DCP Initial Value Register recall

t

D

Voltage at pin from GND to V

wiper change

at which memory recall occurs 1.8 2.6 V

CC

2

completed, and I

C Interface in standby state

CC

EEPROM SPECIFICATIONS

EEPROM Endurance 200,000 Cycles
EEPROM Retention Temperature ≤ +75°C 50 Years

SERIAL INTERFACE SPECIFICATIONS

V

IL

V

IH

Hysteresis

(Note 13) SDA and SCL Input Buffer Hysteresis 0.05*V

V

(Note 13) SDA Output Buffer LOW Voltage,

OL

WP, SDA, and SCL Input Buffer LOW
Voltage

WP, SDA, and SCL Input Buffer
HIGH Voltage

0.7*V

Sinking 4mA

(Note 13) WP, SDA, and SCL Pin Capacitance 10 pF

Cpin

f

SCL

t

(Note 13) Pulse Width Suppression Time at

IN

(Note 13) SCL Falling Edge to SDA Output

t

AA

(Note 13) Time the Bus Must be Free Before

t

BUF

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STO

t

HD:STO:NV

(Note 13) Output Data Hold Time From SCL falling edge crossing 30% of VCC, until

t

DH

(Note 13) SDA and SCL Rise Time From 30% to 70% of V

t

R

SCL Frequency 400 kHz

Any pulse narrower than the max spec is

SDA and SCL Inputs

suppressed.
SCL falling edge crossing 30% of VCC, until SDA

Data Valid

exits the 30% to 70% of V

window.

CC

SDA crossing 70% of VCC during a STOP

the Start of a New Transmission

condition, to SDA crossing 70% of V
following START condition.

during the

CC

Clock LOW Time Measured at the 30% of VCC crossing. 1300 ns
Clock HIGH Time Measured at the 70% of VCC crossing. 600 ns
START Condition Setup Time SCL rising edge to SDA falling edge. Both

crossing 70% of V

CC

.

START Condition Hold Time From SDA falling edge crossing 30% of VCC to

SCL falling edge crossing 70% of V

CC

.

Input Data Setup Time From SDA exiting the 30% to 70% of VCC

window, to SCL rising edge crossing 30% of V

CC

Input Data Hold Time From SCL rising edge crossing 70% of VCC to

SDA entering the 30% to 70% of V

window.

CC

STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to

CC

window.

CC

.

STOP Condition Hold Time for Read,
or Volatile Only Write

STOP Condition Hold Time for Non­Volatile Write

SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge. Both

crossing 70% of V

CC

.

From SDA rising edge to SCL falling edge. Both
crossing 70% of V

CC

.

SDA enters the 30% to 70% of V

CC

0.1 * Cb

(Note 13) SDA and SCL Fall Time From 70% to 30% of V

t

F

CC

0.1 * Cb

(Note 13) Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF

Cb

(Note 1) MAX UNITS

-10 10 µA

-0.3 0.3*V

CC

CC

00.4V

1300 ns

600 ns

600 ns

100 ns

0ns

600 ns

600 ns

2µs

0ns

20 +

20 +

1µs

3ms

CC

VCC+0.3 V

50 ns

900 ns

250 ns

250 ns

V

V

4

FN8090.2

September 19, 2006

ISL95810

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

Rpu (Note 13) SDA and SCL Bus Pull-Up Resistor

Off-Chip

Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ

(Notes 13, 14) Non-Volatile Write Cycle Time 12 20 ms

t

WP

t

SU:WP

t

HD:WP

WP Setup Time Before START condition 600 ns
WP Hold Time After STOP condition 600 ns

SDA vs SCL Timing

t

F

t

HIGH

t

LOW

t

R

(Note 1) MAX UNITS

1kΩ

t

SU:WP

t

SU:DAT

CLK 1

t

HD:DAT

t

HD:WP

t

AA

STOP

t

SU:STO

t

DH

t
t

HD:STO
HD:STO:NV

t

BUF

(INPUT TIMING)

(OUTPUT TIMING)

WP

Pin Timing

SCL

SDA

SDA

SDA IN

t

SU:STA

SCL

WP

t

HD:STA

START

NOTES:

1. Typical values are for T

2. LSB: [V(RW)
incremental voltage when changing from one tap to an adjacent tap.

255

3. ZS error = V(RW)

4. FS error = [V(RW)

5. DNL = [V(RW)

6. INL = [V(RW)

7. for i = 16 to 240 decimal, T = -40°C to +85°C. Max( ) is the maximum value of the wiper

TC

V

|R

8. MI =
Roffset = R

9. Roffset = R

10. RDNL = (R

11. RINL = [R

12. for i = 32 to 255, T = -40°C to +85°C. Max( ) is the maximum value of the resistance and Min ( ) is the

TC

R

– V(RW)

i

– (i • LSB – V(RW)0)]/LSB for i = 1 to 255.

i

Max V RW()

()Min V RW()

----------------------------------------------------------------------------------------------

()Min V RW()

Max V RW()

– R

255

0

/MI, when measuring between RW and RL.

0

/MI, when measuring between RW and RH.

255

– R

i

i-1

– (MI • i) – R0]/MI, for i = 32 to 255.

i

Max Ri()Min Ri()–[]

--------------------------------------------------------------- -

Max Ri()Min Ri()+[]2⁄

= +25°C and 3.3V supply voltage.

A

– V(RW)0]/255. V(RW)

/LSB.

0

– VCC]/LSB.

255

]/LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

i

()+[]2⁄

i

|/255. R

and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.

255

255

()–

i

)/MI, for i = 32 to 255.

6

10

---------------- -

×=

125°C

and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the

6

10

i

---------------- -

×=

125°C

voltage and Min ( ) is the m inimu m va lue of th e wip er vo lt age ov er t he te mper atur e ra nge.

minimum value of the resistance over the temperature range.

13. This parameter is not 100% tested.
is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a

14. t

WC

valid STOP condition at the end of a Write sequence of a I

2

C serial interface Write operation, to the end of the self-timed internal non-volatile

write cycle.

= 0V, VIH = V

15. V

IL

CC

5

FN8090.2

September 19, 2006

Typical Performance Curves

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ISL95810

160

140

VCC = 2.7, T = -40°C

120

100

80

60

40

WIPER RESISTANCE (Ω)

20

VCC = 5.5, T = -40°C

0

0 50 100 150 200 250

TAP POSITION (DECIMAL)

VCC = 2.7, T = 85°C

VCC = 2.7, T = 25°C

VCC = 5.5, T = 85°C

VCC = 5.5, T = 25°C

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

[ I(RW) = V

0.2

0.15

0.05

-0.05

DNL (LSB)

-0.15

0.1

-0.1

-0.2

VCC = 2.7, T = 25°C

0

VCC = 2.7, T = 85°C

0 50 100 150 200 250

/ R

CC

VCC = 5.5, T = -40°C

VCC = 5.5, T = 25°C

TAP POSITION (DECIMAL)

TOTAL

] for 50kΩ (U)

VCC = 5.5, T = 85°C

VCC = 2.7, T = -40°C

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

1.8

1.6

1.4

1.2

(µA)

1.0

CC

0.8

0.6

STANDBY I

0.4

0.2

0.0

2.7 3.2 3.7 4.2 4.7 5.2

FIGURE 2. STANDBY I

0.3

VCC = 5.5, T = -40°C

0.2

0.1

0

INL (LSB)

-0.1

-0.2

-0.3

= 2.7, T = 85°C

V

CC

0 50 100 150 200 250

-40°C

25°C

V

(V)

CC

CC

V

= 2.7, T = -40°C

CC

= 2.7, T = 25°C

V

CC

TAP POSITION (DECIMAL)

85°C

vs V

CC

VCC = 5.5, T = 85°C

V

= 5.5, T = 25°C

CC

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

FSerror (LSB)

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

0

-1

-40

FIGURE 6. FSerror vs TEMPERATURE

0.4

0.35

0.3

0.25

ZSerror (LSB)

0.2

0.15

-40-200 20406080

2.7V

5.5V

TEMPERATURE (°C)

FIGURE 5. ZSerror vs TEMPERATURE

6

-20

= 5.5V

V

CC

VCC = 2.7V

0

20 40 60 80

TEMPERATURE (°C)

FN8090.2

September 19, 2006

Typical Performance Curves (Continued)

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ISL95810

0.3

V

= 2.7, T = 25°C

= 5.5, T = 25°C

V

0.2

0.1

0

DNL (LSB)

-0.1

-0.2

-0.3
32 82 132 182 232

CC

= 5.5, T = 85°C

V

CC

VCC = 2.7, T = -40°C

TAP POSITION (DECIMAL)

CC

VCC = 2.7, T = 85°C

= 5.5, T = -40°C

V

CC

FIGURE 7. DNL vs TAP POSITION IN RHEOST A T MODE FOR

50kΩ (U)

1.50

1.00

0.50

CHANGE (%)

0.00

TOTAL

-0.50

-1.00

5.5V

2.7V

0.5

0.4

0.3

0.2

0.1

0

-0.1

INL (LSB)

-0.2

-0.3

= 2.7, T = 85°C

V

-0.4

CC

-0.5
32 82 132 182 232

V

= 5.5, T = 25°C

CC

TAP POSITION (DECIMAL)

VCC = 5.5, T = -40°C

VCC = 5.5, T = 85°C

= 2.7, T = 25°C

V

CC

VCC = 2.7, T = -40°C

FIGURE 8. INL vs TAP POSITION IN RHEOST AT MODE FOR

50kΩ (U)

20

10

0

TC (ppm/°C)

-10

END TO END R

-1.50

-40-200 20406080

TEMPERATURE (°C)

FIGURE 9. END TO END R

% CHANGE vs

TOTAL

TEMPERATURE

35

25

15

5

TC (ppm/°C)

-5

-15

-25
32 57 82 107 132 157 182 207 232

TAP POSITION (DECIMAL)

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm

-20

32 82 132 182 232

TAP POSITION (DECIMAL)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

INPUT

OUTPUT

Tap Position = Mid Point

= 9.4K

R

TOTAL

FIGURE 12. FREQUENCY RESPONSE (2.2MHz)

7

FN8090.2

September 19, 2006

Typical Performance Curves (Continued)

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ISL95810

Signal at Wiper (Wiper Unloaded)

Wiper Movement Mid Point
From 80h to 7fh

FIGURE 13. MIDSCALE GLITCH, CODE 80h to 7Fh (WIPER 0)

Principles of Operation

The ISL95810 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory, and a I
serial interface providing direct communication between a
host and the potentiometer and memory.

DCP Description

The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). The DCP has its own WR.
When the WR of the DCP contains all zeroes (WR<7:0>:
00h), its wiper terminal (RW) is closest to its “Low” terminal
(RL). When the WR of the DCP contains all ones (WR<7:0>:
FFh), its wiper terminal (RW) is closest to its “High” terminal
(RH). As the value of the WR increases from all zeroes (00h)
to all ones (255 decimal), the wiper moves monotonically
from the position closest to RL to the closest to RH. At the
same time, the resistance between RW and RL increases
monotonically, while the resistance between RH and RW
decreases monotonically.

While the ISL95810 is being powered up, The WR is reset to
80h (128 decimal), which locates RW roughly at the center
between RL and RH. Soon after the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the ISL95810 reads the value stored in non-volatile
Initial Value Registers (IVRs) and loads it into the WR.

The WR and IVR can be read or written directly using the

2

I

C serial interface as described in the following sections.

2

C

SCL

Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)

FIGURE 14. LARGE SIGNAL SETTLING TIME

Memory Description

The ISL95810 volatile and non-volatile registers are
accessed by I
decimal. The non-volatile byte at addresses 0 contains the
initial value loaded at power-up into the volatile Wiper
Register (WR) of the DCP. The byte at address 1 is
reserved; the user should not write to it, and its value should
be ignored if read.

The volatile WR, and the non-volatile Initial Value Register
(IVR) of the DCP are accessed with the same Address Byte,
set to 00 hex in both cases.

A volatile byte at address 2 decimal, controls what byte is
read or written when accessing DCP registers: the WR, the
IVR, or both.

When the byte at address 2 is all zeroes, which is the default
at power-up:

• A read operation to addresses 0 outputs the value of the
non-volatile IVR.

• A write operation to addresses 0 writes the same value to
the WR and IVR of the corresponding DCP.

When the byte at address 2 is 80h (128 decimal):

• A read operation to addresses 0 outputs the value of the
volatile WR.

• A write operation to addresses 0 only writes to the
corresponding volatile WR.

It is not possible to write to an IVR without writing the same
value to its corresponding WR.

00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be
written to address 2.

2

C interface operations at addresses 0 and 2

8

FN8090.2

September 19, 2006

ISL95810

www.BDTIC.com/Intersil

The ISL95810 is pre-programed with 80h in the IVR.

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

2-Access Control
1 Reserved
0IVR WR

WR: Wiper Register, IVR: Initial value Register.

I2C Serial Interface

The ISL95810 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL95810
operates as a slave device in all applications.

All communication over the I
sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power-up of the ISL95810 the SDA pin is in
the input mode.

2

All I

C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL95810 continuously monitors the SDA
and SCL lines for the START condition and does not

2

C interface is conducted by

respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the power­up sequence and during internal non-volatile write cycles.

2

All I

C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15). A STOP condition at the end
of a read operation, or at the end of a write operation to
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte, initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.

An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).

The ISL95810 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL95810 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.

A valid Identification Byte contains 0101000 as the seven
MSBs. The LSB in the Read/Write
Read operation, and “0” for a Write operation (See Table 2).

TABLE 2. IDENTIFICATION BYTE FORMAT

0 101000R/W

(MSB) (LSB)

bit. Its value is “1” for a

SCL

SDA

START DATA DATA STOP

FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS

9

STABLE CHANGE

DATA

STABLE

FN8090.2

September 19, 2006

SCL FROM

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MASTER

ISL95810

81 9

SDA OUTPUT FROM

SDA OUTPUT FROM

SIGNALS

FROM THE

MASTER

TRANSMITTER

RECEIVER

SIGNALS FROM

SIGNAL AT SDA

SIGNALS FROM

S
T
A

IDENTIFICATION

R

BYTE WITH

T

HIGH IMPEDANCE

START ACK

FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER

WRITE

S

THE MASTER

THE ISL95810

T
A

IDENTIFICATION

R
T

BYTE

00011

ADDRESS

BYTE

00000000000

A
C
K

A
C
K

FIGURE 17. BYTE WRITE SEQUENCE

S
T
A

IDENTIFICATION
R
T

BYTE WITH

R/W

=1

R/W

ADDRESS

=0

BYTE

DATA
BYTE

A
C
K

HIGH IMPEDANCE

S
T
O
P

A
C
K

A
C
K

S
T
O
P

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

00011

000 0000 00

A
C
K

A
C
K

FIGURE 18. READ SEQUENCE

Write Operation

A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL95810 responds with an ACK. At this time, if the Data
Byte is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the ISL95810 begins its internal
write cycle to non-volatile memory. During the internal non­volatile write cycle, the device ignores transitions at the SDA
and SCL pins, and the SDA output is at a high impedance
state. When the internal non-volatile write cycle is
completed, the ISL95810 enters its standby state (See
Figure 17).

01011

000

The byte at address 02h determines if the Data Byte is to be
written to volatile and/or non-volatile memory (See “Memory
Description” on page 8).

Data Protection

The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP
device ignores Data Bytes of a Write Operation, does not
respond to the Data Bytes with an ACK, and instead, goes to
its standby state waiting for a new START condition.

A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is

A
C
K

FIRST READ

DATA BYTE

LAST READ
DATA BYTE

is active (LOW) the

10

FN8090.2

September 19, 2006

received. If the Address Byte is 0 or 2, the Data Byte is

www.BDTIC.com/Intersil

transferred to the Wiper Register (WR) or to the Access
Control Register respectively, at the falling edge of the SCL
pulse that loads the last bit (LSB) of the Data Byte. If the
Address Byte is 0, and the Access Control Register is all
zeros (default), then the STOP condition initiates the internal
write cycle to non-volatile memory.

Read Operation

A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W
Address Byte, a second START, and a second Identification
byte with the R/W
the ISL95810 responds with an ACK. Then the ISL95810
then transmits the Data Byte. The master then terminates
the read operation (issuing a STOP condition) following the
last bit of the Data Byte (See Figure 18).

The byte at address 02h determines if the Data Bytes being
read are from volatile or non-volatile memory (See “Memory
Description” on page 8.)

bit set to “1”. After each of the three bytes,

bit set to “0”, an

ISL95810

11

FN8090.2

September 19, 2006

ISL95810

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Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only.

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

C

4X θ

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

05

α

o

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 2 01/03

NOTESMIN MAX MIN MAX

-

-

12

FN8090.2

September 19, 2006

ISL95810

www.BDTIC.com/Intersil

Thin Dual Flat No-Lead Plastic Package (TDFN)

(DATUM B)

6

INDEX

AREA

(DATUM A)

NX (b)

5

6

INDEX
AREA

SEATING

PLANE

NX L

8

A

C

(A1)

D

TOP VIEW

SIDE VIEW

D2

12

N

N-1

e

(Nd-1)Xe

REF .

BOTTOM VIEW

D2/2

C

2X

L

A3

E2/2

NX b

5

87

0.10

E

A

NX k

E2

2X

ABC0.15

0.15

//

L

0.10

0.08

CB

BAMC

L8.3x3B

8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A 0.70 0.75 0.80 ­A1 - - 0.05 ­A3 0.20 REF -

b 0.23 0.30 0.38 5, 8

D 3.00 BSC -

D2 2.15 2.30 2.40 7, 8

E 3.00 BSC -

C

E2 1.35 1.50 1.60 7, 8

e 0.65 BSC -

C

k0.20 - - -

L 0.20 0.30 0.40 8

N82

Nd 4 3

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

NOTESMIN NOMINAL MAX

Rev. 0 6/04

SECTION "C-C"

FOR EVEN TERMINAL/SIDE

CC

e

TERMINAL TIP

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or it s sub s idiari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

13

FN8090.2

September 19, 2006