Datasheet ISL90843 Datasheet (intersil)

®

www.BDTIC.com/Intersil

ISL90843

Quad Digital Controlled Potentiometers (XDCP™)

Data Sheet March 29, 2006

Low Noise, Low Power, I2C® Bus,
256 Taps

The ISL90843 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. Each potentiometer has an associated
Wiper Register (WR) that can be directly written to and read
by the user. The contents of the WR controls the position of
the wiper.

The DCPs can be used as a voltage divider in a wide variety
of applications including control, AC measurement, and
signal processing.

Pinout

ISL90843

(10 LD MSOP)

TOP VIEW

FN8095.2

Features

• Four potentiometers in one package

• 256 resistor taps–0.4% resolution

•I2C serial interface

- Two address pins allow up to four devices/bus

• Wiper resistance: 70Ω typical @ 3.3V

• Standby current <5µA max

• Power supply: 2.7V to 5.5V

•10kΩ or 50kΩ total resistance

• 10 Ld MSOP package

• Pb-free plus anneal product (RoHS compliant)

RW3

SCL

SDA

GND

RW2

1
2

3
4

5

RW0

10

V

9

CC

A1

8

A0

7

RW1

6

Ordering Information

PART NUMBER

(Note) PART MARKING

ISL90843WIU1027Z* DET 10 -40 to +85 10 Ld MSOP

ISL90843UIU1027Z* DES 50 -40 to +85 10 Ld MSOP

*Add "-TK" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

RESISTANCE OPTION

(kΩ)

TEMP RANGE

(°C)

PACKAGE

(Pb-Free)

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Functional Diagram

www.BDTIC.com/Intersil

ISL90843

V

CC

Block Diagram

SDA

SCL

SCL

SDA

A0

A1

2

C

I

INTERFACE

I2C

INTERFACE

GND R

POWER-UP,

INTERFACE,
CONTROL AND
STATUS LOGIC

R

H

R

L

W0

R

H

R

L

R

W1

V

CC

WR3

WR2

WR1

R

H

R

L

R

W2

DCP3

DCP2

DCP1

R

H

R

L

R

W3

R

W3

R

W2

R

W1

A1

A0

GND

WR0

Pin Descriptions

MSOP PIN SYMBOL DESCRIPTION

1 RW3 “Wiper” terminal of DCP3

2

2SCLI

3 SDA Serial data I/O for the I

4 GND Device ground pin

5 RW2 “Wiper” terminal of DCP2

6 RW1 “Wiper” terminal of DCP1

7 A0 Device address for the I

8 A1 Device address for the I

9V

CC

10 RW0 “Wiper” terminal of DCP0

C interface clock

Power supply pin

2

C interface

2

C interface

2

C interface

DCP0

R

W0

2

FN8095.2

March 29, 2006

ISL90843

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V

V

CC

Voltage at any DCP Pin with

Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

W

C

W

VOLTAGE DIVIDER MODE (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0, 1, 2, or 3)

(Note 6) Integral Non-Linearity -1 1 LSB

INL

(Note 5) Differential Non-Linearity Monotonic over all tap positions -0.5 0.5 LSB

DNL

ZSerror
(Note 3)

FSerror
(Note 4)

V

MATCH

(Note 7)

TC

(Note 8) Ratiometric Temperature Coefficient DCP register set to 80 hex ±4 ppm/°C

V

RH to RL Resistance W, U versions respectively 10, 50 kΩ

RH to RL Resistance Tolerance -20 +20 %

Wiper Resistance VCC = 3.3V @ 25°C 70 Ω

Potentiometer Capacitance (Note 15) 25 pF

Zero-Scale Error W option 0 1 7 LSB

Full-Scale Error W option -7 -1 0 LSB

DCP to DCP Matching Any two DCPs at same tap position, same

+0.3

CC

CC

U option 0 0.5 2

U option -2 -1 0

voltage at all RH terminals, and same voltage at
all RL terminals

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

Power Rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

TYP

(NOTE 1) MAX UNITS

(Note 2)

(Note 2)

(Note 2)

(Note 2)

-2 2 LSB
(Note 2)

Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

CC2

I

I

LkgDig

t

DCP

(Note 15)

Vpor Power-On Recall Voltage Minimum V

VCC Supply Current
(Volatile write/read)

VCC Supply Current
(Volatile write/read)

VCC current (standby) V

SB

Leakage Current, at Pins A0, A1,
SDA and SCL Pins

DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to wiper

10k DCPs, f
Read and Write States)

50k DCPs, f
Read and Write States)

= +5.5V, 10k DCPs, I2C Interface in Standby State 2.8 mA

CC

= +5.5V, 50k DCPs, I2C Interface in Standby State 0.6 mA

V

CC

= +3.6V, 10k DCPs, I2C Interface in Standby State 1.9 mA

V

CC

= +3.6V, 50k DCPs, I2C Interface in Standby State 0.4 mA

V

CC

Voltage at pin from GND to V

change

= 400kHz; SDA = Open; (for I2C, Active,

SCL

= 400kHz; SDA = Open; (for I2C, Active,

SCL

CC

at which memory recall occurs 1.8 2.6 V

CC

3

TYP

(NOTE 1) MAX UNITS

3.8 mA

2.9 mA

-10 10 µA

1µs

FN8095.2

March 29, 2006

ISL90843

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

VccRamp VCC Ramp Rate 0.2 V/ms

(Note 15) Power-Up Delay VCC above Vpor, to DCP Initial Value Register recall

t

D

completed, and I

2

C Interface in Standby State.

SERIAL INTERFACE SPECS

V

V

A1, A0, SDA, and SCL Input

IL

Buffer LOW Voltage

A1, A0, SDA, and SCL Input

IH

-0.3 0.3*V

0.7*V

Buffer HIGH Voltage

Hysteresis

(Note 15)

V

OL

(Note 15)

Cpin

(Note 15)

f

SCL

t

IN

(Note 15)

t

AA

(Note 15)

t

BUF

(Note 15)

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STO

t

DH

(Note 15)

t

R

(Note 15)

t

F

(Note 15)

Cb

SDA and SCL Input Buffer
Hysteresis

SDA Output Buffer LOW Voltage,
Sinking 4mA

A1, A0, SDA, and SCL Pin
Capacitance

SCL Frequency 400 kHz

Pulse Width Suppression Time at

Any pulse narrower than the max spec is suppressed. 50 ns

SDA and SCL Inputs

SCL Falling Edge to SDA Output
Data Valid

Time the Bus Must be Free Before
the Start of a New Transmission

SCL falling edge crossing 30% of V
the 30% to 70% of V

SDA crossing 70% of V
SDA crossing 70% of V
condition.

window.

CC

during a STOP condition, to

CC

during the following START

CC

, until SDA exits

CC

Clock LOW Time Measured at the 30% of VCC crossing. 1300 ns

Clock HIGH Time Measured at the 70% of VCC crossing. 600 ns

START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70%

.

of V

CC

START Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL

falling edge crossing 70% of V

CC

.

Input Data Setup Time From SDA exiting the 30% to 70% of VCC window, to

SCL rising edge crossing 30% of V

CC

.

Input Data Hold Time From SCL rising edge crossing 70% of VCC to SDA

entering the 30% to 70% of V

window.

CC

STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA

rising edge crossing 30% of V

STOP Condition Hold Time for
Read, or Volatile Only Write

From SDA rising edge to SCL falling edge. Both crossing
70% of V

CC

.

Output Data Hold Time From SCL falling edge crossing 30% of V

enters the 30% to 70% of V

SDA and SCL Rise Time From 30% to 70% of V

SDA and SCL Fall Time From 70% to 30% of V

CC

CC

CC

window.

CC

.

, until SDA

CC

Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF

0.05*
V

CC

00.4V

1300 ns

600 ns

600 ns

100 ns

0ns

600 ns

600 ns

0ns

20 +

0.1 * Cb

20 +

0.1 * Cb

(Note 15)

Rpu

(Note 15)

SDA and SCL Bus Pull-Up
Resistor Off-Chip

Maximum is determined by t
For Cb = 400pF, max is about 2~2.5kΩ.

and tF.

R

1kΩ

For Cb = 40pF, max is about 15~20kΩ

TYP

(NOTE 1) MAX UNITS

3ms

CC

CC

VCC+0.3 V

10 pF

900 ns

250 ns

250 ns

V

V

4

FN8095.2

March 29, 2006

ISL90843

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

t

SU:A

t

HD:A

A1 and A0 Setup Time Before START condition 600 ns

A1 and A0 Hold Time After STOP condition 600 ns

SDA vs SCL Timing

TYP

(NOTE 1) MAX UNITS

SCL

t

SU:STA

(INPUT TIMING)

(OUTPUT TIMING)

SDA

SDA

A0 and A1 Pin Timing

SDA IN

A0, A1

SCL

t

HD:STA

t

F

START

t

SU:DAT

t

SU:A

t

HIGH

CLK 1

t

LOW

t

HD:DAT

t

R

t

SU:STO

t

t

DH

AA

STOP

t

HD:A

t

BUF

NOTES:

1. Typical values are for T

2. LSB: [V(RW)

255

= 25°C and 3.3V supply voltage.

A

– V(RW)0]/255. V(RW)

and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the

255

incremental voltage when changing from one tap to an adjacent tap.

3. ZS error = V(RW)

4. FS error = [V(RW)

5. DNL = [V(RW)

6. INL = [V(RW)

7. V

8. for i = 16 to 240 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper

9. MI =

= [V(RWx)i – V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.

MATCH

------------------------------------------------------------- -------------------------------- -

TC

V

Max V RW()

|R

255

10. Roffset = R
Roffset = R

11. RDNL = (R

12. RINL = [R

13. R

14. for i = 32 to 255, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the

TC

i

= (R

MATCH

------------------------------------------------------------ --- -

R

Max Ri()Min Ri()+[]2⁄

/LSB.

0

– VCC]/LSB.

255

– V(RW)

i

– i • LSB – V(RW)0]/LSB for i = 1 to 255.

i

Max V RW()

()Min V RW()

()Min V RW()

– R

|/255. R

0

/MI, when measuring between RW and RL.

0

/MI, when measuring between RW and RH.

255

– R

i

i-1

]/LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

()–

i

()+[]2⁄

i

and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.

255

i

10

i

---------------- -

×=

125°C

)/MI-1, for i = 32 to 255.

– (MI • i) – R0]/MI, for i = 32 to 255.

– R

)/MI, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.

i,x

i,y

Max Ri()Min Ri()–[]

---------------- -

×=

125°C

6

10

minimum value of the resistance over the temperature range.

6

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

15. This parameter is not 100% tested.

5

FN8095.2

March 29, 2006

Typical Performance Curves

www.BDTIC.com/Intersil

ISL90843

160

140

Vcc = 2.7, T = -40°C

120

100

80

60

40

WIPER RESISTANCE (Ω)

20

Vcc = 5.5, T = -40°C

0

0 50 100 150 200 250

TAP POSITION (DECIMAL)

Vcc = 2.7, T = 85°C

Vcc = 2.7, T = 25°C

Vcc = 5.5, T = 85°C

Vcc = 5.5, T = 25°C

FIGURE 1. WIPER RESISTANCE vs TAP POSITION

[ I(RW) = Vcc/R

0.2

0.15

0.1

0.05

-0.05

DNL (LSB)

-0.1

-0.15

-0.2

Vcc = 2.7, T = 25°C

0

Vcc = 2.7, T = 85°C

0 50 100 150 200 250

Vcc = 5.5, T = -40°C

Vcc = 5.5, T = 25°C

TAP POSITION (DECIMAL)

] FOR 50kΩ (U)

TOTAL

Vcc = 2.7, T = -40°C

Vcc = 5.5, T = 85°C

FIGURE 3. DNL vs TAP POSITION FOR 10kΩ (W)

1.8

1.6

1.4

1.2

(µA)

1.0

CC

0.8

0.6

STANDBY I

0.4

0.2

0.0

2.7 3.2 3.7 4.2 4.7 5.2

25°C

-40°C

V

(V)

CC

FIGURE 2. STANDBY Icc vs Vcc

0.3

Vcc = 5.5, T = -40°C

0.2

0.1

0

INL (LSB)

Vcc = 2.7, T = 85°C

-0.1

-0.2

-0.3
0 50 100 150 200 250

Vcc = 2.7, T = -40°C

Vcc = 5.5, T = 85°C

Vcc = 2.7, T = 25°C

Vcc = 5.5, T = 25°C

TAP POSITION (DECIMAL)

FIGURE 4. INL vs TAP POSITION FOR 10kΩ (W)

85°C

0.4

0.35

0.3

0.25

ZSerror (LSB)

0.2

0.15

-40-200 20406080

2.7V

5.5V

TEMPERATURE (°C)

FIGURE 5. ZSerror vs TEMPERATURE

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

FSerror (LSB)

-0.7

-0.8

-0.9

-1

-40

FIGURE 6. FSerror vs TEMPERATURE

6

-20

Vcc = 5.5V

Vcc = 2.7V

0

20 40 60 80

TEMPERATURE (°C)

FN8095.2

March 29, 2006

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL90843

1.50

1.00

0.50

CHANGE (%)

5.5V

0.00

TOTAL

-0.50

-1.00

END TO END R

-1.50

-40-200 20406080

FIGURE 7. END TO END R

2.7V

TEMPERATURE (°C)

TOTAL

TEMPERATURE

Signal at Wiper (Wiper Unloaded)

% CHANGE vs

20

10

0

TC (ppm/°C)

-10

-20

32 82 132 182 232

TAP POSITION (DECIMAL)

FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm

SCL

Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)

Wiper Movement Mid Point
From 80h to 7fh

FIGURE 9. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)

Principles of Operation

The ISL90843 is an integrated circuit incorporating four
DCPs with their associated registers, and an I
interface providing direct communication between a host
and the potentiometers.

DCP Description

Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). Each DCP has its own WR.
When the WR of a DCP contains all zeroes (WR<7:0>: 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL).
When the WR of a DCP contains all ones (WR<7:0>: FFh),
its wiper terminal (RW) is closest to its “High” terminal (RH).

2

C serial

FIGURE 10. LARGE SIGNAL SETTLING TIME

As the value of the WR increases from all zeroes (00h) to all
ones (255 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.

While the ISL90843 is being powered up, all four WRs are
reset to 80h (128 decimal), which locates RW roughly at the
center between RL and RH.

The WRs can be read or written directly using the I
interface as described in the following sections. The I

2

C serial

2

C
interface Address Byte has to be set to 00hex, 01hex,
02hex, and 03hex to access the WR of DCP0, DCP1, DCP2,
and DCP3 respectively.

I2C Serial Interface

The ISL90843 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the

7

FN8095.2

March 29, 2006

ISL90843

www.BDTIC.com/Intersil

bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90843
operates as a slave device in all applications.

All communication over the I

2

C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 11). On power-up of the ISL90843 the SDA pin is in
the input mode.

2

All I

C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90843 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 11). A START condition is ignored during the power­up of the device.

2

All I

C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 11). A STOP condition at the end

of a read operation, or at the end of a write operation places
the device in its standby mode.

An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 12).

The ISL90843 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90843 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1 and A0. The LSB is in the Read/Write

bit. Its value
is “1” for a Read operation, and “0” for a Write operation
(See Table 1).

TABLE 1. IDENTIFICATION BYTE FORMAT

Logic values at pins A1, and A0 respectively

01010A1A0R/W

(MSB) (LSB)

SCL

SDA

SCL FROM

MASTER

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

START DATA DATA STOP

STABLE CHANGE

FIGURE 11. VALID DATA CHANGES, START, AND STOP CONDITIONS

HIGH IMPEDANCE

START ACK

FIGURE 12. ACKNOWLEDGE RESPONSE FROM RECEIVER

DATA

STABLE

81 9

HIGH IMPEDANCE

8

FN8095.2

March 29, 2006

SIGNALS FROM

www.BDTIC.com/Intersil

THE MASTER

S
T
A

IDENTIFICATION

R
T

BYTE

ISL90843

WRITE

ADDRESS

BYTE

DATA
BYTE

S
T
O
P

SIGNAL AT SDA

SIGNALS FROM

THE ISL90843

00011

FIGURE 13. BYTE WRITE SEQUENCE

SIGNALS

FROM THE

MASTER

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

S
T
A

IDENTIFICATION

R

BYTE WITH

T

R/W

00011

ADDRESS

=0

A1 A0 A1 A00

0

A
C
K

BYTE

0000 00

A
C
K

FIGURE 14. READ SEQUENCE

Write Operation

A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90843 responds with an ACK. At this time, the device
enters its standby state (See Figure 13).

000 0A0A10 0000

A
C
K

S
T
A

IDENTIFICATION

R

BYTE WITH

T

R/W

01011

A
C
K

=1

A
C

FIRST READ

K

DATA BYTE

A
C
K

A

A

C

C

K

K

LAST READ
DATA BYTE

S

A

T

C

O

K

P

Read Operation

A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 14). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W
Address Byte, a second START, and a second Identification
byte with the R/W

bit set to “1”. After each of the three bytes,
the ISL90843 responds with an ACK. Then the ISL90843
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
NACK and a STOP condition) following the last bit of the last
Data Byte (See Figure 14).

bit set to “0”, an

The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 03h the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.

9

FN8095.2

March 29, 2006

MSOP Packaging Information

www.BDTIC.com/Intersil

ISL90843

10 Lead MSOP, Package Code

0.0433 [1.10] MAX.

0.0106 [0.27]

0.0067 [0.17]

10

9876

1

2

45

3

0.0197 [0.50] BSC

0.1220 [3.10]

0.1142 [2.90]

0.0039 [0.10] MAX. (S)

2

4

0.1970 [5.00]

0.1890 [4.80]

0.0374 [0.95]

0.0295 [0.75]

0.0059 [0.15]

0.0020 [0.05]

(S)

(S)

WITH PLATING

0.0098 [0.25]

GAUGE PLANE

0.0276 [0.70]

0.0157 [0.40]

0.0091 [0.23]

0.0051 [0.13]

0.0106 [0.27]

0.0067 [0.17]
WITH

PLATING

0.0080 [0.203]
REF

SECTION A-A

0.1220 [3.10]

0.1142 [2.90]

0.1220 [3.10]

0.1142 [2.90]

4

0.0050 [0.127]

BASE
METAL

3

3

A

0°-6°

A

NOTES:

1. Package dimensions conform to JEDEC specification MO-187BA.

2

2. Does not include mold flash, protrusion
or gate burrs, mold flash protrusions
or gate burrs shall not exceed 0.15 mm per side.

3

3. Does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.15 mm per side.

4

4. Does not include dambar protrusion. Allowable dambar protrusion shall be 0.8 mm.

5. Lead span/stand-off height/coplanarity are considered as special characteristics.

6. Controlling dimensions in inches [mm].

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

10

FN8095.2

March 29, 2006