Datasheet ISL90840 Datasheet (intersil)

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Quad Digitally Controlled Potentiometers (XDCP™)

ISL90840

Data Sheet November 14, 2006

Low Noise, Low Power I2C® Bus, 256 Taps

The ISL90840 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the

C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. When powered on the ISL90810’s wiper will always commence at mid-scale (128 tap position).

The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing.

Pinout

ISL90840

(20 LD TSSOP)

TOP VIEW

FN8086.2

Features

• Four potentiometers in one package

• 256 resistor taps - 0.4% resolu ti o n

•I2C serial interface

- Three address pins, up to eight devices/bus

- Write/Read capability

• Power-on preset to mid-scale (128 tap position)

• Wiper resistance: 70Ω typical @ 3.3V

• Standby current <5µA max

• Power supply: 2.7V to 5.5V

•50kΩ, 10kΩ total resistance

• 20 Ld TSSOP package

• Pb-free plus anneal available (RoHS compliant)

RW0

RH3

RL3

RW3

SCL SDA GND RW2

RL2

RH2

1 2 3 4 5 6 7 8 9 10

RL0

RH0

D.N.C.

VCC

RH1

RL1

RW1

Ordering Information

RESIST-ANCE

OPTION

PART NUMBER PART MARKING

ISL90840UIV2027Z (Notes 1 and 2) ISL90840UI27Z 50k -40 to +85 20 Ld TSSOP (Pb-free) MDP0044 ISL90840UIV2027 ISL90840UI27 50k -40 to +85 20 Ld TSSOP MDP0044 ISL90840UAV2027Z (Notes 1 and 2) ISL90840UA27Z 50k -40 to +105 20 Ld TSSOP (Pb-free) MDP0044 ISL90840WIV2027Z (Notes 1 and 2) ISL90840WI27Z 10k -40 to +85 20 Ld TSSOP (Pb-free) MDP0044 ISL90840WIV2027 ISL90840WI27 10k -40 to +85 20 Ld TSSOP MDP0044 ISL90840WAV2027Z (Notes 1 and 2) ISL90840WA27Z 10k -40 to +105 20 Ld TSSOP (Pb-free) MDP0044

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “T2” suffix for tape and reel.

(Ω)

TEMP

RANGE

(°C) PACKAGE PKG. DWG #

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Page 2

Functional Diagram

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ISL90840

Block Diagram

SCL

SDA

SCL

A0 A1 A2

I2C

INTERFACE

GND R

I2C INTERFACE

POWER-UP,

INTERFACE,

CONTROL

AND STATUS

LOGIC

WR3

WR2

WR1

WR0

DCP3

DCP2

DCP1

DCP0

GND

FN8086.2

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ISL90840

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Pin Descriptions

TSSOP PIN SYMBOL DESCRIPTION

1 RH3 “High” terminal of DCP3 2 RL3 “Low” terminal of DCP3 3 RW3 “Wiper” terminal of DCP3

4 A2 Device address for the I 5SCLI 6 SDA Serial data I/O for the I 7 GND Device ground pin 8 RW2 “Wiper” terminal of DCP2

9 RL2 “Low” terminal of DCP2 10 RH2 “High” terminal of DCP2 11 RW1 “Wiper” terminal of DCP1 12 RL1 “Low” terminal of DCP1 13 RH1 “High” terminal of DCP1 14 A0 Device address for the I 15 A1 Device address for the I 16 VCC Power supply pin 17 D.N.C. Do not connect 18 RH0 “High” terminal of DCP0 19 RL0 “Low” terminal of DCP0 20 RW0 “Wiper” terminal of DCP0

C interface clock

C interface

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Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at Any Digital Interface Pin

With Respect to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Voltage at Any DCP Pin

With Respect to V

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +105°C

ESD

HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

TOTAL

H/CL/CW

LkgDCP

VOLTAGE DIVIDER MODE (0V @ R

INL

(Note 9)

DNL

(Note 8) ZSerror

(Note 6)

FSerror (Note 7)

MATCH

RINL

RDNL

Roffset

MATCH

(Note 10)

(Note 11)

RESISTOR MODE (Measurements between R

(Note 15)

(Note 14)

(Note 13)

(Note 16)

. . . . . . . . . . . . . . . . . . . .-0.3V to VCC+0.3V

. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

RH to RL resistance W option 10 kΩ

U option 50 kΩ

to RL resistance tolerance -20 +20 %

Wiper resistance VCC = 3.3V @ +25°C,

wiper current = V Potentiometer capacitance (Note 18) 10/10/25 pF Leakage on DCP pins (Note 18) Voltage at pin from GND to V

i; VCC @ RHi; measured at RWi, unloaded; i = 0, 1, 2, or 3)

Integral non-linearity -1 1 LSB

Differential non-linearity Monotonic over all tap positions -0.5 0.5 LSB

Zero-scale error W option 0 1 7 LSB

U option 0 0.5 2 Full-scale error W option -7 -1 0 LSB

U option -2 -1 0 DCP to DCP matching Any two DCPs at same tap position, same

voltage at all RH terminals, and same voltage

at all R Ratiometric temperature coefficient DCP register set to 80 hex ±4 ppm/°C

i and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0, 1, 2 or 3)

Integral non-linearity DCP register set between 20 hex and FF

hex; monotonic over all tap positions Differential non-linearity -0.5 0.5 MI

Offset W option 0 1 7 MI

U option 0 0.5 2 DCP to DCP matching Any two DCPs at the same tap position with

the same terminal voltages

terminals

Thermal Resistance (Typical, Note 3)

20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 90

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Recommended Operating Conditions

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Automotive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Power Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

TYP

(NOTE 4) MAX UNIT

70 200 Ω

CC/RTOTAL

-2 2 LSB

-1 1 MI

-2 2 MI

0.1 1 µA

(Note 5)

(Note 12)

(°C/W)

FN8086.2

November 14, 2006

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ISL90840

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Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

(Note 17)

Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

CC1

LkgDig

DCP

(Note 18)

SERIAL INTERFACE SPECS

Hysteresis

(Note 18)

Cpin

(Note 18)

SCL

(Note 18)

BUF

(Note 18)

LOW

HIGH

SU:STA

HD:STA

SU:DAT

HD:DAT

Resistance temperature coefficient DCP register set between 20 hex and FF hex ±45 ppm/°C

VCC supply current (volatile write/read)

VCC current (standby) V

Leakage current, at pins A0, A1, A2, SDA, and SCL

DCP wiper response time SCL falling edge of last bit of DCP data byte

A2, A1, A0, SDA, and SCL input buffer

LOW voltage A2, A1, A0, SDA, and SCL input buffer

HIGH voltage SDA and SCL input buffer hysteresis 0.05*

SDA output buffer LOW voltage, sinking 4mA

A2, A1, A0, SDA, and SCL pin capacitance

SCL frequency 400 kHz Pulse width suppression time at SDA

and SCL inputs SCL falling edge to SDA output data

valid Time the bus must be free before the

start of a new transmission

Clock LOW time Measured at the 30% of VCC crossing 1300 ns Clock HIGH time Measured at the 70% of VCC crossing 600 ns START condition setup time SCL rising edge to SDA falling edge; both

START condition hold time From SDA falling edge crossing 30% of VCC

Input data setup time From SDA exiting the 30% to 70% of VCC

Input data hold time From SCL rising edge crossing 70% of VCC

= 400kHz; SDA = Open; (for I2C, active,

SCL

read and write states)

= +5.5V , I2C Interface in Standby S t ate,

Temperature range from -40°C to 85°C

= +5.5V , I2C Interface in Standby S t ate,

Temperature range from -40°C to 105°C

= +3.6V , I2C Interface in Standby S t ate,

Temperature range from -40°C to 85°C

= +3.6V , I2C Interface in Standby S t ate,

Temperature range from -40°C to 105°C

Voltage at pin from GND to V

to wiper change

Any pulse narrower than the max spec is

suppressed

SCL falling edge crossing 30% of V

SDA exits the 30% to 70% of V

SDA crossing 70% of VCC during a STOP

condition, to SDA crossing 70% of V

during the following START condition

crossing 70% of V

to SCL falling edge crossing 70% of V

window, to SCL rising edge crossing 30% of

to SDA entering the 30% to 70% of V

window

, until

-10 10 µA

-0.3 0.3*V

0.7*V

00.4V

1300 ns

600 ns

100 ns

0ns

TYP

(NOTE 4) MAX UNIT

TYP

(NOTE 4) MAX UNIT

1mA

25µA

28µA

0.8 2 µA

0.8 5 µA

1µs

VCC+0.3 V

10 pF

50 ns

900 ns

FN8086.2

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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

SU:STO

HD:STO

(Note 18)

STOP condition setup time From SCL rising edge crossing 70% of VCC,

to SDA rising edge crossing 30% of V STOP condition hod time for read, or

volatile only write Output data hold time From SCL falling edge crossing 30% of V

From SDA rising edge to SCL falling edge;

both crossing 70% of V

until SDA enters the 30% to 70% of V

window SDA and SCL rise time From 30% to 70% of V

SDA and SCL fall time From 70% to 30% of V

600 ns

20 +

0.1 * Cb 20 +

0.1 * Cb

Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF

(Note 18)

Rpu

(Note 18)

SDA and SCL bus pull-up resistor offchip

Maximum is determined by t For Cb = 400pF, max is about 2~2.5kΩ.

and t

For Cb = 40pF, max is about 15~20kΩ

SU:A

HD:A

A2, A1 and A0 setup time Before START condition 600 ns A2, A1 and A0 hold time After STOP condition 600 ns

NOTES:

4. Typical values are for T

5. LSB: [V(R incremental voltage when changing from one tap to an adjacent tap.

6. ZS error = V(R

7. FS error = [V(R

8. DNL = [V(R

9. INL = [V(R

10. V

MATCH

11. for i = 16 to 240 decimal, T = -40°C to +105°C. Max( ) is the maximum value of the wiper

12. MI =

255

13. Roffset = R Roffset = R

14. RDNL = (R

15. RINL = [R

16. R

MATCH

17. for i = 32 to 255, T = -40°C to +105°C. Max( ) is the maximum value of the resistance and Min ( ) is

– V(RW)0]/255. V(RW)

W)255

W)0

W)255

– V(RW)

W)i

– i • LSB – V(RW)]/LSB for i = 1 to 255.

W)i

= [V(RWx)i – V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.

Max V RW()

()Min V RW()

----------------------------------------------------------------------------------------------

()Min V RW()

Max V RW()

– R

|/255. R

/MI, when measuring between R

255

– R

i-1

– (MI • i) – R0]/MI, for i = 32 to 255.

= (R

– R

i,x

Max Ri()Min Ri()–[]

--------------------------------------------------------------- -

Max Ri()Min Ri()+[]2⁄

= 25°C and 3.3V supply voltage.

and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively . LSB is the

255

/LSB.

– VCC]/LSB.

]/LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

()–

()+[]2⁄

and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.

255

---------------- -

×=

145°C

and RL.

and RH.

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

)/MI-1, for i = 32 to 255.

)/MI, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.

i,y

---------------- -

×=

145°C

the minimum value of the resistance over the temperature range.

18. This parameter is not 100% tested

(NOTE 4) MAX UNIT

0ns

250 ns

1kΩ

FN8086.2

November 14, 2006

Page 7

SDA vs SCL Timing

STOP

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ISL90840

SCL

SU:STA

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

HD:STA

A0, A1, and A2 Pin Timing

SCL

SDA IN

A0, A1, OR A2

START

SU:DAT

SU:A

HIGH

CLK 1

LOW

HD:DAT

SU:STO

HD:A

BUF

Typical Performance Curves

160 140

VCC=2.7, T=-40°C

120 100

80 60 40

WIPER RESISTANCE (Ω)

VCC=5.5, T=-40°C

0 50 100 150 200 250

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

[I(RW) = V

VCC=2.7, T=+85°C

VCC=2.7, T=+25°C

VCC= 5.5, T=+85°C

VCC=5.5, T=+25°C

TAP POSITION (DECIMAL)

/ R

] FOR 50kΩ (U)

TOTAL

1.8

1.6

1.4

1.2

(µA)

0.8

0.6

STANDBY I

0.4

0.2 0

2.7 3.2 3.7 4.2 4.7 5.2

+25°C

FIGURE 2. STANDBY I

-40°C

(V)

vs V

+85°C

FN8086.2

November 14, 2006

Page 8

Typical Performance Curves (Continued)

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ISL90840

0.2

0.15

VCC=2.7, T=+25°C

0.1

0.05 0

DNL (LSB)

-0.05

-0.1

-0.15

VCC=2.7, T=+85°C

-0.2 0 50 100 150 200 250

VCC=5.5, T=-40°C

VCC=5.5, T=+25°C

TAP POSITION (DECIMAL)

VCC=2.7, T=-40°C

VCC=5.5, T=+85°C

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

0.4

0.35

0.3

0.25

ZSerror (LSB)

2.7V

0.3

VCC=5.5, T=-40°C

0.2

0.1

INL (LSB)

-0.1

-0.2

0.3

=2.7, T=+85°C

0 50 100 150 200 250

=2.7, T=-40°C

VCC=5.5, T=+85°C

=2.7, T=+25°C

TAP POSITION (DECIMAL)

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

-0.2 VCC=5.5V

-0.4

-0.6

FSerror (LSB)

VCC=2.7V

0.2

0.15

-40 -20 20 40 60 80

TEMPERATURE (°C)

5.5V

-0.8

-1

-40 -20 20 40 60 80

TEMPERATURE (°C)

FIGURE 5. ZSerror vs TEMPERATURE FOR 50kΩ (W) FIGURE 6. FSerror vs TEMPERATURE FOR 50kΩ (W)

0.3 VCC=2.7, T=+25°C

0.2

=5.5, T=+25°C

0.1

DNL (LSB)

-0.1 =5.5, T=+85°C

-0.2

-0.3

32 82 132 182 232

VCC=2.7, T=-40°C

TAP POSITI ON (DECIMAL)

=5.5, T=-40°C

VCC=2.7, T=+85°C

FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR

50kΩ (U)

0.5 V

=2.7, T=+25°C

0.3

0.1

-0.1

INL (LSB)

-0.3

-0.5 32 82 132 182 232

=2.7, T=+85°C

=5.5, T=+25°C

TAP POSITI ON (DECIMAL)

VCC=5.5, T=-40°C

VCC=5.5, T=+85°C

VCC=2.7,

T=-40°C

FIGURE 8. INL vs TAP POSITION IN RHEOST AT MODE FOR

50kΩ (U)

FN8086.2

November 14, 2006

Page 9

Typical Performance Curves (Continued)

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ISL90840

1.5

2.7V

0.5

CHANGE (%)

5.5V

TOTAL

-0.5

-1

END TO END R

-1.5

-40 -20 20 40 60 80

FIGURE 9. END TO END R

TEMPERATURE FOR 50kΩ (W)

TC (ppm/°C)

-5

TEMPERATURE (°C)

% CHANGE vs

TOTAL

TC (ppm/°C)

-10

-20 32 82 132 182 232

TAP POSITI ON (DECIMAL)

FIGURE 10. TC FOR VOLT AGE DIVIDER MODE IN ppm FOR

50kΩ (W)

INPUT

OUTPUT

-15

-25 32 82 132 182 232

TAP POSITI ON (DECIMAL)

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FOR 50kΩ (W)

SIGNAL AT WIPER (WIPER UNLOADED)

WIPER MOVEMENT MID POINT FROM 80h TO 7fh

FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)

TAP POSITION = MID POINT

=9.4k

TOTAL

FIGURE 12. FREQUENCY RESPONSE (2.2MHz)

SCL

SIGNAL AT WIPER (WIPER UPLOADED MOVEMENT FROM ffh TO 00h

FIGURE 14. LARGE SIGNAL SETTLING TIME

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ISL90840

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Principles of Operation

The ISL90840 is an integrated circuit incorporating four DCPs with their associated registers, and an I interface providing direct communication between a host and the potentiometers.

C serial

DCP Description

Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (R connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[7:0]: 00h), its wiper terminal (R When the WR of a DCP cont ains al l ones (WR [7:0] : FFh), it s wiper terminal (R the value of the WR increases from all zeroes (0 decimal) to all ones (255 decimal), the wiper moves monotonically from the position closest to R time, the resistance between R monotonically, while the resistance between R decreases monotonically.

While the ISL90840 is being powered up, all four WRs are reset to 80h (128 decimal), which locates R center between R

The WRs can be read or written to directly using the I2C serial interface as described in the following sections. The

C interface Address Byte has to be set to 00h, 01h, 02h, and 03h to access the WR of DCP0, DCP1, DCP2, and DCP3 respectively

and RL pins). The RW pin of each DCP is

) is closest to its “Low” terminal (RL).

) is closest to its “High” terminal (RH). As

to the closest to RH. At the same

and RH.

and RL increases

roughly at the

and RW

I2C Serial Interface

The ISL90840 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL90840 operates as a slave device in all applications.

All communication over the I sending the MSB of each byte of data first.

C interface is conducted by

All I

C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL90840 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 15). A START condition is ignored during the powerup of the device.

All I

C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 15). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode.

An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 16).

The ISL90840 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL90840 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 0101 as the four MSBs, and the following three bits matching the logic values present at pins A2, A1, and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation, and “0” for a Write operation (See Table 1).

TABLE 1. IDENTIFICATION BYTE FORMAT

Logic values at pins A2, A1, and A0 respectively

0101A2A1A0R/W

(MSB) (LSB)

Protocol Conventions

Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 15). On power-up of the ISL90840 the SDA pin is in the input mode.

FN8086.2

November 14, 2006

Page 11

SCL

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SDA

ISL90840

SCL FROM

MASTER

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

START DATA DATA STOP

STABLE CHANGE

FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS

HIGH IMPEDANCE

START ACK

FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER

DATA

STABLE

81 9

HIGH IMPEDANCE

FN8086.2

November 14, 2006

Page 12

SIGNALS FROM

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THE MASTER

S T

IDENTIFICATION

R T

BYTE

ISL90840

WRITE

ADDRESS

BYTE

DATA

BYTE

S T O P

SIGNAL AT SDA

SIGNALS FROM

THE ISL90840

00011

FIGURE 17. BYTE WRITE SEQUENCE

SIGNALS

FROM THE

MASTER

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

IDENTIFICATION

BYTE WITH

R/W

00011

ADDRESS

A C K

BYTE

0000 00A0A1A2 A0A1A2

A C K

FIGURE 18. READ SEQUENCE

Write Operation

A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL90840 responds with an ACK. At this time, the device enters its standby state (See Figure 17).

0000A0A1A2 0000

A C K

S T A

IDENTIFICATION

BYTE WITH

R/W

01011

A C K

A C

FIRST READ

DATA BYTE

A C K

LAST READ DATA BYTE

S T

Read Operation

A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 18). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W Address Byte, a second START, and a second Identification byte with the R/W

bit set to “1”. After each of the three bytes, the ISL90840 responds with an ACK. Then the ISL90840 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a ACK

and STOP condition) following the last bit of the last

Data Byte (See Figure 18).

bit set to “0”, an

The Data Bytes are from the registers indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 03h, the pointer “rolls over” to 00h, and the device continues to output data for each ACK received.

FN8086.2

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Page 13

ISL90840

www.BDTIC.com/Intersil

Thin Shrink Small Outline Package Family (TSSOP)

SEATING PLANE

N LEADS

0.25 CAB

0.10 C

TOP VIEW

SIDE VIEW

SEE DETAIL “X”

(N/2)+1

(N/2)

0.10 CABM

PIN #1 I.D.

0.20 C2XB A

N/2 LEAD TIPS

0.05

MDP0044

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A 1.20 1.20 1.20 1.20 1.20 Max

A1 0.10 0.10 0.10 0.10 0.10 ±0.05

A2 0.90 0.90 0.90 0.90 0.90 ±0.05

b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06

c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06

D 5.00 5.00 6.50 7.80 9.70 ±0.10

E 6.40 6.40 6.40 6.40 6.40 Basic

E1 4.40 4.40 4.40 4.40 4.40 ±0.10

e 0.65 0.65 0.65 0.65 0.65 Basic

L 0.60 0.60 0.60 0.60 0.60 ±0.15

L1 1.00 1.00 1.00 1.00 1.00 Reference

Rev. E 12/02

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side.

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

END VIEW

DETAIL X

GAUGE PLANE

0.25

0° - 8°

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or it s sub sidi ari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8086.2

November 14, 2006