Datasheet ISL9005A Datasheet (intersil)

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ISL9005A

Data Sheet March 27, 2008

LDO with Low I

SUPPLY

ISL9005A is a high performance Low Dropout linear regulator capable of sourcing 300mA current. It has a low standby current and high-PSRR and is stable with output capacitance of 1µF to 10µF with ESR of up to 200mΩ.

The ISL9005A has a high PSRR of 75dB and an output noise of less than 45µV

RMS

quiescent current of 50µA, (typical) and 0.1µA shutdown current, the ISL9005A is an ideal choice for portable wireless equipment.

Several different fixed voltage outputs are standard. Output voltage options for each LDO range are from 1.5V to 3.3V. Other output voltage options may be available upon request.

, High PSRR

. When coupled with a no load

Pinout

ISL9005A

(8 LD 2x3 DFN)

TOP VIEW

VIN

EN NC NC

1 2 3 4

GND

FN6452.1

Features

• 300mA high performance LDO

• Excellent transient response to large current steps

• Excellent load regulation: <0.1% voltage change across full range of load current

• High PSRR: 75dB @ 1kHz

• Wide input voltage capability: 2.3V to 6.5V

• Very low quiescent current: 50µA

• Low dropout voltage: typically 200mV @ 300mA

• Low output noise: typically 45µV

@ 100µA (1.5V)

RMS

• Stable with 1µF to 10µF ceramic capacitors

• Soft-start to limit input current surge during enable

• Current limit and overheat protection

• ±1.8% accuracy over all operating conditions

• Tiny 2mmx3mm 8 Ld DFN package

• -40°C to +85°C operating temperature range

• Pb-free (RoHS compliant)

Applications

• PDAs, cell phones and smart phones

• Portable instruments, MP3 players

• Handheld devices, including medical handhelds

Ordering Information

PACKAGE

PART NUMBER

(Notes 1, 2)

ISL9005AIRNZ-T EBV 3.3 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRMZ-T EBT 3.0 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRLZ-T EBS 2.9 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRKZ-T EBR 2.85 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRJZ-T EBP 2.8 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRRZ-T EBW 2.6 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRFZ-T EBN 2.5 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRCZ-T EBM 1.8 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRBZ-T EBL 1.5 -40 to +85 8 Ld 2x3 DFN L8.2x3

NOTES:

1. These Intersil Pb-free plastic p ackaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Please refer to TB347 for details on reel specifications.

3. For other output voltages, contact Intersil Marketing.

PART

MARKING

VO VOLTAGE (V)

(Note 3) TEMP RANGE (°C)

Tape and Reel

(Pb-Free) PKG. DWG. #

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Page 2

ISL9005A

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V

VO Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V

Recommended Operating Conditions

Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3V to 6.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

4. θ

Tech Brief TB379.

5. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

Thermal Resistance (Notes 4, 5) θ

8 Ld 2x3 DFN Package . . . . . . . . . . . . 69 10

Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature

range of the device as follows: T C

=1µF; CO = 1µF.

PARAMETER SYMBOL TEST CONDITIONS

DC CHARACTERISTICS

Supply Voltage V Ground Current Quiescent condition: I

Shutdown Current I UVLO Threshold V

Regulation Voltage Accuracy Initial accuracy at VIN = VO+ 0.5V, IO = 10mA, TJ = +25°C -0.7 +0.7 %

Maximum Output Current I Internal Current Limit I Dropout Voltage (Note 7) V

Thermal Shutdown Temperature T

AC CHARACTERISTICS

Ripple Rejection (Note 6) I

Output Noise Voltage (Note 6) I

DDS

UV+

UV-

MAX

LIM DO1IO

DO2IO

DO3IO SD+

SD-

LDO active 50 75 µA LDO disabled @ +25°C 0.1 1.0 µA

= VO+ 0.5V to 5.5V, IO = 10µA to 300mA, TJ = +25°C -0.8 +0.8 %

= VO+ 0.5V to 5.5V, IO = 10µA to 300mA,

= -40°C to +125°C

Continuous 300 mA

= 300mA; VO < 2.5V 300 500 mV = 300mA; 2.5V ≤ VO ≤ 2.8V 250 400 mV = 300mA; VO > 2.8V 200 325 mV

= 10mA, VIN = 2.8V (min), VO = 1.8V

@ 1kHz 75 dB @ 10kHz 60 dB @ 100kHz 40 dB

= 100µA, VO = 1.5V, TA = +25°C

BW = 10Hz to 100kHz

= -40°C to +85°C; V

= 0µA

= (VO+ 0.5V) to 5.5V with a minimum VIN of 2.3V;

MIN

(Note 8) TYP

2.3 6.5 V

1.9 2.1 2.3 V

1.6 1.8 2.0 V

-1.8 +1.8 %

350 475 600 mA

(°C/W) θJC (°C/W)

MAX

(Note 8) UNITS

145 °C 110 °C

45 µV

RMS

FN6452.1

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ISL9005A

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Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature

range of the device as follows: T

=1µF; CO = 1µF. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

DEVICE START-UP CHARACTERISTICS

Device Enable Time t

LDO Soft-start Ramp Rate t

EN PIN CHARACTERISTICS

Input Low Voltage V Input High Voltage V Input Leakage Current IIL, I Pin Capacitance C

NOTES:

6. Limits established by characterization and are not production tested.

7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.

8. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.

Time from assertion of the ENx pin to when the output voltage

reaches 95% of the VO (nom) Slope of linear portion of LDO output voltage ramp during

SSR

start-up

IL IH

Informative 5 pF

= -40°C to +85°C; V

= (VO+ 0.5V) to 5.5V with a minimum VIN of 2.3V;

MIN

(Note 8) TYP

-0.3 0.5 V

1.4 VIN+0.3 V

MAX

(Note 8) UNITS

250 500 µs

30 60 µs/V

0.1 µA

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Typical Performance Curves

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ISL9005A

0.8

LOAD

(%)

-0.2

OUTPUT VOLTAGE, V

-0.4

-0.6

-0.8

0.6

0.4

0.2

-40°C

0.0 +25°C

+85°C

3.8 4.2 6.25.8 INPUT VOLTAGE (V)

FIGURE 1. OUTPUT VOLT A GE vs INPUT VOL TAGE

VO = 3.3V

= 0mA

6.63.4 4.6 5.0 5.4

0.10 V

= 3.8V

-40°C

= 3.3V

-0.02

-0.04

-0.06

OUTPUT VOLTAGE CHANGE (%)

-0.08

-0.10

0.08

0.06

0.04

0.02

0.00

+25°C

+85°C

50 150 250 350

100 200 300 4000

LOAD CURRENT - I

(mA)

FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT

(3.3V OUTPUT)

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

OUTPUT VOLTAGE CHANGE (%)

-0.08

-0.10

= 3.8V

= 3.3V

= 0mA

LOAD

-10 20 50 110-40

-25 5 35 8065 95 125 TEMPERATURE (°C)

3.4

IO = 0mA

3.3

(V)

3.2

3.1

3.0

OUTPUT VOLTAGE, V

2.9

2.8

3.1 3.6 4.1 4.6 5.1 6.15.6

IO = 150mA

IO = 300mA

INPUT VOLTAGE (V)

VO = 3.3V

FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE FIGURE 4. OUTPUT VOLT AGE vs INPUT VO L TAGE (3.3V

OUTPUT)

6.5

2.9 IO = 0mA

2.8

2.7

2.6

2.5

OUTPUT VOLTAGE, VO (V)

2.4

2.3

2.63.13.64.14.65.1 6.1

IO = 150mA

IO = 300mA

INPUT VOLTAGE (V)

VO = 2.8V

5.6

FIGURE 5. OUTPUT VOLT A GE vs INPUT VOL TAGE

6.5

350

300

(mV)

250

200

150

100

DROPOUT VOLTAGE, V

50 100 150 200 250 300 350 4000

FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT

(2.8V OUTPUT)

VO = 2.8V

OUTPUT LOAD (mA)

VO = 3.3V

March 27, 2008

FN6452.1

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Typical Performance Curves (Continued)

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350

VO = 3.3V

300

(mV)

250

200

150

100

DROPOUT VOLTAGE, V

+85°C

+25°C

-40°C

ISL9005A

+125°C

GROUND CURRENT (µA)

+25°C

-40°C

VO = 3.3V

50 100 150 200 250 300 350 4000

OUTPUT LOAD (mA)

3.0 3.5 4.58 5.5 6.0

4.0 5.0 6.5 INPUT VOLTAGE (V)

FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE

GROUND CURRENT (µA)

-25 5 35 8065 95 125

-10 20 50 110-40 TEMPERATURE (°C)

VIN = 3.8V

LOAD

200 180 160 140 120 100

GROUND CURRENT (µA)

+85°C

+25°C

80 60 40 20

50 100 150 200 250 4000

LOAD CURRENT (mA)

-40°C

= 3.8V

VO = 3.3V

350300

FIGURE 9. GROUND CURRENT vs LOAD FIGURE 10. GROUND CURRENT vs TEMPERATURE

= 3.3V

= 0µA

VO = 2.85V

= 150mA

VOLTAGE (V)

0.5 1.0 1.5 2.0 2.5 3.0 3.5 5.0

TIME (s)

4.0 4.50

(V)V

(V)

0.20.40.60.81.01.21.41.60

FIGURE 11. POWER-UP/POWER-DOWN FIGURE 12. TURN ON/TURN OFF RESPONSE

TIME (ms)

= 5.0V

VO = 2.85V

IL = 150mA

CL = 1µF

1.8 2.0

FN6452.1

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Typical Performance Curves (Continued)

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ISL9005A

4.3V

3.6V

10mV/DIV

400µs/DIV

VO = 3.3V

= 300mA

LOAD

= 1µF

LOAD

4.2V

3.5V

10mV/DIV

400µs/DIV

VO = 2.8V

= 300mA

LOAD

= 1µF

LOAD

FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT

VO (25mV/DIV)

1.000

300mA

100µA

0.100

0.010

SPECTRAL NOISE DENSITY (µV/√Hz)

0.001 10 100 1k 10k 100k 1M

LOAD

VIN = 3.6V

= 1.8V

= 10mA

= 1µF

FREQUENCY (Hz)

LOAD

100µs/DIV

= 1.8V

VIN = 2.8V

FIGURE 15. LOAD TRANSIENT RESPONSE FIGURE 16. SPECTRAL NOISE DENSITY vs FREQUENCY

100

90 80 70 60 50

PSRR (dB)

40 30 20 10

100 1k 10k 100k 1M

FREQUENCY (Hz)

VIN = 3.6V

LOAD

= 1.8V

= 10mA

= 1µF

FIGURE 17. PSRR vs FREQUENCY

FN6452.1

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ISL9005A

www.BDTIC.com/Intersil

Pin Description

NUMBER PIN NAME DESCRIPTION

1 VIN Supply Voltage/LDO Input: Connect a 1µF capacitor to GND. 2 EN LDO Enable. 3 NC Do not connect. 4 NC Do not connect. 5 GND GND is the connection to system ground. Connect to PCB Ground plane. 6 NC Do not connect. 7 NC Do not connect. 8 VO LDO Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended).

Typical Application

(2.3V TO 5V)

ENABLE

OFF

ISL9005A

VIN

C1, C2: 1µF X5R CERAMIC CAPACITOR

VO NC NC

GND

7 6 5

OUT

FN6452.1

March 27, 2008

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ISL9005A

www.BDTIC.com/Intersil

Block Diagram

VIN

UVLO

CONTROL

LOGIC

BANDGAP AND TEMPERATURE

SENSOR

SHORT CIRCUIT,

THERMAL PROTECTION,

SOFT-START

VOLTAGE AND

REFERENCE GENERATOR

GND

1.0V

0.94V

0.9V

Functional Description

The ISL9005A contains all circuitry required to implement a high performance LDO. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9005A adjusts its biasing to achieve the lowest standby current consumption.

The device also integrates current limit protection, smart thermal shutdown protection, and soft-start. Smart thermal shutdown protects the device against overheating.

Power Control

The ISL9005A has an enable pin (EN) to control power to the LDO output. When EN is low, the device is in shutdown mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1µA. When the enable pin is asserted, the device first monitors the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power-up. Once the references are stable, a fast-start circuit powers up the LDO.

During operation, whenever the VIN voltage drops below about 1.84V, the ISL9005A immediately disables the LDO output. When VIN rises back above 2.1V, the device re-initiates its start-up sequence and LDO operation will resume automatically.

Reference Generation

The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter.

The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference and other voltage references required for current generation and over-temperature detection.

The current generator outputs references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination.

LDO Regulation and Programmable Output Divider

The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9005A provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1µF to 10µF output capacitor that has a toleranc e better than 2 0% and ESR less than 200m

Ω, and the design is performance-optimized for a

1µF output capacitor. Unless limited by the application, use of an output capacitor value above 4.7µF is not recommended as LDO performance improvement is minimal.

Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30µs/V to minimize current surge. The ISL9005A provides short-circuit protection by limiting the output current to about 425mA.

The LDO uses an independently trimmed 1V reference as its input. An internal resistor divider drops the LDO output voltage down to 1V. This is comp ared to the 1V reference for regulation. The resistor division ratio is programmed in the factory.

Overheat Detection

The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about +140°C, if the LDO is sourcing more than 50mA it shuts down until the die cools sufficiently . Once the die temperature falls back below about +110°C, the disabled LDO is re-enabled and soft-start automatically takes place.

FN6452.1

March 27, 2008

Page 9

Dual Flat No-Lead Plastic Package (DFN)

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ISL9005A

(DATUM A)

NX (b)

INDEX

AREA

SEATING

(DATUM B)

INDEX AREA

NX L

PLANE

(A1)

TOP VIEW

SIDE VIEW

D2/2

N-1

(Nd-1)Xe

REF.

BOTTOM VIEW

NX b

E2/2

0.10

ABC0.15

0.15

NX k

0.10

0.08

L8.2x3

8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 A1 - - 0.05 A3 0.20 REF -

b 0.20 0.25 0.32 5,8

D 2.00 BSC D2 1.50 1.65 1.75 7,8

E 3.00 BSC E2 1.65 1.80 1.90 7,8

e 0.50 BSC k0.20 - - L 0.30 0.40 0.50 8

N82 Nd 4 3

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

BAMC

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.

NOTESMIN NOMINAL MAX

Rev. 0 6/04

SECTION "C-C"

FOR EVEN TERMINAL/SIDE

TERMINAL TIP

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subs idi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6452.1

March 27, 2008