Datasheet ISL83384E Datasheet (intersil)

®

www.BDTIC.com/Intersil

ISL83384E

Data Sheet March 15, 2005

±15kV ESD Protected, +3V to +5.5V,
1 Microamp, 250Kbps, RS-232
Transmitter/Receiver

The Intersil ISL83384E contains 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at V
applications are PDAs, Palmtops, and notebook and laptop
computers where the low operational, and even lower
standby, power consumption is critical. Efficient on-chip
charge pumps, coupled with a manual powerdown function
reduces the standby supply current to a 1µA trickle. Small
footprint packaging, and the use of small, low value
capacitors ensure board space savings as well. Data rates
greater than 250Kbps are guaranteed at worst case load
conditions. This device is fully compatible with 3.3V only
systems, mixed 3.3V and 5.0V systems, and 5.0V only
systems.

The single pin powerdown function (SHDN
the transmitters and receivers, while shutting down the
charge pump to minimize supply current drain.

Table 1 summarizes the features of the ISL83384E, while
Application Note AN9863 summarizes the features of each
device comprising the ICL32XX 3V family.

= 3.0V. Targeted

CC

= 0) disables all

FN6017.3

Features

• ESD Protection for RS-232 I/O Pins to ±15kV (IEC61000)

• Drop In Replacement for MAX3384E, SP385E

• Low Power, Pin Compatible Upgrade for 5V MAX222,
SP310E, ADM222, and LT1780

• Single SHDN

• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V

• RS-232 Compatible with V

• Latch-Up Fre e

• On-Chip Voltage Converters Require Only Four External

0.1µF Capacitors

• Receiver Hysteresis For Improved Noise Immunity

• Very Low Supply Current . . . . . . . . . . . . . . . . . . . . 0.3mA

• Guaranteed Minimum Data Rate . . . . . . . . . . . . 250Kbps

• Guaranteed Minimum Slew Rate. . . . . . . . . . . . . . . 6V/µs

• Wide Power Supply Range. . . . . . . . Single +3V to +5.5V

• Low Supply Current in Powerdown State. . . . . . . . . .<1µA

• Pb-Free Available (RoHS Compliant)

Pin Disables Transmitters and Receivers

= 2.7V

CC

Applications

Ordering Information

PART NUMBER

ISL83384ECA 0 to 70 20 Ld SSOP M20.209
ISL83384ECAZA

(See Note)
ISL83384ECA-T 0 to 70 Tape and Reel M20.209
ISL83384ECAZA-T

(See Note)

NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

NUMBER

ISL83384E 2 2 0 250 NO NO YES NO

TEMP.

RANGE (°C) PACKAGE

0 to 70 20 Ld SSOP

0 to 70 Tape and Reel

NO. OF

Tx.

NO. OF

Rx.

(Pb-free)

(Pb-free)

MONITOR Rx.

NO. OF

(R

OUTB

PKG.

DWG. #

M20.209

M20.209

TABLE 1. SUMMARY OF FEATURES

DATA

)

RATE

(Kbps)

• Any System Requiring RS-232 Communication Ports

- Battery Powered, Hand-Held, and Portable Equipment

- Laptop Computers, Notebooks, Palmtops

- Modems, Printers and other Peripherals

- Digital Cameras

- Cellular/Mobile Phones

Related Literature

• Technica l Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

• AN9863, “3V to +5.5V, 250k-1Mbps, RS-232
Transmitters/Receivers”

MANUAL
Rx. ENABLE
FUNCTION?

READY

OUTPUT?

POWER-

DOWN?

POWERDOWN

AUTOMATIC

FUNCTION?

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2001, 2003, 2004, 2005. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

ISL83384E

www.BDTIC.com/Intersil

Pinout

ISL83384E (SSOP)

TOP VIEW

NC

1

C1+

2
3

V+
C1-

4

C2+

5

C2-

6

V-

7

T2

8

OUT

R2

9

IN

10

NC

Typical Operating Circuit

TTL/CMOS

LOGIC LEVELS

20

SHDN
V

19

CC

GND

18
17

T1

OUT

R1

16

IN

R1

15

OUT

T1

14

IN

T2

13

IN

12

R2

OUT

NC

11

+3.3V to +5V

0.1µF

0.1µF

R1

R2

C

C

T1

T2

OUT

OUT

Pin Descriptions

PIN FUNCTION

VCCSystem power supply input (3.0V to 5.5V).

V+ Internally generated positive transmitter supply (+5.5V).

V- Internally generated negative transmitter supply (-5.5V).

GND Ground connection.

C1+ External capacitor (voltage doubler) is connected to this lead.

C1- External cap acitor (voltage doubler) is connected to this lead.

C2+ External capacitor (voltage inverter) is connected to this lead.

C2- External capa citor (voltage inverter) is connected to this lead.

TTL/CMOS compatible transmitter Inputs.

T

IN

±15kV ESD Protected, RS-232 level (nominally ±5.5V)

T

OUT

transmitter outputs.
±15kV ESD Protected, RS-232 compatible receiver inputs.

R

IN

R

TTL/CMOS level receiver outputs.

OUT

Active low input to shut down transmitters, receivers, and

SHDN

on-board power supply, to place device in low power mode.

ISL83384E

C3 (OPTIONAL CONNECTION, NOTE 1)

+

0.1µF
2

1

2

IN

IN

C1+

+

4

C1-

5

C2+

+

6

C2-

14

13

15

12

19

V

CC

T

T

R

1

R

2

V+

V-

1

2

5kΩ

5kΩ

+

3

C

3

+

0.1µF

7

C

4

0.1µF

+

17

T1

OUT

8

T2

OUT

16

R1

9

R2

RS-232
LEVELS

IN

IN

20

GND

SHDN

18

NOTES:

1. The negative terminal of C

can be connected to either VCC or GND.

3

2

V

CC

FN6017.3

March 15, 2005

ISL83384E

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V

V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V

Input Voltages

, SHDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V

T

IN

R

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V

IN

Output Voltages

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V

T

OUT

R

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V

OUT

Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous

T

OUT

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. θ

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Thermal Resistance (Typical, Note 2)

20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 125

Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(Lead Tips Only)

θ

JA

(°C/W)

Operating Conditions

Tem perature Range

ISL83384ECX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Electrical Specifications Test Conditions: V

Typicals are at T

PARAMETER TEST CONDITIONS

DC CHARACTERISTICS

Supply Current, Powerdown SHDN

Supply Current, Enabled All Outputs Unloaded, SHDN

LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS

Input Logic Threshold Low T
Input Logic Threshold High T
Input Leakage Current T
Output Leakage Current SHDN
Output Voltage Low I
Output Voltage High I

RECEIVER INPUTS

Input Voltage Range Full -25 - 25 V
Input Threshold Low V

Input Threshold High V

Input Hysteresis Full 0.2 0.5 1 V
Input Resistance Full 3 5 7 kΩ

TRANSMITTER OUTPUTS

Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V
Output Resistance V
Output Short-Circuit Current Full ±7 ±35 - mA
Output Leakage Current V

TIMING CHARACTERISTICS

Maximum Data Rate R

= GND 25 - 0.1 5 µA

, SHDN Full - - 0.8 V

IN

, SHDN Full 2.4 - - V

IN

, SHDN Full - ±0.01 ±1.0 µA

IN

= GND Full - ±0.05 ±10 µA

= 3.2mA Full - - 0.4 V

OUT

= -1.0mA Full V

OUT

= 3.3V 25 0.6 1.2 - V

CC

= 5.0V Full 0.8 1.5 - V

V

CC

= 3.3V 25 - 1.5 2.4 V

CC

= 5.0V Full - 1.8 2.4 V

V

CC

= V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω

CC

= ±12V, VCC = 0V or 3V to 5.5V, SHDN = GND Full - - ±10 µA

OUT

= 3kΩ, CL = 1000pF, One Transmitter Switching Full 250 500 - Kbps

L

= 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.

CC

= 25°C

A

TEMP

(°C) MIN TYP MAX UNITS

Full - 1 50 µA

= V

CC

Full - 0.3 3.0 mA

CC

-0.6 V

-0.1 - V

CC

3

FN6017.3

March 15, 2005

ISL83384E

www.BDTIC.com/Intersil

Electrical Specifications Test Conditions: V

Typicals are at T

PARAMETER TEST CONDITIONS

Transmitter Propagation Delay Transmitter Input to

Receiver Propagation Delay Receiver Input to Receiver

Transmitter Output Enable Time From SHDN
Transmitter Output Disable Time From SHDN
Transmitter Skew t
Receiver Skew t
Transition Region Slew Rate R

ESD PERFORMANCE

RS-232 Pins (T

All Other Pins Human Body Model 25 - ±3-kV

NOTE:

3. Transmitter skew is measured at the transmitter zero crossing points.

, RIN) Human Body Model 25 - ±15 - kV

OUT

Transmitter Output,

= 1000pF

C

L

Output, C

PHL
PHL

= 3kΩ to 7kΩ,

L

Measured From 3V to -3V or

-3V to 3V

IEC61000-4-2 Contact Discharge 25 - ±8-kV
IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV

= 150pF

L

- t

(Note 3) 25 - 100 - ns

PLH

- t

PLH

= 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.

CC

= 25°C (Continued)

A

TEMP

(°C) MIN TYP MAX UNITS

t

PHL

t

PLH

t

PHL

t

PLH

Rising Edge to T
Falling Edge to T

= ±3V 25 - 50 - µs

OUT

= ±5V 25 - 600 - ns

OUT

VCC = 3.3V, CL = 150pF to
2500pF

V

= 4.5V, CL = 150pF to

CC

2500pF

Full - 0.6 3.5 µs
Full - 0.7 3.5 µs

Full - 0.2 1 µs
Full - 0.3 1 µs

25 - 100 - ns
25 4 - - V/µs

25 6 - - V/µs

Detailed Description

The ISL83384E operates from a single +3V to +5.5V supply,
guarantees a 250Kbps minimum data rate, requires only four
small external 0.1µF capacitors, features low power
consumption, and meets all ElA RS-232C and V.2 8
specifications. The circuit is divided into three sections: The
charge pump, the transmitters, and the receivers.

Charge-Pump

Intersil’s new ISL83384E utilizes regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a V
low as 3.0V. This allows these devices to maintain RS-232
compliant output levels over the ±10% tolerance range of

3.3V powered systems. The efficient on-chip power supplies
require only four small, external 0.1µF capacitors for the
voltage doubler and inverter functions over the full V
range. The charge pumps operate discontinuously (i.e., they
turn off as soon as the V+ and V- supplies are pumped up to
the nominal values), resulting in significant power savings.

Transmitters

The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies, these
transmitters deliver true RS-232 levels over a wide range of
single supply system voltages.

supply as

CC

CC

All transmitter outputs disable and assume a high
impedance state when the device enters the powerdown
mode (see Table 2). These outputs may be driven to ±12V
when disabled.

All devices guarantee a 250Kbps data rate for full load
conditions (3kΩ and 1000pF), V

≥ 3.0V, with one

CC

transmitter operating at full speed. Under more typical
conditions of V

≥ 3.3V, RL = 3kΩ, and CL = 250pF, one

CC

transmitter easily operates at 900Kbps.
Transmitter inputs float if left uncon nected (there are no pull-

up resistors), and may cause I

increases. Connect

CC

unused inputs to GND for the best performance.

TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE

SHDN

INPUT

TRANSMITTER

OUTPUTS

H Active Active Normal Operation

L High-Z High-Z Manual Powerdown

RECEIVER

OUTPUTS MODE OF OPERATION

Receivers

The ISL83384E contains standard inverting receivers that
three-state via the SHDN
powered down peripherals must be disabled to prevent
current flow through the peripheral’s protection diodes (see
Figures 2 and 3).

control line. Receivers driving

4

FN6017.3

March 15, 2005

ISL83384E

www.BDTIC.com/Intersil

All the receivers convert RS-232 signals to CMOS output
levels and accept inputs up to ±30V while presenting the
required 3kΩ to 7kΩ input impedance (see Figure 1) even if
the power is off (V

= 0V). The receivers’ Schmitt trigger

CC

input stage uses hysteresis to increase noise immunity and
decrease errors due to slow input signal transitions.

V

CC

R

XIN

-25V ≤ V

FIGURE 1. INVERTING RECEIVER CONNECTIONS

RIN

GND

≤ +25V

5kΩ

R

GND ≤ V

XOUT

ROUT

≤ V

CC

Low Power Operation

This 3V device requires a nominal supply current of 0.3mA,
even at V

= 5.5V, durin g normal operation (not in

CC

powerdown mode). This is considerably less than the 11mA
current required by comparable 5V RS-232 devices, allo wing
users to reduce system power simply by replacing the old
style device with the ISL83384E.

Low Power, Pin Compatible Replacement

Pin compatibility with existing 5V products (e.g., MAX222),
coupled with the wide operating supply range, make the
ISL83384E a potential lower power, higher performance
drop-in replacement for existing 5V applications. As long as
the ±5V RS-232 output swings are acceptable, and
transmitter pull-up resistors aren’t required, the ISL83384E
should work in most 5V applications.

When replacing a device in an existing 5V application, it is
acceptable to terminate C
Operating Circuit”. Nevertheless, terminate C
possible, as slightly better performance results from this
configuration.

to VCC as shown on the “Typical

3

to GND if

3

Po werdown Functionality

The already low current requirement drops significantly
when the device ente rs powerdown mod e. In powerdow n ,
supply current drops to 1µA, because the on-chip charge
pump turns off (V+ collapses to V
and the transmitter and receiver outputs three-state. This
micro-power mode makes these devices ideal for battery
powered and portable applications.

, V- collapses to GND),

CC

V

CC

V

CC

V

OUT = VCC

Rx

POWERED

DOWN

UART

Tx

= GND

GND

FIGURE 2. POWER DRAIN THROUGH POWERED DO WN

PERIPHERAL

TO

WAKE-UP

LOGIC

V

CC

R

X

POWERED

DOWN

UART

FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN

PWR
MGT

LOGIC

T

X

SHDN

TRANSITION

DETECTOR

V

OUT =

V

CC

HI-Z

SHDN

V-

V

CC

CURRENT
FLOW

OLD

RS-232 CHIP

ISL83384E

ISL83384E

Software Controlled (Manual) Powerdown

The ISL83384E may be forced into its low power, standby
state via a simple shutdown (SHDN

) pin (see Figure 4).
Driving this pin high enables normal operation, while driving
it low forces the IC into its powerdown state. The time

CPU

required to exit powerdown, and resume transmission is less
than 50µs. Connect SHDN

to VCC if the powerdown function

isn’t needed.

FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN

5

I/O

UART

FN6017.3

March 15, 2005

ISL83384E

www.BDTIC.com/Intersil

Capacitor Selection

The charge pumps require 0.1µF or greater capacitors for
operation with 3.3V ≤ V

≤ 5.5V. Increasing the capacitor

CC

values (by a factor of 2) reduces ripple on the transmitter
outputs and slightly reduces power consumption. C
and C

can be increased without increasing C1’s value,

4

however, do not increase C
and C

to maintain the proper ratios (C1 to the other

4

without also increasing C2, C3,

1

, C3,

2

capacitors).
When using minimum required capacitor values, make sure

that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.

Operation Down to 2.7V

ISL83384E transmitter outputs meet RS-562 levels (±3.7V),
at the full data rate, with V

as low as 2.7V. RS-562 levels

CC

typically ensure interoperability with RS-232 devices.

Po wer Supply Decoupling

In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple V
capacitor of the same value as the charge-p ump capacitor C
Connect the bypass capacitor as close as possible to the IC.

to ground with a

CC

1

High Data Rates

The ISL83384E maintains the RS-232 ±5V minimum
transmitter output voltages even at high data rates. Figure 6
details a transmitter loopback test circuit, and Figure 7
illustrates the loopback test result at 120Kbps. For this test,
all transmitters were simultaneously driving RS-232 loads in
parallel with 1000pF, at 120Kbps. Figure 8 shows the
loopback results for a single transmitter driving 1000pF and
an RS-232 load at 250Kbps. The static transmitter was also
loaded with an RS-232 receiver.

V

CC

0.1µF

+

C

1

+

C

2

.

V

CC

C1+

C1-

C2+

C2-

T

IN

R

OUT

SHDN

+

V

CC

ISL83384E

T

OUT

V+

V-

R

IN

5K

+

C

3

C

4

+

1000pF

Transmitter Outputs when Exiting
Powerdown

Figure 5 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.

5V/DIV

2V/DIV

FIGURE 5. TRANSMITTER OUTPUTS WHEN EXITING

SHDN

T1

T2

VCC = +3.3V
C1 - C4 = 0.1µF

TIME (20µs/DIV)

POWERDOWN

FIGURE 6. TRANSMITTER LOOPBACK TEST CIRCUIT

5V/DIV

T1

IN

T1

OUT

R1

OUT

VCC = +3.3V
C1 - C4 = 0.1µF

5µs/DIV

FIGURE 7. LOOPBACK TEST AT 120Kbps

6

FN6017.3

March 15, 2005

ISL83384E

www.BDTIC.com/Intersil

5V/DIV

T1

IN

T1

OUT

R1

OUT

VCC = +3.3V
C1 - C4 = 0.1µF

2µs/DIV

FIGURE 8. LOOPBACK TEST AT 250Kbps

Interconnection with 3V and 5V Logic

The ISL83384E directly interfaces with 5V CMOS and TTL
logic families. Nevertheless, with the device at 3.3V, and the
logic supply at 5V, AC, HC, and CD4000 outputs can drive
ISL83384E inputs, but ISL83384E outputs do not reach the
minimum V

for these logic families. See Table 3 for more

IH

information.

TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS

SUPPLY VOLTAGES

SYSTEM

POWER-SUPPLY

VOLTAGE

(V)

3.3 3.3 Compatible with all CMOS

5 5 Compatible with all TTL and

5 3.3 Compatible with ACT and HCT

V

CC

SUPPLY

VOLTAGE

(V) COMPATIBILITY

families.

CMOS logic families.

CMOS, and with TTL.

ISL83384E outputs are

incompatible with AC, HC, and
CD4000 CMOS inputs.

±15kV ESD Protection

All pins on ISL83XXX devices include ESD protection
structures, but the ISL83384E incorporates advanced
structures which allow the RS-232 pins (transmitter outputs
and receiver inputs) to survive ESD events up to ±15kV. The
RS-232 pins are particularly vulnerable to ESD damage
because they typically connect to an exposed port on the
exterior of the finished product. Simply touching the port
pins, or connecting a cable, can cause an ESD event that
might destroy unprotected ICs. These ne w ESD structures
protect the device whether or not it is powered up, protect
without allowing any latchup mechanism to activate, and
don’t interfere with RS-232 signals as large as ±25V.

Human Body Model (HBM) Testing

As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5kΩ current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an IC’s ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.

IEC16000-4-2 Testing

The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device’s RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-232 port.

AIR-GAP DISCHARGE TEST METHOD

For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
±15kV air-gap discharges.

CONTACT DISCHARGE TEST METHOD

During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing de vices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.

7

FN6017.3

March 15, 2005

ISL83384E

www.BDTIC.com/Intersil

Typical Performance Curves V

6.0

4.0

2.0
1 TRANSMITTER AT 250Kbps
1 TRANSMITTER AT 30Kbps

0

-2.0

-4.0

TRANSMITTER OUTPUT VOLTAGE (V)

-6.0
1000 2000 3000 4000 50000

LOAD CAPACITANCE (pF)

= 3.3V, TA = 25°C

CC

FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD

CAPACITANCE

45

40
35

30

25

20

15

SUPPLY CURRENT (mA)

10

5
0

0 1000 2000 3000 4000 5000

LOAD CAPACITANCE (pF)

250Kbps

120Kbps

20Kbps

V

V

OUT

OUT

25

+

20

15

-SLEW

SLEW RATE (V/µs)

-

10

5

0 1000 2000 3000 4000 5000

+SLEW

LOAD CAPACITANCE (pF)

FIGURE 10. SLEW RATE vs LOAD CAPACITANCE

3.5

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)

NO LOAD
ALL OUTPUTS STATIC

FIGURE 11. SUPPLY CURRENT vs LOAD CAPACIT ANCE

FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE

WHEN TRANSMITTING DATA

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP)

GND

TRANSISTOR COUNT

338

PROCESS

Si Gate CMOS

8

FN6017.3

March 15, 2005

ISL83384E

www.BDTIC.com/Intersil

Shrink Small Outline Plastic Packages (SSOP)

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) B

H

α

e

B

0.25(0.010) C AMB

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.20mm (0.0078 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In­terlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.

10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.

M

A1

0.10(0.004)

S

GAUGE

PLANE

M

0.25

0.010

A2

M

L

M20.209 (JEDEC MO-150-AE ISSUE B)

20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.068 0.078 1.73 1.99
A1 0.002 0.008’ 0.05 0.21
A2 0.066 0.070’ 1.68 1.78

B 0.010’ 0.015 0.25 0.38 9

C 0.004 0.008 0.09 0.20’
D 0.278 0.289 7.07 7.33 3

E 0.205 0.212 5.20’ 5.38 4

e 0.026 BSC 0.65 BSC

C

H 0.301 0.311 7.65 7.90’

L 0.025 0.037 0.63 0.95 6

N20 207

α

0 deg. 8 deg. 0 deg. 8 deg.

NOTESMIN MAX MIN MAX

Rev. 3 11/02

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

9

FN6017.3

March 15, 2005