Datasheet ISL8104 Datasheet (intersil)

Page 1

ISL8104

Data Sheet November 10, 2006 FN9257.1

8V to 14V, Single-Phase Synchronous Buck Pulse-Width Modulation (PWM) Controller With Integrated Gate Drivers

The ISL8104 is a 8V to 14V synchronous PWM controller with integrated MOSFET drivers. The controller features the ability to safely start-up into prebiased output loads and provides protection against overcurrent fault events. Overcurrent protection is implemented using top-side MOSFET r

sensing, eliminating the need for a current

DS(ON)

sensing resistor. The ISL8104 employs voltage-mode control with dual-edge

modulation to achieve fast transient response. The operating frequency is adjustable from 50kHz to 1.5MHz with full (0% to 100%) PWM duty cycle capability. The error amplifier features a 15MHz (typ) gain-bandwidth product and 6V/µs slew rate enabling high converter bandwidth.

The output voltage of the converter can be regulated to as low as 0.597V with a tolerance of ±1.0% over the commercial temperature range (0°C to +70°C), and ±1.5% over industrial temperature range (-40°C to +85°C). Provided in the QFN package, a SS pin and REFIN pin enable supply sequencing and voltage tracking functionality.

Pinouts

ISL8104 (16 LD QFN)

TOP VIEW

Features

• +8V ±5% to +14V ±10% Bias Voltage Range

- 1.5V to 15.4V Input Voltage Range

• 0.597V Internal Reference Voltage

- ±1.0% Over the Commercial Temperature Ran g e

- ±1.5% Over the Industrial Temperature Range

• Voltage-Mode PWM Control with Dual-Edge Modulation

• 14V High Speed N-Channel MOSFET Gate Drivers

- 2.0A Source/3A Sink at 14V Bottom-Side Gate Drive

- 1.25A Source/2A Sink at 14V Top-Side Gate Drive

• Fast Transient Response

- 15MHz (typ) Gain-Bandwidth Error Amplifier with 6V/µs slew rate

- Full 0% to 100% Duty Cycle Support

• Programmable Operating Frequency from 50kHz to

1.5MHz

• Lossless Programmable Overcurrent Protecti on

- Top-Side MOSFET’s r

DS(ON)

Sensing

- ~120ns Blanking Time

• Sourcing and Sinking Current Capability

• Support for Start-Up into Prebiased Loads

• Soft-Start Done and an External Reference Pin for Tracking Applications are Available in the QFN Package

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

TSOC

SSDONE

COMP

REFIN

ISL8104 (14 LD NARROW SOIC)

FSET

TSOC

COMP

GND

FSET

1516 14 13

6578

GND

TOP VIEW

VCC

TGATE

PVCC

BGATE

PGND

BOOT

VCC

PVCC

BGATE

PGND

BOOT

TGATE

• Test and Measurement Instruments

• Distributed DC/DC Power Architecture

• Industrial Applications

• Telecom/Datacom Applica ti on s

Ordering Information

PART #

(Note)

ISL8104CBZ 8104CBZ 0 to +70 14 Ld SOIC M14.15 ISL8104IBZ 8104IBZ -40 to +85 14 Ld SOIC M14.15 ISL8104CRZ 8104CRZ 0 to +70 16 Ld 4x4 QFN L16.4x4 ISL8104IRZ 8104IRZ -40 to +85 16 Ld 4x4 QFN L16.4x4 ISL8104EVAL1Z Evaluation Board ISL8104EVAL2Z Evaluation Board *Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

All other trademarks mentioned are the property of their respective owners.

PART

MARKING

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

Page 2

Block Diagram

SSDONE

(QFN ONLY)

30μA

VCC

INTERNAL

REGULATOR

POWER-ON

RESET (POR)

SOFT-START

AND

FAULT LOGIC

TSOC

200μA

BOOT

SOURCE OCP

TGATE

ISL8104

GATE

FSET

6μA

REFERENCE V

= 0.597 V

REF

OSCILLATOR

CONTROL

LOGIC

PWM

PVCC

REFIN

(QFN ONL Y)

GND

November 10, 2006

FN9257.1

BGATE

PGND

COMP

Page 3

ISL8104

Typical Application with Single Power Supply

+8V to +14V

FILTER

BOOT

BIN

HFIN

VCC

PVCC

BOOT

TSOC

SSDONE

(QFN ONLY)

FSET

REFIN

ISL8104

FSET

TSOC

TGATE LX

BGATE

PGND

COMP

GND

TSOC

Typical Application with Separated Power Supplies

+8V to +14V

FILTER

SSDONE

(QFN ONLY)

REFIN

(QFN ONLY)

VCC

PVCC

BOOT

TSOC

TGATE LX

BOOT

OUT

HFOUT

BOUT

OUT

+1.5V to +15.4V

HFIN

BOOT

BIN

OUT

FSET

ISL8104

FSET

BGATE

PGND

COMP

GND

HFOUT

BOUT

November 10, 2006

FN9257.1

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ISL8104

Absolute Maximum Ratings Thermal Information

Supply Voltage, V Enable Voltage, V Soft-start Done Voltage, V TSOC Voltage, V BOOT Voltage, V LX Voltage, V

PVCC,VVCC

. . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +16V

TSOC BOOT

. . . . . . . . . . . . . . . . V

. . . . . . . . . . . . . .GND - 0.3V to +16V

SSDONE

. . . . . . . . . .GND - 0.3V to +16V

. . . . . . . . . . . . . . . . . . . .GND - 0.3V to +16V

. . . . . . . . . . . . . . . . . . .GND - 0.3V to +36V

BOOT

- 16V to V

BOOT

+ 0.3V

All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5.0V

Thermal Resistance (Typical) θ

SOIC Package (Note 1) . . . . . . . . . . . . 95 N/A

QFN Package (Notes 2, 3). . . . . . . . . . 47 8.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(SOIC - Lead tips only)

(°C/W) θJC (°C/W)

Operating Conditions

Supply Voltage, V Supply Voltage, V Boot to Phase Voltage, V

. . . . . . . . . . . . . . . . .+8V ±5% to +14V ±10%

VCC

. . . . . . . . . . . . . . . .+8V ±5% to +14V ±10%

PVCC

BOOT

- VLX . . . . . . . . . . . . . . . . . <V

PVCC

ESD Ratings

ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Ambient Temperature Range, ISL8104C. . . . . . . . . . . 0°C to +70°C

Ambient Temperature Range, ISL8104I. . . . . . . . . . .-40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

2. θ

Tech Brief TB379.

3. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

4. Parameters are Guaranteed by Design.

Electrical Specifications Recommended Operating Conditions, unless otherwise noted specifications in bold are valid for process,

temperature, and line operating conditions.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SUPPLY CURRENT

Shutdown Supply V Shutdown Supply V

CC PVCC

POWER-ON RESET

CC/VPVCC

Rising Threshold 6.55 7.10 7.55 V

Hysteresis 170 250 500 mV TSOC Rising Threshold 0.70 0.73 0.75 V TSOC Hysteresis 180 200 220 mV Enable - Rising Threshold 1.4 1.5 1.60 V Enable - Hysteresis 175 250 325 mV

REFERENCE

Reference Voltage T

System Accuracy T

REFIN Current Source (QFN Only) -4 -6 -8 μA REFIN Threshold (QFN Only) 2.10 - 3.50 V REFIN Offset (QFN Only) -3 - 3 mV

OSCILLATOR

Trim Test Frequency R Total Variation (Note 4) 8kΩ < R Ramp Amplitude ΔV

VCC

PVCC

OSC

SS/EN = 0V 3.5 6.1 8.5 mA SS/EN = 0V 0.30 0.5 0.75 mA

= 0°C to +70°C 0.591 0.597 0.603 V

= -40°C to +85°C 0.588 0.597 0.606 V

= 0°C to +70°C -1.0 - 1.0 %

= -40°C to +85°C -1.5 - 1.5 %

= OPEN V

FSET

to GND < 200kΩ - ±15 - %

FSET

= OPEN 1.7 1.9 2.15 V

FSET

= 12 175 200 220 kHz

VCC

P-P

FN9257.1

November 10, 2006

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ISL8104

Electrical Specifications Recommended Operating Conditions, unless otherwise noted specifications in bold are valid for process,

temperature, and line operating conditions. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Ramp bottom (Note 4) -1- V

ERROR AMPLIFIER

DC Gain (Note 4) R Gain-Bandwidth Product (Note 4) GBWP R Slew Rate (Note 4) SR R COMP Source Current (Note 4) I COMP Sink Current (Note 4) I

GATE DRIVERS

Top-side Drive Source Current (Note 4) I Top-side Drive Source Impedance R Top-side Drive Sink Current (Note 4) I Top-side Drive Sink Impedance R Bottom-side Drive Source Current (Note 4) I Bottom-side Drive Source Impedance R Bottom-side Drive Sink Current (Note 4) I Bottom-side Drive Sink Impedance R

PROTECTION

TSOC Current I

TSOC Measurement Offset (Note 4) OCP

SOFT-START

Soft-start Current I SSDONE Low Output Voltage

(QFN ONLY)

COMPSRC COMPSNK

T_SOURCEVBOOT

T_SOURCE

T_SINK

B_SOURCEVPVCC

B_SOURCE

B_SINK

TSOC

OFFSET

= 10kΩ, CL= 100pF - 88 - dB

= 10kΩ, CL= 100pF - 15 - MHz

= 10kΩ, CL= 100pF - 6 - V/μs

-2-mA

- VLX = 14V, 3nF Load - 1.25 - A 90mA Source Current - 2.0 - Ω V

- VLX = 14V, 3nF Load - 2 - A

BOOT

90mA Source Current - 1.3 - Ω

= 14V, 3nF Load - 2 - A 90mA Source Current - 1.3 - Ω V

= 14V, 3nF Load - 3 - A

PVCC

90mA Source Current - 0.94 - Ω

TJ = 0°C to +70°C 180 200 220 μA

= -40°C to +85°C 176 200 224 μA

TSOC = 1.5V to 15.4V - ±10 - mV

22 30 38 μA

= 2mA - - 0.30 V

SSDONE

Functional Pin Description (QFN/SOIC)

SS (Pin 1/3)

Connect a capacitor from this pin to ground. This capacitor, along with an internal 30μA current source, sets the soft-start interval of the converter.

COMP (Pin 2/4) and FB (Pin 3/5)

COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter.

EN (Pin 4/6)

This pin is a TTL compatible input. Pull this pin below 0.8V to disable the converter. In shutdown the soft-start pin is discharged and the TGATE and BGATE pins are held low.

REFIN (QFN ONLY Pin 5)

Upon enable if REFIN is less than 2.2V, the external reference pin is used as the control reference instead of the internal 0.597V reference. An internal 6

μA pull up to 5V is

provided for disabling this functionality.

GND (Pin 6/7)

Signal ground for the IC. All voltage levels are measured with respect to this pin.

LX (Pin 7/8)

This pin connects to the source of the top-side MOSFET and the drain of the bottom-side MOSFET. This pin represents the return path for the top-side gate driver. During normal switching, this pin is used for top-side current sensing.

TGATE (Pin 8/9)

Connect TGATE to the top-side MOSFET gate. This pin provides the gate drive for the top-side MOSFET.

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November 10, 2006

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BOOT (Pin 9/10)

This pin provides bias to the top-side MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET.

PGND (Pin 10/11)

This is the power ground connection. Tie the bottom-side MOSFET source and board ground to this pin.

BGATE (Pin 11/12)

Connect BGATE to the bottom-side MOSFET gate. This pin provides the gate drive for the bottom-side MOSFET.

PVCC (Pin 12/13)

Provide an 8V to 14V bias supply for the bottom-si d e ga te drive to this pin. This pin should be bypassed with a capacitor to PGND.

ISL8104

(mA)

PVCC+VCC

100 200 300 400 500 600 700 800 900 1000

FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

= 3300pF

GATE

SWITCHING FREQUENCY (kHz)

GATE

= 1000pF

= 10pF

VCC (Pin 13/14)

Provide an 8V to 14V bias supply for the chip to this pin. The pin should be bypassed with a capacitor to GND.

FSET (Pin 14/1)

This pin provides oscillator switching frequency adjustment. By placing a resistor (R switching frequency is set from between 200kHz and

1.5MHz according to the following equation:

FSET

⎛⎞

kΩ[]

⎝⎠

6500

-------------------------------------------------------

kHz[]200 kHz[]–

Alternately ISL8104’s switching frequency can be lowered from 200kHz to 50kHz by connecting the FSET pin with a resistor to VCC according to the following equation:

55000

⎛⎞

FSET

1000

)

RESISTANCE (k

100

-------------------------------------------------------

kΩ[]

⎝⎠

200 kHz[]F

FSET

10 100 1000

SWITCHING FREQUENCY (kHz)

FIGURE 1. R

FSET

) from this pin to GND, the

FSET

1.3–

kΩ≈

FSET

70+

kΩ≈

kHz[]–

PULLUP

TO VCC

PULLDOWN

FSET

TO GND

RESISTANCE vs. FREQUENCY

FSET

to GND)

to VCC)

TSOC (Pin 15/2)

The current limit is programmed by connecting this pin with a resistor and capacitor to the drain of the top-side MOSEFT. A 200

μA current source develops a voltage across the

resistor which is then compared with the voltage developed across the top-side MOSFET. A blanking period of 120ns is provided for noise immunity.

SSDONE (QFN ONLY Pin 16)

Provides an open drain signal at the end of soft-start.

Functional Description

Initialization

The ISL8104 automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the bias voltage at the VCC pin and the driver input on the PVCC pin. When the voltages at VCC and PVCC exceed their rising POR thresholds, a 30μA current source driving the SS pin is enabled. Upon the SS pin exceeding 1V, the ISL8104 begins ramping the non-inverting input of the error amplifier from GND to the System Reference. During initialization the MOSFET drivers pull TGATE to LX and BGATE to PGND.

Soft-Start

During soft-start, an internal 30μA current source charges the external capacitor (C ISL8104 is utilizing the internal reference, then as the SS pin’ s voltage ramps from 1V to 3V, the soft-start function scales the reference input (positive terminal of error amp) from GND to VREF (0.597V nominal). If the ISL8104 is utilizing an externally supplied reference, when the voltage on the SS pin reaches 1V , the internal reference input (into of the error amp) ramps from GND to the externally supplied reference at the same rate as the voltage on the SS pin. Figure 3 shows a typical soft-start interval. The rise time of the output volt age is, therefore, dependent upon the value of the soft-start

) on the SS pin up to ~4V. If the

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ISL8104

capacitor , CSS. If the internal reference is used, then the soft-start capacit ance value can be calculated through:

30μ AtSS⋅

----------------------------

If an external reference is used, then the soft-start capacitance can be calculated through:

30μ AtSS⋅

----------------------------

REFEXT

OUT

FIGURE 3. TYPICAL SOFT-START INTERVAL

Prebiased Load Start-up

Drivers are held in tri-state (TGATE pulled to LX, BGATE pulled to PGND) at the beginning of a soft-start cycle until two PWM pulses are detected. The bottom-side MOSFET is turned on first to provide for charging of the bootstrap capacitor. This method of driver activation provides support for start-up into prebiased loads by not activating the drivers until the control loop has entered its linear region, thereby substantially reducing output transients that would otherwise occur had the drivers been activated at the beginning of the soft-start cycle.

clock cycles an automatic boot cap refresh circuit will activate turning on BGATE for approximately 1/2 of a clock cycle.

Overcurrent Protection

The OCP function is enabled with the drivers at start-up. OCP is implemented via a resistor (R (C side MOSEFT. An internal 200 voltage across R

) connecting the TSOC pin and the drain of the top-

TSOC

which is then compared with the

TSOC

mA current source develops a

voltage developed across the top-side MOSFET at turn on as measured at the LX pin. When the voltage drop across the MOSFET exceeds the voltage drop across the resistor, a sourcing OCP event occurs. C R

to smooth the voltage across R

TSOC

of switching noise on the input bus. A 120ns blanking period is used to reduce the current

sampling error due to leading-edge switching noise. An additional simultaneous 120ns low pass filter is used to further reduce measurement error due to noise.

OCP faults cause the regulator to disable (top- and bottom-side drives disabled, SSDONE pulled low, soft-start capacitor discharged) itself for a fixed period of time, after which a normal soft-start sequence is initiated. If the voltage on the SS pin is already at 4V and an OCP is detected, a 30μA current sink is immediately applied to the SS pin. If an OCP is detected during soft-start, the 30μA current sink will not be applied until the voltage on the SS pin has reached 4V . This current sink discharges the C fashion. Once the voltage on the SS pin has reached approximately 0V , the normal soft-start sequence is initiated. If the fault is still present on the subsequent restart, the ISL8104 will repeat this process in a hiccup mode. Figure 4 shows a typical reaction to a repeated overcurrent condition that places the regulator in a hiccup mode. If the regulator is

SSDONE

) and a capacitor

TSOC

is placed in parallel with

in the presence

TSOC

capacitor in a linear

SSDONE

Soft-start done is only available in the 16 Lead QFN packaging option of the ISL8104. When the sof t-st art pin reaches 4V, an open drain signal is provided to support sequencing requirements. SSDONE is deasserted by disabling of the part, including pulling SS low, and by POR and OCP events.

Oscillator

The oscillator is a triangular waveform, providing for leading and falling edge modulation. The peak to peak of the ramp amplitude is set at 1.9V and varies as a function of frequency. At 50kHz the peak to peak amplitude is approximately 1.8V while at 1.5M Hz it is approximately 2.2V . In the event the regulator operates at 100% duty cycle for 64

OCP

LOAD

HICCUP

FIGURE 4. TYPICAL OVERCURRENT PROTECTION

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ISL8104

repeatedly tripping overcurrent, the hiccup period can be approximated by the following formula:

24VC

⋅⋅

30μ A

DS(ON)

HICCUP

------------------------------- -

The OCP trip point varies mainly due to MOSFET r variations and layout noise concerns. To avoid overcurrent tripping in the normal operating load range, find the R

OCSET

resistor from the following equations with:

1. The maximum r

at the highest junction

DS(ON)

temperature;

2. The minimum I

from the specification table;

TSOC

Determine the overcurrent trip point greater than the maximum output continuous current at maximum inductor ripple current.

Simple OCP Equation

TSOC

OC _SOURCE

--------------------------------------------------------------- -

200μ A

r•

DS ON()

Detailed OCP Equation

IΔ

---- -

•

TSOCNT

OUT

r•

DS ON()

TSOC

ΔI =

⎛⎞

OC _SOURCE

⎝⎠

--------------------------------------------------------------------------------- -

NUMBER OF TOP-SIDE MOSFETs=

- V

---------------------------------

FSWL

•

Regulator Switching Frequency=

OUT

--------------- -

•

High Speed MOSFET Gate Driver

The integrated driver has the same drive capability and feature as the Intersil’s 12V gate driver, ISL6612. The PWM tri-state feature helps prevent a negative transient on the

output voltage when the output is being shut down. This eliminates the Schottky diode that is used in some systems for protecting the loads from reversed-output-voltage damage. See the ISL6612 data sheet for specification parameters that are not defined in the current ISL8104

electrical specifications table.

Internal Reference and System Accuracy

The Internal Reference is set to 0.597V. The tota l DC system accuracy of the system is to be within 1.5% over the industrial temperature range. System Accuracy includes Error Amplifier offset, and Reference Error. The use of REFIN may add up to 3mV of offset error into the system (as the Error Amplifier offset is trimmed out via the internal System reference.)

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding.

A multi-layer printed circuit board is recommended. Figure 5 shows the critical components of the converter. Note that

+14V

BP_PVCC

BP_VCC

VIN

OUT

LOAD

ISL8104

GND

VCC

PVCC

TGATE

BOOT

BGATE

PGND

Reference Input

The REFIN pin allows the user to bypass the internal 0.597V reference with an external reference. If REFIN is NOT above ~2.2V, the external reference pin is used as the control reference instead of the internal 0.597V reference. When not using the external reference option the REFIN pin should be left floating. An internal 6μA pull-up keeps this REFIN pin above 2.2V in this situation.

KEY

TRACE SIZED FOR 3A PEAK CURRENT

SHORT TRACE, MINIMUM IMPEDANCE

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 5. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

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ISL8104

capacitors CIN and C

could each represent numerous

OUT

physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the LX terminals to the output inductor short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the LX nodes. Use the remaining printed circuit layers for small signal wiring.

Locate the ISL8104 within 2 to 3 inches of the MOSFETs, Q1 and Q2 (1 inch or less for 500kHz or higher operation). The circuit traces for the MOSFET s’ gate and source connections from the ISL8104 must be sized to handle up to 3A peak current. Minimize any leakage current paths on the SS pin and locate the capacitor, C internal current source is only 30μA. Provide local V

close to the SS pin as the

decoupling between VCC and GND pins. Locate the capacitor , C

as close as practical to the BOOT pin and

BOOT

the phase node.

Compensating the Converter

This section highlights the design consideration for a voltagemode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended (see Figure 6).

FIGURE 6. COMPENSATION CONFIGURATION FOR THE

ISL8104 CIRCUIT

Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage is regulated to the reference voltage level. The error amplifier output is compared with the oscillator triangle wave to provide a pulse-width modulated wave with an amplitude of V

at the LX node. The PWM wave is smoothed by the

output filter. The output filter capacitor bank’s equivalent series resistance is represented by the series resistor ESR.

The modulator transfer function is the small-signal transfer function of V

OUT/VCOMP

DC gain and shaped by the output filter, with a double pole break frequency at F

VOUT

COMP

ISL8104

. This function is dominated by a

and a zero at FCE. For the purpose

of this analysis, L and DCR represent the output inductance and its DCR, while C and ESR represents the total output capacitance and its equivalent series resistance.

---------------------------

FLC

2π LC⋅⋅

COMP

OSCILLATOR

PWM

CIRCUIT

HALF-BRIDGE

FIGURE 7. VOLT AGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

E/A

OSC

DRIVE

FCE

VREF

---------------------------------

2π C ESR⋅⋅

GND

TGATE

BGATE

EXTERNAL CIRCUITISL8104

OUT

DCR

ESR

The compensation network consists of the error amplifier (internal to the ISL8104) and the external R

1-R3

, C1-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F

; typically 0.1 to 0.3 of FSW) and adequate

phase margin (better than 45 degrees). Phase margin is the difference between the closed loop phase at F

and 180°.

0dB

The equations that follow relate the compensation network’s poles, zeros and gain to the components (R and C

) in Figures 6 and 7. Use the following guidelines for

, R2, R3, C1, C2,

locating the poles and zeros of the compensation network:

1. Select a value for R value for R

for desired converter bandwidth (F0). If

(1kΩ to 10kΩ, typically). Calculate

setting the output voltage to be equal to the reference set voltage as shown in Figure 7, the design procedure can be followed as presented.

⋅⋅

OSCR1F0

----------------------------------------------

⋅⋅

MAXVINFLC

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ISL8104

As the ISL8104 supports 100% duty cycle, D

1. The ISL8104 uses a fixed ramp amplitude (V

MAX

equals

OSC

) of

1.9V, the above equation simplifies to:

1.9 R1F

⋅⋅

-------------------------------

2. Calculate C at 0.1 to 0.75 of F

⋅

INFLC

such that FZ1 is placed at a fraction of the FLC,

(to adjust, change the 0.5 factor below

to the desired number). The higher the quality factor of the output filter and/or the higher the ratio F

CE/FLC

, the lower

the FZ1 frequency (to maximize phase boost at FLC).

2π R

3. Calculate C

--------------------------------------------------------

2π R2C1FCE1–⋅⋅⋅

4. Calculate R

0.5 F

⋅⋅ ⋅

such that FP1 is placed at FCE.

such that FZ2 is placed at FLC. Calculate C3

-----------------------------------------------

such that FP2 is placed below FSW (typically, 0.3 to 1.0 times F

). FSW represents the switching frequency of

the regulator. Change the numerical factor (0.7) below to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter.

----------------------

------------

1–

-------------------------------------------------

2π R

0.7 F

⋅⋅ ⋅

It is recommended that a mathematical model be used to plot the loop response. Check the loop gain against the error amplifier’s open-loop gain. Verify phase margin results and adjust as necessary. The following equations describe the frequency response of the modulator (G compensation (G

------------------------------ -

f()

MOD

----------------------------------------------------

f()

sf() R

-------------------------------------------------------------------------------------------------------------------------

f() G

) and closed-loop response (GCL):

⋅

MAXVIN

OSC

1sf() R

-----------------------------------------------------------------------------------------------------------

⋅=

1sf() ESR DCR+()C⋅⋅s

⋅⋅+

2C1

1C1C2

1sf() R

⋅⋅+()1sf() R

3C3

f() GFBf()⋅=

MOD

+()⋅⋅

1sf() ESR C⋅⋅+

⋅=

+()C

⋅⋅+

1R3

⎛⎞

⋅

⎜⎟ ⎝⎠

where s f(), 2 π fj⋅⋅=

), feedback

MOD

C1C2⋅

⎛⎞

---------------------

⋅⋅+

⎜⎟

⎝⎠

1C2

f() LC⋅⋅++

COMPENSATION BREAK FREQUENCY EQUATIONS

------------------------------ -

2π R

-------------------------------------------------

2π R

⋅⋅

2C1

+()C

⋅⋅

1R3

---------------------------------------------

2π R

------------------------------ -

2π R

C1C2⋅

---------------------

⋅⋅

3C3

1C2

Figure 8 shows an asymptotic plot of the DC/DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the above guidelines should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at F amplifier. The closed loop gain, G

against the capabilities of the error

, is constructed on the

log-log graph of Figure 8 by adding the modulator gain, G

(in dB), to the feedback compensation gain, GFB (in

MOD

dB). This is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain.

MODULATOR GAIN

COMPENSATI ON GAIN

CLOSED LOOP GAIN

OPEN LOOP E/A GAIN

V⋅

MAX

OSC

MOD

FREQUENCY

----------------------------------log

GAIN

LOG

log

⎛⎞

------- -

⎝⎠

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. The mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. When designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, F

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current.

FN9257.1

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ISL8104

These requirements are generally met with a mix of capacitors and careful layout.

For applications that have transient load rates above 1A/ns, high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the ma nu facturer of the load on specific decoupling requirements.

Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:

OUT

--------------- -

•

OUT

ΔV

= ΔI x ESR

OUT

- V

--------------------------------

ΔI =

Fs x L

Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL8104 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output capacitance required.

The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:

LOI

TRAN

RISE

where: I

------------------------------- -

–

INVOUT

is the transient load current step, T

TRAN

FALL

response time to the application of load, and T

-------------------------------

OUT

TRAN

FALL

RISE

is the

response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2.

The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select a bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage, a voltage rating of 1.5 times greater is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current.

For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested.

MOSFET Selection/Considerations

The ISL8104 requires at least 2 N-Channel power MOSFETs. These should be selected based upon r gate supply requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss

DS(ON)

FN9257.1

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ISL8104

components; conduction loss and switching loss. At a 300kHz switching frequency, the conduction losses are the largest component of power dissipation for both the top-side and the bottom-side MOSFET s. These losses are distributed between the two MOSFETs according to duty factor (see the following equations). Only the top-side MOSFET exhibits switching losses, since the schottky rectifier clamps the switching node before the synchronous rectifier turns on.

top-side

bottom-side

= I

x r

DS(ON)

x r

DS(ON)

where: D is the duty cycle = V

x D +

x (1 - D)

Io x VIN x TSW x Fs

/ VIN,

TSW is the switching interval, and Fs is the switching frequency.

These equations assume linear voltage-current transitions and do not adequately model power loss due the reverserecovery of the bottom-side MOSFETs body diode. The gate-charge losses are dissipated by the ISL8104 and don't heat the MOSFETs. However, large gate-charge increa se s the switching interval, T

which increases the top-side

MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specification s. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.

Standard-gate MOSFETs are normally recommended for use with the ISL8104. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, top-side gate drive level, and the MOSFETs absolute gateto-source voltage rating determine whether logic-level MOSFETs are appropriate.

Figure 9 shows the top-side gate drive (BOOT pin) supplied by a bootstrap circuit from +14V. The boot capacitor , C

BOOT

develops a floating supply voltage referenced to the LX pin. This supply is refreshed each cycle to a voltage of +14V less the boot diode drop (V

) when the bottom-side MOSFET , Q2

turns on. A MOSFET can only be used for Q1 if the MOSFETs absolute gate-to-source voltage rating exceeds the maximum voltage applied to +14V. For Q2, a logic-level MOSFET can be used if its absolute gate-to-source voltage rating also exceeds the maximum voltage applied to +14V.

Figure 10 shows the top-side gate drive supplied by a direct connection to +14V. This option should only be used in converter systems where the main input voltage is +5VDC or less. The peak top-side gate-to-source voltage is approximately +14V less the input supply. For +5V main power and +14VDC for the bias, the gate-to-source voltage of Q1 is 9V. A logic-level MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to PVCC. This method reduces the number of

+14V

ISL8104

FIGURE 9. TOP-SIDE GATE DRIVE - BOOTSTRAP OPTION

GND

BOOT

TGATE

PVCC

BGATE

PGND

BOOT

+1.2V TO +14V

NOTE: V

≈ V

G-S

NOTE: V

G-S

≈ PVCC

- V

+14V

required external components, but does not provide for immunity to phase node ringing during turn on and may result in lower system efficiency.

+14V

ISL8104

FIGURE 10. TOP-SIDE GATE DRIVE - DIRECT VCC DRIVE

GND

OPTION

BOOT

TGATE

PVCC

BGATE

PGND

+14V

+5V OR LESS

NOTE:

G-S

NOTE: V

G-S

≈ V

≈ PVCC

- 5V

Schottky Selection

Rectifier D2 is a clamp that catches the negative inductor swing during the dead time between turning off the bottomside MOSFET and turning on the top-side MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the bottom-side MOSFET clamp the negative inductor swing, but efficiency could slightly decrease as a result. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage.

FN9257.1

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Page 13

Small Outline Plastic Packages (SOIC)

ISL8104

INDEX AREA

123

-A-

-B-

SEATING PLANE

-C-

0.25(0.010) BM M

h x 45

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

0.10(0.004)

M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.3367 0.3444 8.55 8.75 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N14 147

Rev. 0 12/93

NOTESMIN MAX MIN MAX

FN9257.1

November 10, 2006

Page 14

ISL8104

Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 -

A1 - - 0.05 -

A2 - - 1.00 9

A3 0.20 REF 9

b 0.23 0.28 0.35 5, 8

D 4.00 BSC -

D1 3.75 BSC 9

D2 1.95 2.10 2.25 7, 8

E 4.00 BSC -

E1 3.75 BSC 9

E2 1.95 2.10 2.25 7, 8

e 0.65 BSC -

k0.25 - - -

L 0.50 0.60 0.75 8

L1 - - 0.15 10

N162

Nd 4 3

Ne 4 3

P- -0.609 θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation.

10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.

NOTESMIN NOMINAL MAX

Rev. 5 5/04

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9257.1

November 10, 2006