Datasheet ISL6622B Datasheet (intersil)

Page 1

ISL6622B

Data Sheet March 19, 2009

VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers

The ISL6622B is a high frequency MOSFET driver designed to drive upper and lower power N-Channel MOSFETs in a synchronous rectified buck converter topology . The advanced PWM protocol of ISL6622B is specifically designed to work with Intersil VR11.1 controllers and combined with N-Channel MOSFETs, form a complete core-volt age regulator solution for ad va nc e d mi cr o pr oc e s sor s . When ISL6622B detects a PSI controller, it activates Diode Emulation (DE) operation; otherwise, it operates in normal Continuous Conduction Mode (CCM) PWM mode.

In the 8 Ld SOIC package, the ISL6622B drives the upper gate to 12V while the lower drive voltage is fixed at 5.75V. The 10 Ld DFN part offers more flexibility: the upper gate can be driven from 5V to 12V via the UVCC pin, while the lower gate has a resistor-selectable drive voltage of 5.75V, 6.75V, and

7.75V (typically). This provides the flexibility necessary to optimize applications involving trade-of fs betwe en gate charge and conduction losses.

To further enhance light load efficiency, the ISL6622B enables diode emulation operation during PSI allows for Discontinuous Conduction Mode (DCM) operation by detecting when the inductor current reaches zero and subsequently turning off the low side MOSFET to prevent it from sinking current.

An advanced adaptive shoot-through protection is integrated to prevent both the upper and lower MOSFETs from conducting simultaneously and to minimize dead time. The ISL6622B has a 20k gate-to-source resistor to prevent self turn-on due to high input bus dV/dt. This driver also has an overvoltage protection feature operational while VCC is below the POR threshold: the PHASE node is connected to the gate of the low side MOSFET (LGATE) via a 10k output voltage of the converter close to the gate threshold of the low side MOSFET, dependent on the current being shunted, which provides some protection to the load should the upper MOSFET(s) be shorted prior to start-up.

PWM protocol sent by an Intersil VR11.1

mode. This

Ω integrated high-side MOSFET

Ω resistor, limiting the

FN6602.1

Features

• Dual MOSFET Drives for Synchronous Rectified Bridge

• Advanced Adaptive Zero Shoot-Through Protection

• Integrated LDO with Selectable Lower Gate Drive Voltage for Light Load Efficiency Optimization

• 36V Internal Bootstrap Diode

• Advanced PWM Protocol (Patent Pending) to Support PSI Operation

• Diode Emulation for Enhanced Light Load Efficiency

• Bootstrap Capacitor Overcharging Prevention

• Supports High Switching Frequency

- 3A Sinking Current Capability

- Fast Rise/Fall Times and Low Propagation Delays

• Integrated UGATE-to-PHASE Resistor for Increased Upper MOSFET Input Bus High dV/dt Immunity

• Pre-POR Overvoltage Protection at Start-Up and Shutdown

• Dual Flat No-Lead (DFN) Package

- Near Chip-Scale Package Footprint; Improves PCB

Efficiency and Thinner in Profile

- Bottom Copper Pad for Enhanced Heat Sinking

• Pb-Free (RoHS Compliant)

Applications

• High Light-Load Efficiency Voltage Regulators

• Core Regulators for Advanced Microprocessors

• High Current DC/DC Converters

• High Frequency and High Efficiency VRM and VRD

Related Literature

• Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”

• Technical Brief TB417 “Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators” for Power Train Design, Layout Guidelines, and Feedback Compensation Design

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Page 2

ISL6622B

Ordering Information

PART NUMBER

(Note)

ISL6622BCBZ* 6622B CBZ 0 to +70 8 Ld SOIC M8.15 ISL6622BCRZ* 622B 0 to +70 10 Ld 3x3 DF N L10.3x3 ISL6622BIBZ* 6622B IBZ -40 ISL6622BIRZ* 22BI -40 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

TEMP. RANGE

(°C)

to +85 8 Ld SOIC M8.15 to +85 10 Ld 3x 3 D FN L10.3x3

PACKAGE

(Pb-free)

PKG.

DWG. #

Pinouts

UGATE

BOOT

PWM

GND

Block Diagrams

ISL6622B

(8 LD SOIC)

TOP VIEW

1 2 3 4

UVCC

GD_SEL

VCC

PWM

ISL6622B

(10 LD 3x3 DFN)

TOP VIEW

PHASE 7 6 5

VCC

LVCC

LGATE

UGATE

BOOT

GD_SEL

3 4

PWM

GND LGATE

PAD

9 8 7 6

PHASE VCC UVCC LVCC

ISL6622B

BOOT

UGATE

PHASE

LVCC

LGATE

+5V

11.2k

9.6k

LDO

POR/

CONTROL

LOGIC

LVCC

SHOOT-

THROUGH

PROTECTION

20k

10k

GND

LVCC = 5.75V (TYPICALL Y) at 50mA for SOIC

UVCC = VCC for SOIC

March 19, 2009

Page 3

Typical Application Circuit

ISL6622B

VTT

VR_RDY

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

PSI

VR_FAN VR_HOT

VIN

+5V

VDIFF VSEN

RGND

EN_VTT

EN_PWR

GND

IMON

TCOMP

+5V

COMPFB

PWM1

ISEN1-

ISEN1+

ISL6334

PWM2

ISEN2-

ISEN2+

PWM3

ISEN3-

ISEN3+

PWM4

ISEN4-

ISEN4+

OFS FS SS

DACVCC REF

+12V

LVCC

VCC

PWM

PVCC

VCC

PWM

PVCC

VCC

PWM

PVCC

ISL6622B

DRIVER

ISL6612 DRIVER

BOOT

UGATE PHASE

LGATE

GND

BOOT

UGATE PHASE

LGATE

GND

BOOT

UGATE PHASE

LGATE

GND

BOOT

VIN

µP

LOAD

VIN

NTC

VCC

ISL6612 DRIVER

PWM

UGATE PHASE

LGATE

GND

March 19, 2009

Page 4

ISL6622B

Absolute Maximum Ratings Thermal Information

Supply Voltage (VCC, UVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

BOOT Voltage (V Input Voltage (V

UGATE. . . . . . . . . . . . . . . . . . . V

LGATE. . . . . . . . . . . . . . . . . . GND - 0.3V

BOOT-GND

PWM

- 3.5V (<100ns Pulse Width, 2µJ) to V

PHASE

GND - 5V (<100ns Pulse Width, 2µJ) to V

PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V

GND - 8V (<400ns, 20µJ) to 30V (<200ns, V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V

) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V

PHASE

- 0.3VDC to V

to V

LVCCLVCC LVCCLVCC

BOOT-GND

BOOT BOOT

to 15V

+ 0.3V + 0.3V + 0.3V + 0.3V

<36V)

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

2. θ

Tech Brief TB379.

3. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

4. Limits should be considered typical and are not production tested.

Electrical Specifications Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,

unless otherwise specified. Temperature limits established by characterization and are not production tested.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

No Load Switching Supply Current I

Standby Supply Current I

VCC

UVCC

VCC

UVCC

ISL6622BCBZ and ISL6622BIBZ, f

PWM

ISL6622BCRZ and ISL6622BIRZ, f

PWM

ISL6622BCBZ and ISL6622BIBZ, PWM Transition from 0V to 2.5V

ISL6622BCRZ and ISL6622BIRZ, PWM Transition from 0V to 2.5V

POWER-ON RESET

VCC Rising Threshold 6.25 6.45 6.70 V VCC Falling Threshold 4.8 5.0 5.25 V LVCC Rising Threshold (Note 4) -4.4- V LVCC Falling Threshold (Note 4) -3.4- V

PWM INPUT (See “TIMING DIAGRAM” on page 6)

Input Current I

PWM

PWM Rising Threshold VCC = 12V - 3.4 - V PWM Falling Threshold VCC = 12V - 1.6 - V Tristate Lower Gate Falling Threshold VCC = 12V - 1.60 - V Tristate Lower Gate Rising Threshold VCC = 12V - 1.1 - V Tristate Upper Gate Rising Threshold VCC = 12V - 3.2 - V Tristate Upper Gate Falling Threshold VCC = 12V - 2.8 - V

Thermal Resistance θ

(°C/W) θJC (°C/W)

SOIC Package (Note 1) . . . . . . . . . . . . 100 N/A

DFN Package (Notes 2, 3). . . . . . . . . . 48 7

Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Ambient Temperature Range

ISL6622BIBZ, ISL6622BIRZ . . . . . . . . . . . . . . . . .-40°C to +85°C

ISL6622BCBZ, ISL6622BCRZ. . . . . . . . . . . . . . . . . 0°C to +70°C

Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V

Supply Voltage Range, UVCC. . . . . . . . . . . . . . . . . .4.75V to 13.2V

-8.6-mA

= 300kHz, V

= 5V - 500 - µA

= 0V - -430 - µA

VCC

= 12V

-6.6-mA

-2-mA

-5.1-mA

-5.0-mA

-0.07- mA

March 19, 2009

Page 5

ISL6622B

Electrical Specifications Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,

unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

UGATE Rise Time t LGATE Rise Time t UGATE Fall Time t LGATE Fall Time t UGATE Turn-On Propagation Delay (Note 4) t LGATE Turn-On Propagation Delay (Note 4) t UGATE Turn-Off Propagation Delay (Note 4) t LGATE Turn-Off Propagation Delay (Note 4) t Tristate Low Delay t Minimum LGATE ON-T ime During PSI

Operation t

LG_ON_DMVVCC

OUTPUT (Note 4)

Upper Drive Source Current I Upper Drive Source Impedance R Upper Drive Sink Current I

U_SOURCEVVCC

U_SOURCE

U_SINKVVCC

Upper Drive Sink Impedance R Lower Drive Source Current I Lower Drive Source Impedance R Lower Drive Sink Current I

L_SOURCEVVCC

L_SOURCE

L_SINK

Lower Drive Sink Impedance R

RU RL FU

FL PDHU PDHL PDLU PDLL TSLD

U_SINK

L_SINK

= 12V, 3nF Load, 10% to 90% - 26 - ns

VCC

= 12V, 3nF Load, 10% to 90% - 18 - ns

VCC

= 12V, 3nF Load, 90% to 10% - 18 - ns

VCC

= 12V, 3nF Load, 90% to 10% - 12 - ns

VCC

= 12V, 3nF Load, Adaptive - 20 - ns

VCC

= 12V, 3nF Load, Adaptive - 10 - ns

VCC

= 12V, 3nF Load - 10 - ns

VCC

= 12V, 3nF Load - 10 - ns

VCC

= 12V - 60 - ns

VCC

= 12V 230 330 450 ns

= 12V, 3nF Load - 1.25 - A

20mA Source Current - 2.0 - Ω

= 12V, 3nF Load - 2 - A

20mA Sink Current - 1.35 - Ω

= 12V, 3nF Load - 2 - A 20mA Source Current - 1.35 - Ω V

= 12V, 3nF Load - 3 - A

VCC

20mA Sink Current - 0.90 - Ω

Functional Pin Description

PACKAGE PIN #

1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET. 2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the

- 3 GD_SEL This pin sets the LG drive voltage.

3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct sta tes during operation ,

4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver. 5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET. 6 7 L VCC This pin provides power for the LGA TE drive. Place a high quality low ESR ceramic capacitor from this pin to GND.

- 8 UVCC This pin supplies power to the upper gate drive. Its operating range is +5V to +12V. Place a high quality low ESR

7 9 VCC Connect this pin to 12V bias supply . This pin supplies power to the upper gate in the SOIC and to the LDO for the

8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides

- 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.

SYMBOL FUNCTIONSOIC DFN

PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap Device” on page 7 for guidance in choosing the capacitor value.

see “Advanced PWM Protocol (Patent Pending)” on page 6 for further details. Connect this pin to the PWM output of the controller.

ceramic capacitor from this pin to GND.

lower gate drive. Place a high quality low ESR ceramic capacitor from this pin to GND.

a return path for the upper gate drive.

March 19, 2009

Page 6

ISL6622B

PWM

PDHL

PDLU

FIGURE 1. TIMING DIAGRAM

UGATE

LGATE

PDLL

PDHU

Description

Operation and Adaptive Shoot-through Protection

Designed for high speed switching, the ISL6622B MOSFET driver controls both high-side and low-side N-Channel FETs from one externally provided PWM signal.

A rising transition on PWM initiates the turn-off of the lower MOSFET (see Figure 1). After a short propagation delay [t

], the lower gate begins to fall. Typica l fall time [tFL] is

PDLL

provided in the “Electrical S pecifications” on page5. Following a 25ns blanking period, adaptive shoot-through circuitry monitors the LGATE voltage and turns on the upper gate following a short delay time [t drops below ~1.75V. The upper gate drive then begins to rise [t

] and the upper MOSFET turns on.

A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET . A short propagation delay [t begins to fall [t

]. The adaptive shoot-through circuitry

] is encountered before the upper gate

PDLU

monitors the UGATE-PHASE voltage and turns on the lower MOSFET a short delay time [t PHASE voltage drops below +0.8V or 40ns after the upper MOSFET’s gate voltage [UGA TE-PHASE] drops below ~1.75V . The lower gate then rises [t

These methods prevent both the lower and upper MOSFETs from conducting simultaneously (shoot-through), while adapting the dead time to the gate charge characteristics of the MOSFETs being used.

This driver is optimized for voltage regulators with large step down ratio. The lower MOSFET is usually sized larger compared to the upper MOSFET because the lower MOSFET conducts for a longer time during a switching period. The lower gate driver is therefore sized much larger to meet this application requirement. The 0.8 current capability enable the lower gate driver to absorb the current injected into the lower gate through the drain-to-gate capacitor of the lower MOSFET and help prevent

] after the LGATE voltage

PDHU

] after the upper MOSFET’s

PDHL

], turning on the lower MOSFET.

Ω ON-resistance and 3A sink

1.5V<PWM<3.2V

TSHD

PDTS

1.0V<PWM<2.6V

TSLD

shoot-through caused by the self turn-on of the lower MOSFET due to high dV/dt of the switching node.

Advanced PWM Protocol (Patent Pending)

The advanced PWM protocol of ISL6622B is specifically designed to work with Intersil VR11.1 controllers. When ISL6622B detects a PSI

protocol sent by an Intersil VR11.1 controller, it turns on diode emulation operation; otherwise, it remains in normal CCM PWM mode.

Another unique feature of ISL6622B and other Intersil drivers is the addition of a tristate shutdown window to the PW M input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the driver outputs are disabled and both MOSFET gates are pulled and held low . The shutdown state is removed when the PWM signal moves outside the shutdown window . Otherwise, the PWM rising and falling thresholds outlined in the “Electrical Specifications” on page 4 determine when the lower and upper gates are enabled. This feature helps prevent a negative transient on the output voltage when the output is shut down, eliminating the Schottky diode that is used in some systems for protecting the load from reversed output voltage events.

Note that for a PWM low to tri-level (2.5V) transition, the LGATE will not turn off until the diode emulation minimum ON-time of 350ns is expired.

Diode Emulation

Diode emulation allows for higher converter efficiency under light-load situations. With diode emulation active, the ISL6622B detects the zero current crossing of the output inductor and turns off LGATE. This prevents the low side MOSFET from sinking current and ensures that discontinuous conduction mode (DCM) is achieved. The LGATE has a minimum ON-time of 350ns in DCM mode.

Gate Voltage Optimization Technology (GVOT)

The ISL6622B provides the user flexibility in choosing the gate drive voltage for efficiency optimization. In applications when the switching losses dominate system performance, dropping

PDTS

March 19, 2009

Page 7

ISL6622B

down to a lower drive voltage with GVOT can improve the switching losses seen and maximize system efficiency.

Figure 2 shows that the gate drive voltage optimization is accomplished via an internal low drop out regulator (LDO) that regulates the lower gate drive voltage. LVCC is driven to a lower voltage depending on the GD_SEL pin impedance. The input and output of this internal regulator are the VCC and LVCC pins, respectively . Both VCC and LVCC should be decoupled with a high quality, low ESR ceramic capacitor.

EXTERNAL CIRCUIT

VIN

RCC

LVCC

RCC = OPTION FOR HIGHER LVCC

THAN PRE-SET BY GD_SEL

FIGURE 2. GATE VOLTAGE OPTIMIZATION (GVOT) DETAIL

ISL6622B INTERNAL CIRCUIT

VCC

1µF

GVOT

LDO

SET BY GD_SEL

LGATE DRIVER

7.75V (typically). This provides the flexibility necessary to optimize applications involving trade-of fs betwe en gate charge and conduction losses. Table 1 shows the LDO output (LVCC) level set by GD_SEL pin impedance.

TABLE 1. LDO OPERATION AND OPTIONS

PWM INPUT GD_SEL PIN LVCC @ 50mA DC LOAD

Don’t Care Floating 5.75V (Typ ica l; F ixe d in SOI C Pa cka ge)

4.5kΩ to GND 6.75V(Typical) GND 7.75V(Typical)

Figure 3 illustrates the internal LDO’s variation with the average load current plotted over a range of temperatures spanning from -40 L VCC voltage be necessary, a resistor (R

°C to +120°C. Should finer tweaking of this

) can be used to

shunt the LDO, as shown in Figure 2. The resistor thus delivers part of the LGATE drive current, leaving less current going through the internal LDO, elevating the LDO’s output voltage. Further reduction in RCC’s value can raise the L VCC voltage further, as desired.

Power-On Reset (POR) Function

During initial start-up, the VCC voltage rise is moni tored. Once the rising VCC voltage exceeds the rising POR threshold, operation of the driver is enabled and the PWM input signal

takes control of the gate drives. If VCC drops below the POR falling threshold, operation of the driver is disabled.

9.0

8.5

8.0

7.5

7.0

6.5

LVCC VOLTAGE (V)

6.0

5.5

5.0 0 20406080100

FIGURE 3. TYPICAL LVCC VARIATION WITH LOAD

GD_SEL TIED TO GND

GD_SEL TIED TO 4.5kΩ TO GND

GD_SEL FLOATING

AVERAGE LOAD CURRENT (mA)

+120°C

+40°C

-40°C

Pre-POR Overvoltage Protection

While VCC is below its POR level, the upper gate is held low and LGATE is connected to the PHASE pin via an internal 10kΩ (typically) resistor. By connecting the PHASE node to the gate of the low side MOSFET, the driver offers some passive protection to the load if the upper MOSFET(s) is or becomes shorted. If the PHASE node goes higher than the gate threshold of the lower MOSFET, it results in the progressive turn-on of the device and the effective clamping of the PHASE node’s rise. The actual PHASE node clamping level depends on the lower MOSFET’s electrical characteristics, as well as the characteristics of the input supply and the path connecting it to the respective PHASE node.

Internal Bootstrap Device

The ISL6622B features an internal bootstrap Schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the trailing-edge of the PHASE node. This reduces the voltage stress on the BOOT to PHASE pins.

The bootstrap capacitor must have a maximum voltage rating well above the maximum voltage intended for UVCC. Its minimum capacitance value can be estimated from Equation 1:

GATE

BOOT_CAP

GATE

where Q at V

GS1

control MOSFETs. The ΔV allowable droop in the rail of the upper gate drive. Select results are exemplified in Figure 4.

--------------------------------------

≥

ΔV

BOOT_CAP

QG1UVCC•

------------------------------------

GS1

is the amount of gate charge per upper MOSFET

•=

gate-source voltage and NQ1 is the number of

BOOT_CAP

term is defined as the

(EQ. 1)

March 19, 2009

Page 8

ISL6622B

1.6

1.4

1.2

(µF)

1.0

0.8

0.6

BOOT_CAP

0.4

0.2

20nC

0.0

= 100nC

GATE

50nC

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0 ΔV

BOOT_CAP

(V)

FIGURE 4. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

Power Dissipation

Package power dissipation is mainly a function of the switching frequency (F layout resistance, and the selected MOSFET’s internal gate resistance and total gate charge (Q dissipation in the driver for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level may push the IC beyond the maximum recommended operating junction temperature. The DFN package is more suitable for high freq uency applications. See “Layout Considerations” on page 8 for thermal impedance improvement suggestions. The total gate drive power losses due to the gate charge of MOSFETs and the driver’s internal circuitry and their corresponding average driver current can be estimated with Equations 2 and 3, respectively:

Qg_TOTPQg_Q1PQg_Q2IQ

QG1UVCC

Qg_Q1

Qg_Q2

⎛⎞

⎜⎟

⎝⎠

---------------------------------------

QG2LVCC

--------------------------------------

QG1UVCC NQ1••

------------------------------------------------------

GS1

where the gate charge (Q particular gate to source voltage (V corresponding MOSFET data sheet; I quiescent current with no load at both drive outputs; N and N

are number of upper and lower MOSFETs,

respectively; UVCC and LVCC are the drive voltages for both upper and lower FETs, respectively. The I product is the quiescent power of the driver without a load.

), the output drive impedance, the

). Calculating the power

VCC•++=

•

GS1

•

GS2

• NQ1•=

• NQ2•=

LVCC NQ2••

-----------------------------------------------------

GS2

and QG2) is defined at a

and V

GS1

is the driver’s total

GS2

SWIQ

) in the

VCC

(EQ. 2)

+•=

(EQ. 3)

DRPDR_UPPDR_LOWIQ

⎛⎞

HI1

DR_UP

DR_LOW

EXT1RG1

--------------------------------------

⎜⎟

⎝⎠

HI1REXT1

⎛⎞

HI2

--------------------------------------

⎜⎟

⎝⎠

HI2REXT2

GI1

-------------

VCC•++=

LO1

----------------------------------------

LO1REXT1

LO2

----------------------------------------

LO2REXT2

EXT2RG2

Qg_Q1

---------------------

•=

---------------------

•=

-------------

(EQ. 4)

Qg_Q2

GI2

The total gate drive power losses are dissip ated among the resistive components along the transition path, as outlined in Equation 4. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (R resistors (R

GI1

and R

and RG2) and the internal gate

) of MOSFETs. Figures 5 and 6 show

GI2

the typical upper and lower gate drives turn-on current paths.

UVCC

FIGURE 5. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

LVCC

FIGURE 6. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

BOOT

PHASE

HI2

LO2

HI1

LO1

Application Information

Layout Considerations

During switching of the devices, the parasitic inductances of the PCB and the power devices’ packaging (both upper and lower MOSFETs) leads to ringing, possibly in excess of the absolute maximum rating of the devices. Careful layout can help minimize such unwanted stress. The following advice is meant to lead to an optimized layout:

• Keep decoupling loops (L VCC-GND and BOOT-PHASE) as short as possible.

• Minimize trace inductance, especially low-impedance lines: all power traces (UGA TE, PHASE, LGATE, GND, LVCC) should be short and wide, as much as possible.

March 19, 2009

Page 9

ISL6622B

• Minimize the inductance of the PHASE node: ideally, the source of the upper and the drain of the lower MOSFET should be as close as thermally allowable.

• Minimize the input current loop: connect the source of the lower MOSFET to ground as close to the transistor pin as feasible; input capacitors (especially ceramic decoupling) should be placed as close to the drain of upper and source of lower MOSFETs as possible.

In addition, for improved heat dissipation, place copper underneath the IC whether it has an exposed pad or not. The copper area can be extended beyond the bottom area of the IC and/or connected to buried power ground plane(s) with thermal vias. This combination of vias for vertical heat escape, extended surface copper islands, and buried planes combine to allow the IC and the power switches to achieve their full thermal potential.

Upper MOSFET Self Turn-On Effect at Start-up

Should the driver have insufficient bias voltage applied, its outputs are floating. If the input bus is energized at a high dV/dt rate while the driver outputs are floating, due to self coupling via the internal C upper MOSFET could momentarily rise up to a level greater than the threshold voltage of the device, potentially turning on the upper switch. Therefore, if such a situation could conceivably be encountered, it is a common practice to place a resistor (R

UGPH

upper MOSFET to suppress the Miller coupling effect. The value of the resistor depends mainly on the input voltage’s rate of rise, the C

GD/CGS

threshold of the upper MOSFET. A higher dV/dt, a lower C

DS/CGS

ratio, and a lower gate-source threshold upper FET will require a smaller resistor to diminish the effect of the internal capacitive coupling. For most applications, the integrated 20kΩ resistor is sufficient, not affecting normal performance and efficiency.

The coupling effect can be roughly e stimated with Equation 5, which assumes a fixed linear input ramp and neglects the clamping effect of the body diode of the upper drive and the bootstrap capacitor . Other parasitic comp onents, such as lead inductances and PCB capacita nces, are also not t aken in to account. Figure 7 provides a visual reference for this phenomenon and its potential solution.

of the MOSFET , the gate of the

) across the gate and source of the

ratio, as well as the gate-source

V–

--------------------------------- -

-------

⋅

BOOT

UGPH

--------------------------------- -

-------

–

RC⋅

iss

issCGDCGS

V–

RC⋅

⋅

iss

issCGDCGS

VIN

(EQ. 5)

UPPER

(EQ. 6)

⎛⎞

GS_MILLER

UGPHRGI

UVCC

ISL6622B

FIGURE 7. GATE TO SOURCE RESISTOR T O REDUCE

GS_MILLER

UGPHRGI

-------

⋅⋅=

+= C

20kΩ

UPPER MOSFET MILLER COUPLING

-------

⋅⋅=

⎜⎟ ⎜⎟

–

rss

⎜⎟ ⎜⎟ ⎝⎠

= C

rssCGD

BOOT

UGATE

PHASE

⎛⎞ ⎜⎟ ⎜⎟

rss

⎜⎟ ⎜⎟ ⎝⎠

rssCGD

Gate Drive Voltage Options

Intersil provides various gate drive voltage options in the ISL6622 product family, as shown in Table 2.

The ISL6622 can drop the low-side MOSFET’s gate drive voltage when operating in DEM, while the high-side FET’s gate drive voltage of the DFN package can be connected to VCC or LVCC.

The ISL6622A allows the low-side MOSFET(s) to operate from an externally-provided rail as low as 5V, eliminating the LDO losses, while the high-side MOSFET’s gate drive volt age of the DFN package can be connected to VCC or LVCC.

The ISL6622B sets the low-side MOSFET’s gate drive voltage at a fixed, programmable LDO level, while the highside FETs’ gate drive voltage of the DFN package can be connecte d to VCC or LV CC.

TABLE 2. ISL6622 FAMILY OPTIONS

LVCC

POWER RAILS

ISL6622 SOIC 5.75V 11.2V VCC Operating Voltage Ranges from 6.8V to 13.2V

DFN Programmable 11.2V Separate Rail

ISL6622A SOIC Separate Rail VCC

DFN Separate Rail Separate Rail

ISL6622B SOIC 5.75V VCC

DFN Programmable Separate Rail

= LOW PSI = HIGH

UVCC VCCPSI

March 19, 2009

Page 10

Dual Flat No-Lead Plastic Package (DFN)

ISL6622B

INDEX

SEATING

(DATUM B)

INDEX

AREA

(DATUM A)

NX (b)

SECTION "C-C"

AREA

PLANE

NX L

TOP VIEW

SIDE VIEW

BOTTOM VIEW

D2/2

N-1N

(Nd-1)Xe

REF.

(A1)

NX b 5

0.415

0.15

E2/2

0.10 MC

0.200

NX b

0.152XB

0.10 C

0.08

NX L

L10.3x3

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

NOTESMIN NOMINAL MAX

A 0.80 0.90 1.00 -

A1 - - 0.05 -

A3 0.20 REF -

b 0.18 0.23 0.28 5,8

D 3.00 BSC -

D2 1.95 2.00 2.05 7,8

E 3.00 BSC -

E2 1.55 1.60 1.65 7,8

e 0.50 BSC -

k0.25 - - L0.300.35 0.40 8

N102

Nd 5 3

Rev. 3 6/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.

FOR ODD TERMINAL/SIDE

TERMINAL TIP

March 19, 2009

Page 11

Small Outline Plastic Packages (SOIC)

ISL6622B

INDEX AREA

123

-A-

-B-

SEATING PLANE

-C-

0.25(0.010) BM M

h x 45°

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

March 19, 2009