Datasheet ISL6524 Datasheet (intersil)

Page 1

查询ISL6524ACB供应商

ISL6524

Data Sheet April 18, 2005

VRM8.5 PWM and Triple Linear Power System Controller

The ISL6524 provides the power control and protection for four output voltages in high-performance microprocessor and computer applications. The IC integrates one PWM controller and three linear controllers, as well as the monitoring and protection functions into a 28-pin SOIC package. The PWM controller regulates the microprocessor core voltage with a synchronous-rectified buck converter. One linear controller supplies the computer system’s AGTL+

1.2V bus power. The other two linear controllers regulate power for the 1.5V AGP bus and the 1.8V power for the chip set core voltage and/or cache memory circuits.

The ISL6524 includes an Intel VRM8.5 compatible, TTL 5-input digital-to-analog converter (DAC) that adjusts the microprocessor core-targeted PWM output voltage from

1.050V to 1.825V in 25mV steps. The precision reference and voltage-mode control provide ±1% static regulation. The linear regulators use external N-channel MOSFETs or bipolar NPN pass transistors to provide fixed output voltages of 1.2V ±3% (V

The ISL6524 monitors all the output voltages. A delayedrising VTT (V before the core PWM starts to ramp up. Another system Power Good signal is issued when the core is within ±10% of the DAC setting and all other outputs are above their undervoltage levels. Additional built-in overvoltage protection for the core output uses the lower MOSFET to prevent output voltages above 115% of the DAC setting. The PWM controllers’ overcurrent function monitors the output current by using the voltage drop across the upper MOSFET’s r

), 1.5V ±3% (V

OUT2

output) Power Good signal is issued

OUT2

, eliminating the need for a current sensing resistor.

DS(ON)

) and 1.8V ±3% (V

OUT3

OUT4

FN9015.3

Features

• Provides 4 Regulated Voltages

- Microprocessor Core, AGTL+ Bus, AGP Bus Power, and North/South Bridge Core

• Drives N-Channel MOSFETs

• Linear Regulator Drives Compatible with both MOSFET and Bipolar Series Pass Transistors

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast PWM Converter Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratio

• Excellent Output Voltage Regulation

- Core PWM Output: ±1% Over Temperature

- All Other Outputs: ±3% Over Temperature

• VRM8.5 TTL-Compatible 5-Bit DAC Microprocessor Core Output Voltage Selection

- Wide Range - 1.050V to 1.825V

• Power-Good Output Voltage Monitors

- Separate delayed VTT Power Good

• Overcurrent Fault Monitor

- Switching Regulator Doesn’t Require Extra Current

Sensing Element, Uses MOSFET’s r

DS(ON)

• Small Converter Size

- Constant Frequency Operation

- 200kHz Internal Oscillator

• Pb-Free Available (RoHS Compliant)

Applications

•

Motherboard Power Regulation for Computers

Ordering Information

TEMP.

PAR T N UMBER

ISL6524CB* 0 to 70 28 Ld SOIC M28.3

ISL6524CBZ* (See Note)

ISL6524CBZA* (See Note)

ISL6524EVAL1 Evaluation Board

*Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

RANGE (°C) PACKAGE

0 to 70 28 Ld SOIC

(Pb-free)

0 to 70 28 Ld SOIC

(Pb-free)

PKG.

DWG. #

M28.3

1-888-INTERSIL or 1-888-352-6832

Pinout

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

All other trademarks mentioned are the property of their respective owners.

ISL6524 (SOIC) TOP VIEW

VCC

DRIVE2

PGOOD

FAULT/RT

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

FIX

VID3

VID2

VID1

VID0

VID25

VTTPG

VSEN2

SS24

SS13

VSEN4

UGATE

PHASE

LGATE

PGND

OCSET

VSEN1

COMP

VSEN3

DRIVE3

GND

VAU X

DRIVE4

Page 2

VAUX

PGOOD

UGATE

PHASE

LGATE

PGND

GND

VCC

OCSET

VSEN1

POWER-ON

RESET (POR)

VCC

DRIVE1

200µA

1.10

0.90

1.15

SOFT-

LOGIC

START

AND FAULT

GATE

CONTROL

VCC

EA1

PWM

COMP

DRIVE

SYNCH

(DAC)

TTL D/A

CONVERTER

DACOUT

28µA

4.5V

VID25

VID0

VID1

VID2

VID3

COMP

SS24

FIGURE 1.

VSEN3

Block Diagram

1.5V or 1.26V

VAUX

EA3

UV3

x0.75

DRIVE3

SS13

FAULT

UV4

x0.75

DRIVE4

EA4

1.8V or 1.26V

VSEN4

OSCILLATOR

INHIBIT

FIX

DRIVE2

VSEN2

EA2

UV2

x0.90

CLK

SET

1.2V

CLR

FAULT/RT

VTTPG

FN9015.3

April 18, 2005

Page 3

+5V

+3.3V

+12V

OUT2

1.2V

+5V

OUT1

OUT2

LINEAR

CONTROLLER

PWM1

CONTROLLER

ISL6524

OUT3

LINEAR

CONTROLLER

LINEAR

CONTROLLER

OUT4

FIGURE 2. SIMPLIFIED POWER SYSTEM DIAGRAM

OUT2

VCC

OCSET

DRIVE2

FAULT/RT

PGOOD

UGATE

PHASE

OUT1

POWERGOOD

OUT1

1.3V to 3.5V

FIX

VTT POWERGOOD

+3.3V

OUT3

1.5V

OUT3

OUT4

1.8V

OUT4

VSEN2

VTTPG

ISL6524

VAUX

DRIVE3

VSEN3

DRIVE4

VSEN4

SS24

FIGURE 3. TYPICAL APPLICATION

GND

LGATE

PGND

VSEN1

COMP

VID3

VID2

VID1

VID0

VID25

SS13

OUT1

FN9015.3

April 18, 2005

Page 4

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V

PGOOD, RT/FAULT, DRIVE, PHASE, and

GATE Voltage. . . . . . . . . . . . . . . . . . . GND - 0.3V to V

+ 0.3V

Input, Output or I/O Voltage. . . . . . . . . . . . . . . . . . GND -0.3V to 7V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Resistance (Typical, Note 1)

(oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range. . . . . . . . . . -65

C to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

Recommended Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0

Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

C to 70oC

C to 125oC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply Current I

POWER-ON RESET

Rising VCC Threshold - - 10.4 V

Falling VCC Threshold 8.2 - - V

Rising VAUX Threshold -2.5- V

VAUX Threshold Hysteresis -0.5- V

Rising V

Threshold -1.26- V

OCSET

OSCILLATOR

Free Running Frequency F

OSC

Total Variation 6kΩ < RT to GND < 200kΩ; Note 2 -15 - +15 %

Ramp Amplitude ∆V

OSC

DAC REFERENCE

DAC (VID25-VID3) Input Low Voltage 0.8 V

DAC (VID25-VID3) Input High Voltage 2.0 V

DACOUT Voltage Accuracy -1.0 - +1.0 %

LINEAR REGULATORS (V

OUT2

, V

OUT3

, AND V

OUT4

Regulation Tolerance -3- %

VSEN3 Regulation Voltage VREG

VSEN2 Regulation Voltage VREG

VSEN3 Regulation Voltage VREG

VSEN4 Regulation Voltage VREG

VSEN3, 4 Undervoltage Level VSEN3, 4

VSEN3, 4 Undervoltage Hysteresis VSEN3, 4 Falling 7 %

Output Drive Current VAUX-V

SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER

DC Gain Note 2 - 88 - dB

UGATE, LGATE, DRIVE2, DRIVE3, and

-9- mA

DRIVE4 Open

185 200 215 kHz

-1.9- V

)

FIX = 0V - 1.26 - V

FIX = Open - 1.5 - V

FIX = Open - 1.8 - V

VSEN3, 4 Rising - 75 - %

DRIVE2,3,4

> 0.6V 20 40 - mA

-1.2- V

P-P

FN9015.3

April 18, 2005

Page 5

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Gain-Bandwidth Product GBWP Note 2 - 15 - MHz

Slew Rate SR COMP = 10pF, Note 2 - 6 - V/µs

PWM CONTROLLERS GATE DRIVERS

UGATE Source I

UGATE Sink R

LGATE Source I

LGATE Sink R

UGATE

LGATE

PROTECTION

FAULT Sourcing Current I

OCSET Current Source I

Soft-Start Current I

OVP

OCSET

SS13,24

POWER GOOD

VSEN1 Upper Threshold (VSEN1/DACOUT)

VSEN1 Undervoltage (VSEN1/DACOUT)

VSEN1 Hysteresis (VSEN1/DACOUT) VSEN1 Falling - 2 - %

PGOOD Voltage Low V

PGOODIPGOOD

VSEN2 Undervoltage VSEN2 Rising 1.08 V

VSEN2 Hysteresis VSEN2 Falling - 48 - mV

VTTPG Voltage Low V

VTTPGIVTTPG

NOTE:

2. Guaranteed by design

VCC = 12V, V

GATE-PHASE

VCC = 12V, V

= 1V - 1.4 3.0 Ω

LGATE

FAULT/R T

OCSET

SS13,24

= 2.0V - 8.5 - mA

= 4.5V

= 2.0V

= 6V - 1 - A

UGATE

= 1V - 1.7 3.5 Ω

= 1V - 1 - A

LGATE

170 200 230 µA

-28- µA

VSEN1 Rising 108 - 110 %

VSEN1 Rising 92 - 94 %

= -4mA - - 0.8 V

Typical Performance Curves

1000

100

RESISTANCE (kΩ)

RT PULLUP TO +12V

RT PULLDOWN TO V

10 100 1000

SWITCHING FREQUENCY (kHz)

FIGURE 4. RT RESISTANCE vs FREQUENCY FIGURE 5. BIAS SUPPLY CURRENT vs FREQUENCY

100

= C

UGATE

VIN = 5V

VCC = 12V

(mA)

0 100 200 300 400 500 600 700 800 900 1000

= C

LGATE

SWITCHING FREQUENCY (kHz)

C = 4800pF

C = 3600pF

C = 1500pF

C = 660pF

FN9015.3

April 18, 2005

Page 6

Functional Pin Descriptions

VCC (Pin 28)

Provide a 12V bias supply for the IC to this pin. This pin also provides the gate bias charge for all the MOSFETs controlled by the IC. The voltage at this pin is monitored for Power-On Reset (POR) purposes.

GND (Pin 17)

Signal ground for the IC. All voltage levels are measured with respect to this pin.

PGND (Pin 24)

This is the power ground connection. Tie the synchronous PWM converter’s lower MOSFET source to this pin.

VAUX (Pin 16)

Connect this pin to the ATX 3.3V output. The voltage present at this pin is monitored for sequencing purposes. This pin provides the necessary base bias for the NPN pass transistors, as well as the current sunk through the 5kW VID pull-up resistors.

SS13 (Pin 13)

Connect a capacitor from this pin to ground. This capacitor, along with an internal 28mA current source, sets the soft-start interval of the synchronous switching converter (V the AGP regulator (V

). A VTTPG high signal is also

OUT3

delayed by the time interval required by the charging of this capacitor from 0V to 1.25V (see Soft-Start details).

SS24 (Pin 12)

Connect a capacitor from this pin to ground. This capacitor, along with an internal 28mA current source, sets the soft-start interval of the V

regulator. Pulling this pin

OUT2

below 0.8V induces a chip reset (POR) and shutdown.

VTTPG (Pin 9)

VTTPG is an open collector output used to indicate the status of the V pulled low when the V

regulator output voltage. This pin is

OUT2

output is below the undervoltage

OUT2

threshold or when the SS13 pin is below 1.25V.

PGOOD (Pin 8)

PGOOD is an open collector output used to indicate the status of the output voltages. This pin is pulled low when the synchronous regulator output is not within

±10% of the

DACOUT reference voltage or when any of the other outputs is below its undervoltage threshold.

VID3, VID2, VID1, VID0, VID25 (Pins 3-7)

VID3-25 are the TTL-compatible input pins to the 5-bit DAC. The logic states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the microprocessor core converter output voltage (V well as the corresponding PGOOD and OVP thresholds. Each VID pin is connected to the VAUX pin through a 5kW pull-up resistor.

OUT1

) and

), as

OCSET (Pin 23)

Connect a resistor (R upper MOSFET. R (I

), and the upper MOSFET’s on-resistance (r

OCSET

set the converter overcurrent (OC) trip point according to the following equation:

PEAK

----------------------------------------------------

OCSETROCSET

DS ON()

An overcurrent trip cycles the soft-start function.

The voltage at OCSET pin is monitored for power-on reset (POR) purposes.

) from this pin to the drain of the

OCSET

, an internal 200mA current source

DS(ON)

PHASE (Pin 26)

Connect the PHASE pin to the PWM converter’s upper MOSFET source. This pin represents the gate drive return current path and is used to monitor the voltage drop across the upper MOSFET for overcurrent protection.

UGATE (Pin 27)

Connect UGATE pin to the PWM converter’s upper MOSFET gate. This pin provides the gate drive for the upper MOSFET.

LGATE (Pin 25)

Connect LGATE to the synchronous PWM converter’s lower MOSFET gate. This pin provides the gate drive for the lower MOSFET.

COMP and FB (Pins 20, 21)

COMP and FB are the available external pins of the synchronous PWM regulator error amplifier. The FB pin is the inverting input of the error amplifier. Similarly, the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter.

VSEN1 (Pin 22)

This pin is connected to the synchronous PWM converters’ output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status.

DRIVE2 (Pin 1)

Connect this pin to the gate/base of a N-type external pass transistor (MOSFET or bipolar). This pin provides the drive for the 1.2V regulator’s pass transistor.

VSEN2 (Pin 11)

Connect this pin to the output of the standard buck PWM regulator. The voltage at this pin is regulated to a 1.2V level. This pin is also monitored for undervoltage events.

FIX (Pin 2)

Grounding this pin bypasses the internal resistor dividers that set the output voltage of the 1.5V and 1.8V linear regulators. This way, the output voltage of the two regulators can be adjusted from 1.26V up to the input voltage (+3.3V or +5V;

)

FN9015.3

April 18, 2005

Page 7

VOUT4 can only be set from 1.7V up) by way of an external resistor divider connected at the corresponding VSEN pin. The new output voltage set by the external resistor divider can be determined using the following formula:



OUT

where R

OUT

1.265V 1

is the resistor connected from VSEN to the

OUT

output of the regulator, and R

---------------- -

×=





GND

is the resistor connected from VSEN to ground. Left open, the FIX pin is pulled high, enabling fixed output voltage operation.

DRIVE3 (Pin 18)

Connect this pin to the gate/base of a N-type external pass transistor (MOSFET or bipolar). This pin provides the drive for the 1.5V regulator’s pass transistor.

VSEN3 (Pin 19)

Connect this pin to the output of the 1.5V linear regulator. This pin is monitored for undervoltage events.

DRIVE4 (Pin 15)

Connect this pin to the base of an external bipolar transistor. This pin provides the drive for the 1.8V regulator’s pass transistor.

VSEN4 (Pin 14)

Connect this pin to the output of the linear 1.8V regulator. This pin is monitored for undervoltage events.

FAULT/RT (Pin 10)

This pin provides oscillator switching frequency adjustment. By placing a resistor (R

) from this pin to GND, the nominal

200kHz switching frequency is increased according to the following equation:

510

-------------------- -

Fs 200 k H z

+≈

kΩ()

(RT to GND)

Conversely, connecting a resistor from this pin to VCC reduces the switching frequency according to the following equation:

410

Fs 200 k H z

-------------------- -

–≈

kΩ()

(RT to 12V)

Nominally, the voltage at this pin is 1.26V. In the event of an overvoltage or overcurrent condition, this pin is internally pulled to VCC.

Description

Operation

The ISL6524 monitors and precisely controls 4 output voltage levels (Refer to Figures 1, 2, 3). It is designed for microprocessor computer applications with 3.3V, 5V, and 12V bias input from an ATX power supply. The IC has one PWM and three linear controllers. The PWM controller is designed to regulate the microprocessor core voltage (V

OUT1

). The PWM

controller drives 2 MOSFETs (Q1 and Q2) in a synchronousrectified buck converter configuration and regulates the core voltage to a level programmed by the 5-bit digital-to-analog converter (DAC). The first linear controller (EA2) is designed to provide the AGTL+ bus voltage (V

) by driving a MOSFET

OUT2

(Q3) pass element to regulate the output voltage to a level of

1.2V. The remaining two linear controllers (EA3 and EA4) supply the 1.5V advanced graphics port (AGP) bus power (V

) and the 1.8V chip set core power (V

OUT3

OUT4

Initialization

The ISL6524 automatically initializes in ATX-based systems upon receipt of input power. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias voltage (+12V 5V input voltage (+5V input voltage (+3.3V OCSET is equal to +5V

) at the OCSET pin, and the 3.3V

) at the VAUX pin. The normal level on

less a fixed voltage drop (see

) at the VCC pin, the

overcurrent protection). The POR function initiates soft-start operation after all supply voltages exceed their POR thresholds.

Soft-Start

The 1.8V supply designed to power the chip set (OUT4), cannot lag the ATX 3.3V by more than 2V, at any time. To meet this special requirement, the linear block controlling this output operates independently of the chip’s power-on reset. Thus, DRIVE4 is driven to raise the OUT4 voltage before the input supplies reach their POR levels. As seen in Figure 6, at time T0 the power is turned on and the input supplies ramp up. Immediately following, OUT4 is also ramped up, lagging the ATX 3.3V by about 1.8V. At time T1, the POR function initiates the SS24 soft-start sequence. Initially, the voltage on the SS24 pin rapidly increases to approximately 1V (this minimizes the soft-start interval). Then, an internal 28mA current source charges an external capacitor (C SS24 voltage increases, the EA2 error amplifier drives Q3 to provide a smooth transition to the final set voltage. The OUT4 reference (clamped to SS24) increasing past the intermediary level, established based on the ATX 3.3V presence at the VAUX pin, brings the output in regulation soon after T2.

As OUT2 increases past the 90% power-good level, the second soft-start (SS13) is released. Between T2 and T3, the SS13 pin voltage ramps from 0V to the valley of the oscillator’s triangle wave (at 1.25V). Contingent upon OUT2 remaining above

1.08V, the first PWM pulse on PHASE1 triggers the VTTPG pin to go high. The oscillator’s triangular wave form is compared to the clamped error amplifier output voltage. As the SS13 pin voltage increases, the pulse-width on the PHASE1 pin increases, bringing the OUT1 output within regulation limits. Similarly, the SS13 voltage clamps the reference voltage for OUT3, enabling a controlled output voltage ramp-up. At time T4, all output voltages are within power-good limits, situation reported by the PGOOD pin going high.

) on the SS24 pin to about 4.5V. As the

SS24

FN9015.3

April 18, 2005

Page 8

10V

3.0V

ATX 12V

ATX 5 V

SS24

ATX 3 . 3V

OUT4

(1.8V)

VTTPG

PGOOD

SS13

OUT1

(1.65V)

VSEN3, or VSEN4) is ignored until the respective UP signal goes high. This allows V

OUT3

and V

OUT4

to increase without fault at start-up. Following an overcurrent event (OC1, UV2, or UV3 event), bringing the SS24 pin below 0.8V resets the overcurrent latch and generates a soft-started ramp-up of the outputs 1, 2, and 3.

SS13UP

LATCH

SRQ

COUNTER

INHIBIT1,2,3

SSDOWN

UV3

OC1

SS13

(1.2V)

OUT2

(1.5V)

OUT3

T1 T2 T4T0 T5

FIGURE 6. SOFT-START INTERVAL

TIME

The T2 to T3 time interval is dependent upon the value of C

. The same capacitor is also responsible for the ramp-

SS13

up time of the OUT1 and OUT3 voltages. If selecting a different capacitor then recommended in the circuit application literature, consider the effects the different value will have on the ramp-up time and inrush currents of the OUT1 and OUT3 outputs.

Fault Protection

All four outputs are monitored and protected against extreme overload. The chip’s response to an output overload is selective, depending on the faulting output.

An overvoltage on V 1, 2, and 3, and latches the IC off. An undervoltage on V

output latches the IC off. A single overcurrent event

OUT4

on output 1, or an undervoltage event on output 2 or 3, increments the respective fault counters and triggers a shutdown of outputs 1, 2, and 3, followed by a soft-start restart. After three consecutive fault events on either counter, the chip is latched off. Removal of bias power resets both the fault latch and the counters. Both counters are also reset by a successful start-up of all the outputs.

Figure 6 shows a simplified schematic of the fault logic. The overcurrent latches are set dependent upon the states of the overcurrent (OC1), output 2 and 3 undervoltage (UV2, UV3) and the soft-start signals (SS13, SS24). Window comparators monitor the SS pins and indicate when the respective C

pins are fully charged to above 4.0V (UP

signals). An undervoltage on either linear output (VSEN2,

output (VSEN1) disables outputs

OUT1

0.8V

SS24

SS24UP

SRQ

LATCH

POR

COUNTER

UV4

UV2

FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC

FAULT

LATCH

FAULT

OUT1 Overvoltage Protection

The overvoltage circuit provides protection during the initial application of power. For voltages on the VCC pin below the power-on reset level (and above ~4V), the output level is monitored for voltages above 1.3V. Should VSEN1 exceed this level, the lower MOSFET, Q2, is driven on.

Overcurrent Protection

All outputs are protected against excessive overcurrents. The PWM controller uses the upper MOSFET’s onresistance, r against a shorted output. All linear regulators monitor their respective VSEN pins for undervoltage to protect against excessive currents.

Figure 8 illustrates the overcurrent protection with an overload on OUT1. The overload is applied at T0 and the current increases through the inductor (L comparator trips when the voltage across Q1 (i exceeds the level programmed by R outputs 1, 2, and 3, discharges the soft-start capacitor C with 28mA current sink, and increments the counter. Soft-start capacitor C

SS13

up at T2 and initiates a new soft-start cycle. With OUT2 still overloaded, the inductor current increases to trip the overcurrent comparator. Again, this inhibits the outputs, but the C

soft-start voltage continues increasing to above

SS24

to monitor the current for protection

DS(ON)

). At time T1, the OC1

OUT1

OCSET

is quickly discharged. C

• r

. This inhibits

starts ramping

SS13

DS(ON)

SS24

)

FN9015.3

April 18, 2005

Page 9

4.0V before discharging. Soft-start capacitor C

SS13

is, again, quickly discharged. The counter increments to 2. The softstart cycle repeats at T3 and trips the overcurrent comparator. The SS24 pin voltage increases to above 4.0V at T4 and the counter increments to 3. This sets the fault latch to disable the converter.

FAU LT

REPORTED

COUNT

= 2

OVERLOAD

APPLIED

T1 T2 T3T0 T4

TIME

COUNT

= 3

SS24

10V

FAULT/RT

COUNT

= 1

SS13

INDUCTOR CURRENT

FIGURE 8. OVERCURRENT OPERATION

The OC trip point varies with MOSFET’s r

DS(ON)

temperature variations. To avoid overcurrent tripping in the normal operating load range, determine the ROCSET resistor value from the equation above with:

1. The maximum r

2. The minimum I

3. Determine I

PEAK

at the highest junction temperature

DS(ON)

from the specification table

OCSET

for I

PEAK

> I

OUT(MAX)

+ (DI)/2,

where DI is the output inductor ripple current.

For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’.

OVERCURRENT TRIP:

VDSV

iDr

× I

DS ON()

PWM

CONTROL

SET

×>

OCSETROCSET

OCSET

200µA

DRIVE

GATE

OCSET

VCC

UGATE

PHASE

PHASEVINVDS

OCSETVINVSET

SET

VIN = +5V

–=

The three linear controllers monitor their respective VSEN pins for undervoltage. Should excessive currents cause VSEN3 or VSEN4 to fall below the linear undervoltage threshold, the respective UV signals set the OC latch or the FAULT latch, providing respective C

capacitors are fully

charged. Blanking the UV signals during the CSS charge interval allows the linear outputs to build above the undervoltage threshold during normal operation. Cycling the bias input power off then on resets the counter and the fault latch.

An external resistor (R

) programs the overcurrent trip

OCSET

level for the PWM converter. As shown in Figure 9, the internal 200mA current sink (I R

OCSET (VSET

) that is referenced to VIN. The DRIVE signal

) develops a voltage across

OCSET

enables the overcurrent comparator (OC). When the voltage across the upper MOSFET (V

DS(ON)

) exceeds V

SET

, the overcurrent comparator trips to set the overcurrent latch. Both V

and VDS are referenced to VIN and a small capacitor

SET

across R

OCSET

helps V

track the variations of VIN due

OCSET

to MOSFET switching. The overcurrent function will trip at a peak inductor current (I

PEAK

----------------------------------------------------

OCSETROCSET

DS ON()

determined by:

PEAK)

FIGURE 9. OVERCURRENT DETECTION

OUT1 Voltage Program

The output voltage of the PWM converter is programmed to discrete levels between 1.050V and 1.825V. This output (OUT1) is designed to supply the core voltage of Intel’s advanced microprocessors. The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a TTL-compatible 5-bit digital-to-analog converter (DAC). The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the different combinations of connections on the VID pins. The VID pins can be left open for a logic 1 input, since they are internally pulled to the VAUX pin through 5kW resistors. Changing the VID inputs during operation is not recommended and could toggle the PGOOD signal and exercise the overvoltage protection. The output voltage program is Intel VRM8.5 compatible.

FN9015.3

April 18, 2005

Page 10

TABLE 1. OUT1 OUTPUT VOLTAGE PROGRAM

PIN NAME NOMINAL

DACOUT

VO LTAG EVID3 VID2 VID1 VID0 VID25

010001.050

010011.075

001101.100

001111.125

001001.150

001011.175

000101.200

000111.225

000001.250

000011.275

111101.300

111111.325

111001.350

111011.375

110101.400

110111.425

110001.450

110011.475

101101.500

101111.525

101001.550

101011.575

100101.600

100111.625

100001.650

100011.675

011101.700

011111.725

011001.750

011011.775

010101.800

010111.825

NOTE: 0 = connected to GND, 1 = open or connected to 3.3V through pull-up resistors

Application Guidelines

Soft-Start Interval

Initially, the soft-start function clamps the error amplifier’s output of the PWM converter. This generates PHASE pulses of increasing width that charge the output capacitor(s). The resulting output voltages start-up as shown in Figure 6.

The soft-start function controls the output voltage rate of rise to limit the current surge at start-up. The soft-start interval and the surge current are programmed by the soft-start capacitor, C increases the peak surge current. Using the recommended

0.1mF soft start capacitors ensure all output voltages ramp

. Programming a faster soft-start interval

up to their set values in a quick and controlled fashion, while meeting the system timing requirements.

Shutdown

The PWM output does not switch until the soft-start voltage (V

) exceeds the oscillator’s valley voltage. Additionally,

SS13

the reference on each linear’s amplifier is clamped to the softstart voltage. Holding the SS24 pin low (with an open drain or open collector signal) turns off regulators 1, 2 and 3. Regulator 4 (MCH) will simply drop its output to the intermediate soft-start level. This output is not allowed to violate the 2V maximum potential gap to the ATX 3.3V output.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turn-off transition of the upper MOSFET. Prior to turn-off, the upper MOSFET was carrying the full load current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET or Schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes.

There are two sets of critical components in a DC-DC converter using an ISL6524 controller. The switching power components are the most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current.

The power components and the controller IC should be placed first. Locate the input capacitors, especially the highfrequency ceramic decoupling capacitors, close to the power switches. Locate the output inductor and output capacitors between the MOSFETs and the load. Locate the PWM controller close to the MOSFETs.

The critical small signal components include the bypass capacitor for VCC and the soft-start capacitor, C these components close to their connecting pins on the control IC. Minimize any leakage current paths from any SS node, since the internal current source is only 28mA.

A multi-layer printed circuit board is recommended. Figure 10 shows the connections of the critical components in the converter. Note that the capacitors C

and C

could represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer.

OUT

. Locate

each

FN9015.3

April 18, 2005

Page 11

Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE node, but do not unnecessarily oversize this particular island. Since the PHASE node is subject to very high dV/dt voltages, the stray capacitor formed between these island and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the control IC to the MOSFET gate and source should be sized to carry 2A peak currents.

+5V

+3.3V

OUT2

LOAD

SS24,13

OUT3

LOAD

+3.3V

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE

OUT2

+12V

VCC

DRIVE2

SS24 SS13

ISL6524

DRIVE3

GNDVCC

OCSET

DRIVE4

PGND

UGATE

PHASE

LGATE

OCSET

OUT

CR1

OUT4

OUT1

OUT4

LOAD

The modulator transfer function is the small-signal transfer function of V

OUT/VE/A

Gain, given by V a double pole break frequency at F

OSC

∆V

OSC

E/A

FIGURE 11. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

. This function is dominated by a DC

IN/VOSC

ERROR AMP

DETAILED COMPENSATION COMPONENTS

ISL6524

, and shaped by the output filter, with

and a zero at F

DRIVER

PWM

COMP

DRIVER

REFERENCE

DACOUT

PHASE

(PARASITIC)

ESR

OUT

Modulator Break Frequency Equations

----------------------------------------

2π L

××

OCO

ESR

-----------------------------------------

2π ESR C

××

OUT

FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

PWM1 Controller Feedback Compensation

The PWM controller uses voltage-mode control for output regulation. This section highlights the design consideration for a voltage-mode controller requiring external compensation.

Figure 11 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (V

) is regulated to the Reference voltage level. The

OUT

reference voltage level is the DAC output voltage (DACOUT) for the PWM. The error amplifier output (V the oscillator (OSC) triangular wave to provide a pulse-width modulated wave with an amplitude of V The PWM wave is smoothed by the output filter (L

) is compared with

E/A

at the PHASE node.

and CO).

The compensation network consists of the error amplifier (internal to the ISL6524) and the impedance networks Z Z

. The goal of the compensation network is to provide a

and

closed loop transfer function with high 0dB crossing frequency (f

) and adequate phase margin. Phase margin is the

0dB

difference between the closed loop phase at f

and 180o.

0dB

The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3 , C1, C2, and C3) in Figure 11. Use these guidelines for locating the poles and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1

3. Place 2

4. Place 1

5. Place 2

Zero Below Filter’s Double Pole (~ 75% FLC)

Zero at Filter’s Double Pole

Pole at the ESR Zero

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

FN9015.3

April 18, 2005

Page 12

Compensation Break Frequency Equations

-----------------------------------

2π R× 2C1×

-------------------------------------------------------

2π R1 R3+()C3××

-------------------------------------------------------

2π R

-----------------------------------

2π R× 3C3×

Figure 12 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown in Figure 12. Using the above guidelines should yield a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at F

of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 12 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain.

log

GAIN



--------



100

GAIN (dB)

-20 MODULATOR

-40

-60

FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

FLCF

ESR

FREQUENCY (Hz)

The compensation gain uses external impedance networks Z

and ZIN to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin.

C1 C2×



----------------------

××



C1 C2+

with the capabilities

OPEN LOOP

ERROR AMP GAIN



------------------

log





PP–

COMPENSATION

GAIN

CLOSED LOOP

GAIN

10M1M100K10K1K10010

Component Selection Guidelines

Output Capacitor Selection

The output capacitors for each output have unique requirements. In general the output capacitors should be selected to meet the dynamic regulation requirements. Additionally, the PWM converter requires an output capacitor to filter the current ripple. The load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demands.

PWM Output Capacitors

Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements.

Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR determines the output ripple voltage and the initial voltage drop following a high slew-rate transient’s edge. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.

Linear Output Capacitors

The output capacitors for the linear regulators provide dynamic load current. Thus capacitors C C

should be selected for transient load regulation.

OUT4

OUT2

, C

OUT3

, and

PWM Output Inductor Selection

The PWM converter requires an output inductor. The output inductor is selected to meet the output voltage ripple requirements and sets the converter’s response time to a load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:

∆I

–

INVOUT

------------------------------- -

Increasing the value of inductance reduces the ripple current and voltage. However, large inductance values increase the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6524 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial

OUT

--------------- -

×=

L×

∆ I∆ ESR×=

OUT

FN9015.3

April 18, 2005

Page 13

current value to the post-transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required.

The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:

RISE

where: I

TRAN

response time to the application of load, and t

LOI

------------------------------- -

–

INVOUT

TRAN

FALL

LOI

-------------------------------

OUT

is the transient load current step, t

FALL

TRAN

RISE

is the

is the response time to the removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.

Input Capacitor Selection

The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage. The maximum RMS current rating requirement for the input capacitors of a buck regulator is approximately 1/2 of the DC output load current. Worst-case RMS current draw in a circuit employing the ISL6524 amounts to the largest RMS current draw of the switching regulator.

MOSFET Selection/Considerations

The ISL6524 requires 5 external transistors. Two N-channel MOSFETs are employed by the PWM converter. The GTL, AGP, and memory linear controllers can each drive a MOSFET or a NPN bipolar as a pass transistor. All these transistors should be selected based upon r

DS(ON)

, current gain, saturation voltages, gate supply requirements, and thermal management considerations.

PWM MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two main loss components: conduction losses and switching losses. These losses are distributed between the upper and lower MOSFET according to the duty factor. The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage.

The equations presented assume linear voltage-current transitions and do not model power losses due to the lower MOSFET’s body diode or the output capacitances associated with either MOSFET. The gate charge losses are dissipated by the controller IC (ISL6524) and do not contribute to the MOSFETs’ heat rise. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.

Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances.

For a through-hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested.

The r

UPPER

LOWER

DS(ON)

× V

------------------------------------------------------------

× VINV

----------------------------------------------------------- ----------------------

DS ON()

is different for the two equations above even if

OUT

× tSW× FS×

OVIN

----------------------------------------------------

–()×

OUT

the same device is used for both. This is because the gate drive applied to the upper MOSFET is different than the lower MOSFET. Figure 13 shows the gate drive where the upper MOSFET’s gate-to-source voltage is approximately V

less the input supply. For +5V main power and +12VDC

for the bias, the approximate gate-to-source voltage of Q1 is 7V. The lower gate drive voltage is 12V. A logic-level MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to V

FN9015.3

April 18, 2005

Page 14

+12V

VCC

ISL6524

FIGURE 13. UPPER GATE DRIVE - DIRECT VCC DRIVE

UGATE

PHASE

LGATE

PGND

GND

+5V OR LESS

CR1

NOTE: V

≈ V

-5V

Rectifier CR1 is a clamp that catches the negative inductor swing during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. For best results, the diode must be a surface-mount Schottky type to prevent the parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but one must ensure the PHASE node negative voltage swing does not exceed -3V to -5V peak. The diode's rated reverse breakdown voltage must be equal or greater to 1.5 times the maximum input voltage.

Linear Controllers Transistor Selection

The ISL6524 linear controllers are compatible with both NPN bipolar as well as N-channel MOSFET transistors. The main criteria for selection of pass transistors for the linear regulators is package selection for efficient removal of heat. The power dissipated in a linear regulator is

LINEARIOVINVOUT

Select a package and heatsink that maintains the junction temperature below the maximum desired temperature with the maximum expected ambient temperature.

When selecting bipolar NPN transistors for use with the linear controllers, insure the current gain at the given operating V

output load current when the base is fed with the minimum driver output current.

In order to ensure the strict timing/level requirement of OUT4, an NPN transistor is recommended for use as a pass element on this output (Q5). A low gate threshold NMOS could be used, but meeting the requirements would then depend on the VCC bias being sufficiently high to allow control of the MOSFET.

–()×=

is sufficiently large to provide the desired

FN9015.3

April 18, 2005

Page 15

+5V

+12V

+3.3V

GND GND

1µH

680µF

GND

(VTT)

OUT2

+1.2V

VTT

POWER GOOD

HUF76107

(AGP)

OUT3

+1.5V

(MCH)

OUT4

+1.8V

HUF76107

R10

10kΩ

C17 560µF

2SD1802

C20 560µF

1000µF

C14

10µF

FAULT/RT

DRIVE3

DRIVE4

FIX

DRIVE2

VSEN2

VTTPG

VAU X

VSEN3

VSEN4

1µF

VCC

ISL6524

GND

OCSET1

PGOOD

UGATE1

PHASE1

LGATE1

PGND

VSEN1

FB1

COMP1

VID25

VID0

VID1

VID2

VID3

SS24

SS13

C21

0.1µF

1nF

1.5kΩ

2.2nF

C12

270pF

C15

HUF76139

Q2 HUF76143

R14

43kΩ

C18

0.1µF

4.99kΩ

R11

3.32kΩ

10kΩ

C13

22nF

C3 1µF

R15

267kΩ

1.8µH

R13

33Ω

POWER GOOD

(1.050V to 1.825V)

C7-9

3x1000µF

C11

0.30µF

R12

12.1k

OUT1

(CORE)

FIGURE 14. TYPICAL APPLICATION CIRCUIT

ISL6524 DC-DC Converter Application Circuit

Figure 14 shows an application circuit of a power supply for a microprocessor computer system. The power supply provides the microprocessor core voltage (V bus voltage (V

), the AGP bus voltage (V

OUT2

OUT1

OUT3

), the GTL

), and the

memory controller hub voltage (V

) from +3.3V, +5VDC,

OUT4

and +12VDC. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note AN9925. Also see Intersil web page (www.intersil.com), for the latest information.

FN9015.3

April 18, 2005

Page 16

Small Outline Plastic Packages (SOIC)

INDEX AREA

123

SEATING PLANE

-AD

0.25(0.010) C AM BS

-B-

-C-

0.25(0.010) BM M

0.10(0.004)

h x 45

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

M28.3 (JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9

C 0.0091 0.0125 0.23 0.32 -

D 0.6969 0.7125 17.70 18.10 3

E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.01 0.029 0.25 0.75 5

L 0.016 0.050 0.40 1.27 6

N28 287

Rev. 0 12/93

NOTESMIN MAX MIN MAX

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9015.3

April 18, 2005