Datasheet ISL6425 Datasheet (intersil)

Page 1

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ISL6425

Data Sheet

Single Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs

The ISL6425 is a highly integrated solution for supplying power and control signals from advanced satellite set-top box (STB) modules to the low noise block (LNB). This device is comprised of a current-mode boost PWM and a low-noise linear regulator, along with the circuitry required for I device interfacing and for providing DiSEqC standard control signals to the LNB.

A regulated output voltage is available at the output terminal (VOUT) to support the operation of the antenna port in advanced satellite STB applications. The regulated output may be set to either 13V or 18V by use of the voltage select command (VSEL) through the I compensate for the voltage drop in the coaxial cable, the voltage may be increased by 1V with the line length compensation (LLC) feature. An enable command sent on

the I

C bus provides standby mode control for the PWM and

linear combination, disabling the output to conserve power.

A current-mode boost converter provides the linear regulator with an input voltage that is set to the required output voltage, plus 1.2V (typ.) to insure minimum power dissipation. This maintains a constant voltage drop across the linear pass element, while permitting an adequate voltage range for tone injection.

The device is capable of providing 750mA (typ.).

C bus. Additionally, to

Ordering Information

TEMP.

PART NUMBER

ISL6425ER -20 to 85 32 Ld 5x5 QFN L32.5x5

ISL6425ER-T 32 Ld 5x5 QFN Tape and Reel L32.5x5

ISL6425ERZ (Note)

ISL6425ERZ-T (Note)

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

RANGE (°C) PACKAGE

-20 to 85 32 Ld 5x5 QFN (Pb-free)

32 Ld 5x5 QFN Tape and Reel (Pb-free)

PKG.

DWG. #

L32.5x5

February 8, 2005

FN9176.1

Features

• Switch-Mode Power Converter for Lowest Dissipation

- Boost PWM with >92% Efficiency

- Selectable 13V or 18V Outputs

- Digital Cable Length Compensation (1V)

• External Pin to Select 13V/18V Options

• DSQIN and SEL18V pins are 2.5V logic compatible

C Compatible Interface for Remote Device Control

•I

- Registered Slave Address 0001 00XX

- Fully Functional 3.3V, 5V Operation up to 400kHz

• Built-In Tone Oscillator Factory Trimmed to 22kHz

- Facilitates DiSEqC (EUTELSAT) Encoding

• Internal Over-Temperature Protection and Diagnostics

• Internal Overload and Overtemp Flags (Visible on I

• LNB Short-Circuit Protection and Diagnostics

• QFN Package

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline

- Near Chip-Scale Package Footprint

• Pb-free available (RoHS Compliant)

Applications

• LNB Power Supply and Control for Satellite Set-Top Box

References

• Tech Brief 389 (TB389) - “PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages”; Available on the Intersil website, www.intersil.com

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

All other trademarks mentioned are the property of their respective owners.

| Intersil (and design) is a trademark of Intersil Americas Inc.

Page 2

Pinout

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PGND

ISL6425

ISL6425 (32 LEAD 5x5 QFN)

TOP VIEW

32 31 30 29 28 2 7 26 25

VCC

CPVOUT

CPSWOUT

SGND

SEL18V

BYPASS

PGND

GATE

9 10111213141516

COMP

VSW

SDA

ADDR

AGND

VOUT

DSQIN

TCAP

SCL CPSWIN

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Typical Application Schematic

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VIN

L2 33uH

C6 56uF

6 7 8

STPS2L40U

FDS6612A

C4 56uF

C17

C16 1uF

PGND

C15 10uF

SGND

SEL18V

BYP

PGND

GATE

C10 33p

C8 1uF

C13 10uF

R5 100

0.1 100pF

1 2

L3 4.7uH

C14 10uF

45 3 2 1

R8 68KC9 1.5n

NC31NC

ISL6425ER

COMP

VSW

11FB10

VCC

CPVOUT

SDA14ADDR

CPSWIN

CPSWOUT

SCL

47nF

C18 1n

NC NC NC

AGND

VOUT

DSQIN

TCAP

D5 STPS2L40U

24 23 22 21 20 19 18 17

C20

0.22uF

R10 1k

R11 1k

D3 STPS2L40U

R13 100k

C22

0.1uF

VLNB1

ISL6425

DSQIN1

SCL

SDA

SEL18V1

February 8, 2005

FN9176.1

Page 4

Block Diagram

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VREF

SEL18V

BAND GAP

RE F VO LTA GE

REF

VOLTAGE

ADJ

ISEL

ENT

OTF

BGV

OLF

INTERFACE

LLC VSEL

TONE

INJ

CKT

I2C

OSC.

CLK

220kHz

÷ 10 AND

WAVE SHAP ING

22kHz TONE

SDA

ADDR

SCL

DCL

ENT

SDA

ADDR

SCL

DSQIN

ISL6425

COUNTER

GATE

E PAD

PGND

COMP

VSW

OVERCURRENT

PROTECTION

LOGIC SCHEME 1

ILIM

CS AMP

PWM

LOGIC

∑

SLOPE

COMPENSATION

OLF

DCL

CLK

VOUT

VCC

SGND

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ON CHIP

LINEAR

UVLO

POR

SOFT-START

BYPASS

INT 5V

SOFT-START

AGND

OTF

TCAP

THERMAL

SHUTDOWN

CHARGE PUMP

CPSWOUT

251821

CPVOUT

CPSWIN

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ISL6425

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Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V

Logic Input Voltage Range

(SDA, SCL, ENT, DSQIN, SEL18V) . . . . . . . . . . . . . . -0.5V to 7V

Output Current . . . . . . . . . . . . . . . . . . . . Externally/Internally Limited

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

2. For θ

, the “case temperature” location is the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Thermal Resistance θ

QFN Package (Notes 1, 2) . . . . . . . . 32 4

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

NOTE: The device junction temperature should be kept below 150°C. Thermal shut-down circuitry turns off the device if junction temperature exceeds +150°C typically.

(°C/W) θJC (°C/W)

Electrical Specifications V

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Operating Supply Voltage Range 81214 V

Standby Supply Current EN = L - 1.5 3.0 mA

Supply Current I

UNDERVOLTAGE LOCKOUT

Start Threshold 7.5 - 7.95 V

Stop Threshold 7.0 - 7.55 V

Start to Stop Hysteresis 350 400 500 mV

SOFT-START

COMP Rise Time (Note 2) (Note 4) - 1024 - Cycles

OUTPUT VOLTAGE

Output Voltage (Note 3) V

Line Regulation DV

Load Regulation DV

Dynamic Output Current Limiting I

Dynamic Overload Protection Off Time TOFF DCL = L, Output Shorted (Note 4) - 900 - ms

Dynamic Overload Protection On Time TON - 20 - ms

22kHz TONE

Tone Frequency f

Tone Amplitude V

Tone Duty Cycle dc

Tone Rise or Fall Time T

= 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. EN = H, LLC = L,

ENT = L, DCL = L, DSQIN = L, I access to the system.

OUT

OOU

OUT

OUTIO

MAX

tone

, T

EN = LLC = VSEL = ENT = H, No Load - 4.0 8.0 mA

VSEL = L, LLC = L 12.74 13.0 13.26 V

VSEL = L, LLC = H 13.72 14.0 14.28 V

VSEL = H, LLC = L 17.64 18.0 18.36 V

VSEL = H, LLC = H 18.62 19.0 19.38 V

VIN = 8V to 14V; V

= 12mA to 450mA - 50 80 mV

DCL = L, ISEL = L 425 - 550 mA

DCL = L, ISEL = H 775 - 950 mA

ENT = H 20.0 22.0 24.0 kHz

ENT = H 550 680 900 mV

ENT = H (Note 5) 40 50 60 %

ENT = H 5 8 14 µs

= 12mA, unless otherwise noted. See software description section for I2C

OUT

= 13V - 4.0 40.0 mV

OUT

= 18V - 4.0 60.0 mV

OUT

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Electrical Specifications V

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

LINEAR REGULATOR

Drop-Out Voltage Iout = 450mA (Note 4) - 1.2 - V

DSQIN, SEL18V INPUT PINs (Note 6)

Asserted Low --0.8V

Asserted HIGH 1.7 - - V

Input Current -1-µA

CURRENT SENSE

Input Bias Current I

Overcurrent Threshold Static current mode, DCL = H 325 400 500 mV

ERROR AMPLIFIER

Open Loop Voltage Gain A

Gain Bandwidth Product

PWM

Maximum Duty Cycle 90 93 - %

Minimum Pulse Width (Note 4) - 20 - ns

OSCILLATOR

Oscillator Frequency f

THERMAL PROTECTION

Thermal Shutdown

Temperature Shutdown Threshold (Note 4) - 150 -

Temperature Shutdown Hysteresis (Note 4) - 20 -

NOTES:

3. Internal Digital Soft-start

4. Voltage programming signals VSEL and LLC are implemented via the I IO = 450mA.

5. Guaranteed by Design.

6. Unused DSQIN pin should be connected to GND. SEL18V pins is internally connected to GND by a 200K resistor.

= 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. EN = H, LLC = L,

ENT = L, DCL = L, DSQIN = L, I access to the system. (Continued)

BIAS

GBP

(Note 4) 70 88 - dB

(Note 4) 10 - - MHz

Fixed at (10)(f

= 12mA, unless otherwise noted. See software description section for I2C

OUT

- 700 - nA

) 200 220 240 kHz

tone

C bus.

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Functional Pin Description

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SYMBOL FUNCTION

SDA Bidirectional data from/to I

SCL Clock from I

VSW Input of the linear post-regulator.

PGND Dedicated ground for the output gate driver of the PWM.

CS Current sense input; connect Rsc at this pin for desired overcurrent value for the PWM.

SGND Small signal ground for the IC.

AGND Analog ground for the IC.

TCAP Capacitor for setting rise and fall time of the output of the LNB. Use a capacitor value of 1µF or higher.

BYPASS Bypass capacitor for internal 5V.

DSQIN When HIGH this pin enables the internal 22kHz modulation for the LNB, Use this pin for tone enable function for

the LNB.

VCC Main power supply to the chip.

GATE This is the device output of the PWM. This high current driver output is capable of driving the gate of a power FET.

This output is actively held low when Vcc is below the UVLO threshold.

VOUT Output voltage for the LNB.

ADDR Address pin to select two different addresses per voltage level at this pin.

COMP Error amp output used for compensation.

FB Feedback pin for the PWM.

CPVOUT, CPSWIN, CPSWOUT Charge pump connections.

SEL18V When connected HIGH, this pin will change the output of the PWM to 18V.

C bus.

ISL6425

Functional Description

The ISL6425 single output voltage regulator makes an ideal choice for advanced satellite set-top box and personal video recorder applications. Both supply and control voltage outputs for a low noise block (LNB) are available simultaneously in any output configuration. The device utilizes a built-in DC/DC step-converter that, from a single supply source ranging from 8V to 14V, generates the voltage that enables the linear post-regulator to work with a minimum of dissipated power. An undervoltage lockout circuit disables the circuit when V threshold (7.5V typ).

DiSEqC Encoding

The internal oscillator is factory-trimmed to provide a tone of 22kHz in accordance with DISeqC standards. No further adjustment is required. The 22kHz oscillator can be controlled either by the I dedicated pin (DSQIN) that allows immediate DiSEqC data encoding for the LNB. All the functions of this IC are controlled via the I (SR). The same registers can be read back, and two bits will report the diagnostic status. The internal oscillator operates the converters at ten times the tone frequency. The device offers full I

C compatible functionality, 3.3V or 5V, and up to

400kHz operation.

If the Tone Enable (ENT) bit is set LOW through I the DSQIN terminal activates the internal tone signal,

C interface (ENT bit) or by a

C bus by writing to the system registers

drops below a fixed

C, then

modulating the dc output with a 0.3V, 22kHz, symmetrical waveform. The presence of this signal usually gives the LNB information about the band to be received.

Burst coding of the 22kHz tone can be accomplished due to the fast response of the DSQIN input and rapid tone response. This allows implementation of the DiSEqC (EUTELSAT) protocols.

When the ENT bit is set HIGH, a continuous 22kHz tone is generated regardless of the DSQIN pin logic status. The ENT bit must be set LOW when the DSQIN pin is used for DiSEqC encoding.

Linear Regulator

The output linear regulator will sink and source current. This feature allows full modulation capability into capacitive loads as high as 0.25µF. In order to minimize the power dissipation, the output voltage of the internal step-up converter is adjusted to allow the linear regulator to work at minimum dropout.

When the device is put in the shutdown mode (EN = LOW), the PWM power block is disabled. When the regulator block is active (EN = HIGH), the output can be logic controlled to be 13V or 18V (typical) by means of the VSEL bit (Voltage Select) for remote controlling of non-DiSEqC LNBs. Additionally, it is possible to increment by 1V (typical) the selected voltage value to compensate for the excess voltage drop along the coaxial cable (LLC bit HIGH).

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ISL6425

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Output Timing

The programmed output voltage rise and fall times can be set by an external capacitor. The output rise and fall times will be approximately 3400 times the TCAP value. For the recommended range of 0.47µF to 2.2µF, the rise and fall time would be 1.6ms to 7.6ms. Using a 0.47µF capacitor insures the PWM stays below its overcurrent threshold when charging a 120µF VSW filter cap during the worst case 13V to 19V transition. A typical value of 1.0µF is recommended. This feature affects the programmed voltage rise and fall times.

Current Limiting (Only one ISEL option needed)

The current limiting block can operate either statically (simple current clamp) or dynamically. The lower threshold is between 425mA and 550mA (ISEL = L), while the higher threshold is between 775mA and 950mA (ISEL = H). When the DCL (Dynamic Current Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically. That is, as soon as an overload is detected, the output is shutdown for a time t (OLF) bit of the system register is set to HIGH. After this time has elapsed, the output is resumed for a time Ton = 20ms. During Ton, the device output will be current limited to between 575mA and 950mA. At the end of Ton, if the overload is still detected, the protection circuit will cycle again through Toff and Ton. At the end of a full Ton during which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical Ton+Toff time is 920ms as determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in a short circuit condition, still ensuring excellent power-on start-up in most conditions.

However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up, when the dynamic protection is chosen. This can be solved by initiating a power start-up in static mode (DCL = HIGH) and then switching to the dynamic mode (DCL = LOW) after a chosen amount of time. When in static mode, the OLF bit goes HIGH when the current limit threshold at the CS pin reaches 0.45V typ and returns LOW when the overload condition is cleared. The OLF bit will be LOW at the end of initial power-on soft-start.

, typically 900ms. Simultaneously the overload flag

OFF

Thermal Resistance

This IC is protected against overheating. When the junction temperature exceeds 150°C (typical), the step-up converter and the linear regulator are shut off and the overtemp flag (OTF) bit of the SR is set HIGH. Normal operation is resumed and the OTF bit is reset LOW, when the junction is cooled down to 130°C (typical).

independent 13V/18V output voltage selection. When using this pin, the I

C bits should be initialized to 13V status.

TABL E 1 .

C BITS SEL18V O/P VOLTAGE

13V Low 13V

13V High 18V

I2C Bus Interface for ISL6425

(Refer to Philips I2C Specification, Rev. 2.1)

Data transmission from main microprocessor to the ISL6425 and vice versa takes place through the 2 wire I interfaces, consisting of the two lines SDA and SCL. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor. (Pull up resistors to positive supply voltage must be externally connected). When the bus is free, both lines are HIGH. The output stage of ISL6425 will have an open drain/open collector in order to perform the wired-AND function. Data on the I transferred up to 100kbits/s in the standard-mode or up to 400kbits/s in the fast-mode. The level of logic “0” and logic “1” is dependent of associated value of Vdd as per electrical specification table. One clock pulse is generated for each data bit transferred.

Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. (Refer to Figure 1.)

SDA

SCL

DATA LINE

STABLE

DATA VALID

FIGURE 1. DATA VALIDITY

CHANGE OF DATA

ALLOWED

START and STOP Conditions

As shown in the Figure 2, START condition is a HIGH to LOW transition of the SDA line, while SCL is HIGH. The STOP condition is a LOW to HIGH transition on the SDA line, while SCL is HIGH. A STOP condition must be sent before each START condition.

C bus

C bus can be

External Output Voltage Selection

The output voltage can be selected by the I2C bus. Additionally, the QFN package offers a pin (SEL18V) for

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SDA

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SCL

START

CONDITION

FIGURE 2. START AND STOP WAVEFORMS

STOP

CONDITION

Byte Format

Every byte put on the SDA line must be 8 bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit first (MSB).

Acknowledge

The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (Figure 3). The peripheral that acknowledges has to pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. (Of course, set-up and hold times must also be taken into account.)

The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The ISL6425 will not generate the acknowledge if the POWER OK signal from the UVLO is LOW.

SCL

ISL6425

Transmission Without Acknowledge

Avoiding detection of the acknowledgement, the microprocessor can use a simpler transmission; it waits one clock without checking the slave acknowledging, and sends the new data.

This approach, though, is less protected from error and decreases the noise immunity.

ISL6425 Software Description

Interface Protocol

The interface protocol is comprised of the following, as shown below in Table 2:

• A start condition (S)

• A chip address byte (MSB on left; the LSB bit determines read (1) or write (0) transmission) (the assigned I address for the ISL6425 is 0001 00XX)

• A sequence of data (1 byte + Acknowledge)

• A stop condition (P)

TABLE 2. INTERFACE PROTOCOL

S0001000R/WACKData (8 bits)ACKP

Transmitted Data (I

C bus WRITE mode)

When the R/W bit in the chip is set to 0, the main microprocessor can write on the system register (SR1) of the ISL6425 via I

C bus. These will be written by the

microprocessor as shown below.

C slave

SDA

MSB

START

FIGURE 3. ACKNOWLEDGE ON THE I2C BUS

R, W R, W R, W R, W R, W R, W R, W R

SR1 DCL X ENT1 LLC1 VSEL1 EN1 OLF1

R, W R, W R, W R, W R, W R, W R R

SR2 X X X X EN2 OTF X

System Register Format

• R, W = Read and Write bit

• R = Read-only bit All bits reset to 0 at Power-On

ACKNOWLEDGE

FROM SLAVE

TABLE 3. SYSTEM REGISTER 1 (SR1)

TABLE 4. SYSTEM REGISTER 2 (SR2)

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TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION

SR1 DCL ISEL1 ENT1 LLC1 VSEL1 EN1 OLF1 FUNCTION

0 X X X 0 0 X X SR1 is selected

0 X X X 0 0 1 X Vout1 = 13V, Vboost1 = 13V + Vdrop

0 X X X 0 1 1 X Vout1 = 18V, Vboost1 = 18V + Vdrop

0 X X X 1 0 1 X Vout1 = 14V, Vboost1 = 14V + Vdrop

0 X X X 1 1 1 X Vout1 = 19V, Vboost1 = 19V + Vdrop

0 X X 0 X X 1 X 22kHz tone is controlled by the DSQIN pin

0 X X 1 X X 1 X 22kHz tone is ON, the DSQIN input is disabled

0 X 0 X X X 1 X Iout1 = 425mA max.

0 X 1 X X X 1 X Iout1 = 775mA max.

0 1 X X X X 1 X Dynamic current limit NOT selected

0 0 X X X X 1 X Dynamic current limit selected

0 X X X X X 0 X PWM and Linear for channel 1 disabled

SR2 - - - - EN2 OTF - FUNCTION

1 X X X X 0 X X SR2 is selected; to read OTF flag.

NOTE: OTF is a “Read Only” bit and X indicates a “Don’t Care” condition for the function specified.

Received Data (I

C Bus Read Mode)

The ISL6425 can provide to the master a copy of the System Register information via the I

C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following Master generated clock bits, the ISL6425 issues a byte on the SDA data bus line (MSB transmitted first).

At the ninth clock bit the MCU master can:

• Acknowledge the reception, starting in this way the

transmission of another byte from the ISL6425.

• Not acknowledge, stopping the read mode

communication.

While the whole register is read back by the microprocessor, only the two read-only bits, OLF and OTF, convey diagnostic information about the ISL6425.

TABLE 6. READING SYSTEM REGISTERS

DCL ISEL ENT LLC VSEL EN OTF OLF FUNCTION

These bits are read as they were after the last write operation.

0Tj ≤ 130°C, Normal

operation

1 Tj > 150°C, Power

blocks disabled

0 Iout < Imax, Normal

operation

1 Iout > Imax, Overload

protection triggered

Power-On I2C Interface Reset

The I2C interface built into the ISL6425 is automatically reset at power-on. The I logic signal from the UVLO circuit. This signal will go HIGH when chip power is OK. As long as this signal is LOW, the interface will not respond to any I system register SR is initialized to all zeros, thus keeping the power blocks disabled.

C interface block will receive a Power OK

C commands and the

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Once Vcc rises above the UVLO level, the POWER OK signal given to the I

C interface block will be HIGH, the I2C interface becomes operative and the SR can be configured by the main microprocessor. About 400mV of hysteresis is provided in the UVLO threshold to avoid false triggering of the Power-On reset circuit.

C comes up with EN = 0, EN goes HIGH at the same time

as (or later than) all other I

C data for the PWM becomes

valid).

ADDRESS Pin

Connecting this pin to GND forces the chip I2C interface address to 0001000; applying a voltage >2.7V forces the address to 0001001, as shown below.

TABLE 7. ADDRESS PIN CHARACTERISTICS

VAD DR MIN T YP MA X

Vaddr-1

“0001000”

Vaddr-2

“0001001”

0V - 2.0V

2.7V - 5.0V

I2C Electrical Characteristics

TABL E 8 . I2C SPECIFICATIONS

PARAMETER

Input Logic High, VIH

Input Logic Low, VIL

Input Logic Current, IIL

SCL Clock Frequency

TEST

CONDITION MIN TYP MAX

SDA, SCL 0.7 x V

SDA, SCL 0.3 x V

SDA, SCL;

0.4V < Vin < 4.5V

0 100kHz 400kHz

10µA

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Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)

L32.5x5

32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 A1 - - 0.05 A2 - - 1.00 9 A3 0.20 REF 9

b 0.18 0.23 0.30 5,8

D 5.00 BSC D1 4.75 BSC 9 D2 2.95 3.10 3.25 7,8

E 5.00 BSC E1 4.75 BSC 9 E2 2.95 3.10 3.25 7,8

e 0.50 BSC -

k0.25 - - -

L 0.30 0.40 0.50 8 L1 - - 0.15 10

N322 Nd 8 3 Ne 8 8 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation.

10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.

NOTESMIN NOMINAL MAX

Rev. 1 10/02

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FN9176.1

February 8, 2005