Page 1
Multiphase PWM Regulator for AMD Fusion™ Desktop
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35 40 45 50 55
I
OUT
(A)
EFFICIENCY (%)
V
OUT
CORE = 1.1V
V
IN
= 8V
V
IN
= 12V
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
1.12
0 5 10 15 20 25 30 35 40 45 50 55
I
OUT
(A)
V
OUT
(A)
V
IN
= 8V
V
IN
= 12V
V
OUT
CORE = 1.1V
CPUs Using SVI 2.0
ISL6377
The ISL6377 is fully compliant with AMD Fusion™ SVI 2.0 and
provides a complete solution for microprocessor and graphics
processor core power. The ISL6377 controller supports two
Voltage Regulators (VRs) with three integrated gate drivers and
three optional external drivers for maximum flexibility. The Core
VR can be configured for 4-, 3-, 2-, or 1-phase operation while the
Northbridge VR supports 2- or 1-phase configurations. The two
VRs share a serial control bus to communicate with the AMD CPU
and achieve lower cost and smaller board area compared with
two-chip solutions.
The PWM modulator is based on Intersil’s Robust Ripple
Regulator R3 Technology™. Compared to traditional modulators,
the R3 modulator can automatically change switching frequency
for faster transient settling time during load transients and
improved light load efficiency.
The ISL6377 has several other key features. Both outputs
support DCR current sensing with single NTC thermistor for
DCR temperature compensation or accurate resistor current
sensing. Both outputs utilize remote voltage sense, adjustable
switching frequency, OC protection and power good.
Applications
• AMD Fusion CPU/GPU Core Power
•Desktop Computers
Features
• Supports AMD SVI 2.0 Serial Data Bus Interface
• Dual Output Controller with Integrated Drivers
- Two Dedicated Core Drivers
- One Programmable Driver for Either Core or Northbridge
• Precision Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- 0.5V to 1.55V in 6.25mV Steps
- Enhanced Load Line Accuracy
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Programmable 1-, 2-, 3- or 4-Phase for the Core Output and
1- or 2-Phase for the Northbridge Output
• Adaptive Body Diode Conduction Time Reduction
• Superior Noise Immunity and Transient Response
• Output Current and Voltage Telemetry
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
•Programmable Slew Rate
• Programmable VID Offset and Droop on Both Outputs
• Programmable Switching Frequency for Both Outputs
• Excellent Dynamic Current Balance Between Phases
• Protection: OCP/WOC, OVP, PGOOD, and Thermal Monitor
• Small Footprint 48 Ld 6x6 QFN Package
- Pb-Free (RoHS Compliant)
Core Performance
August 6, 2012
FN8336.0
FIGURE 1. EFFICIENCY vs LOAD
1
FIGURE 2. V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Intersil (and design) and R3 Technology are trademarks owned by Intersil Corporation or one of its subsidiaries.
1-888-INTERSIL or 1-888-468-3774
All other trademarks mentioned are the property of their respective owners.
| Copyright Intersil Americas Inc. 2012. All Rights Reserved
OUT
vs LOAD
Page 2
ISL6377
NB_PH1
NB_PH2
FIGURE 3. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
BOOTX
UGATEX
PHASEX
LGATEX
BOOT2
UGATE2
PHASE2
LGATE2
BOOT1
UGATE1
PHASE1
LGATE1
PWM_Y
ISL6377
ISUMP
ISUMN
PH1
PH2
PH3
VO1
VO2
VO3
GND PAD
FB_NB
COMP_NB
VSEN_NB
VNB_SENSE
VDDP
PGOOD
ISEN1
ISEN2
ISEN3
ENABLE
PH1
PH2
PH3
VCORE
PH2
ISL6208
VO2
VO1
+12V
VO3
PH1
+12V
+12V
VO1
PH3
PH1
+12V
VNB
VDD
PWM2_NB
ISL6208
VNB1
NB_PH1
VNB2
NB_PH2
ISEN1_NB
ISEN2_NB
ISUMP_NB
ISUMN_NB
NB_PH1
NB_PH2
VNB1
VNB2
NTC_NB
IMON
IMON_NB
PWROK
SVT
SVD
µP
SVC
VDDIO
NTC
VR_HOT_L
THERMAL INDICATOR
FCCM_NB
VCORE_SENSE
FB
COMP
VSEN
RTN
+12V
NTC
NTC
Cn
Cn
Ri
Ri
*OPTIONAL
*
*
*OPTIONAL
*
*
ISEN4
PH4
VO4
PH4
PWM4
ISL6208
+12V
VO4
PH4
PGOOD_NB
Simplified Application Circuit for High Power CPU Core
2
FN8336.0
August 6, 2012
Page 3
ISL6377
FIGURE 4. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
BOOTX
UGATEX
PHASEX
LGATEX
BOOT2
UGATE2
PHASE2
LGATE2
BOOT1
UGATE1
PHASE1
LGATE1
ISL6377
GND PAD
VCORE_SENSE
FB_NB
COMP_NB
VSEN_NB
VNB_SENSE
VDDP
PGOOD
ENABLE
VCORE
PH2
ISL6208
VO2
VO1
+12V
VNB1
PH1
+12V
+12V
VO1
NB_PH1
PH1
+12V
VNB
VDD
PWM2_NB
ISL6208
V03
PH3
VNB2
NB_PH2
NTC_NB
IMON
IMON_NB
PWROK
SVT
SVD
µP
SVC
VDDIO
NTC
VR_HOT_L
THERMAL INDICATOR
FB
COMP
VSEN
RTN
FCCM_NB
PWM_Y
+12V
NB_PH1
NB_PH2
ISEN1_NB
ISEN2_NB
ISUMP_NB
ISUMN_NB
NB_PH1
NB_PH2
VNB1
VNB2
ISUMP
ISUMN
PH1
PH2
PH3
VO1
VO2
VO3
ISEN1
ISEN2
ISEN3
PH1
PH2
PH3
NTC
NTC
Cn
Cn
Ri
Ri
*OPTIONAL
*
*
*OPTIONAL
*
*
PWM4
ISL6208
V04
PH4
+12V
ISEN4PH4
VO4
PH4
PGOOD_NB
Simplified Application Circuit with 3 Internal Drivers Used for Core
FN8336.0
August 6, 2012
3
Page 4
Simplified Application Circuit for Mid-Power CPUs [3+1 Configuration]
FIGURE 5. TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING
BOOT2
UGATE2
PHASE2
LGATE2
BOOT1
UGATE1
PHASE1
LGATE1
PWM2_NB
ISL6377
ISUMP
ISUMN
VP1
VP2
VN1
VN2
GND PAD
FB_NB
COMP_NB
VSEN_NB
VNB_SENSE
VDDP
PGOOD
ISEN1
ISEN2
ISEN3
ENABLE
VP1
VP2
VCORE
VP2
VN2
+12V
+12V
VNB
VDD
PWM_Y
ISL6208
NBN
NBP
NTC_NB
IMON
IMON_NB
PWROK
SVT
SVD
µP
SVC
VDDIO
NTC
VR_HOT_L
Thermal Indicator
FCCM_NB
VCORE_SENSE
FB
COMP
VSEN
RTN
+12V
+5V
ISEN1_NB
ISEN2_NB
ISUMP_NB
ISUMN_NB
NBP
NBN
10kΩ*
OPEN
NTC
NTC
* Resistor required or ISEN1_NB
will pull HIGH if left open and
disable Channel 1.
VP1
VN1
Cn
Cn
Ri
Ri
*OPTIONAL
*
*
*OPTIONAL
*
*
PWM4
OPEN
ISEN4
+5V
BOOTX
UGATEX
PHASEX
LGATEX
+12V
VP3
VN3
VP3
VN3
VP3
PGOOD_NB
ISL6377
4
FN8336.0
August 6, 2012
Page 5
Block Diagram
RTN
E/A
FB
IDROOP
CURRENT
SENSE
ISUMP
ISUMN
COMP
DRIVER
DRIVER
LGATE1
PHASE1
UGATE1
BOOT1
VCCP
OV FAULT
PGOOD
_
+
_
+
+
+
DRIVER
DRIVER
LGATE2
PHASE2
UGATE2
BOOT2
IBAL FAULT
OC FAULT
PWM_Y
ISEN3
ISEN2
ISEN1
CURRENT
BALANCING
DIGITAL
INTERFACE
PWROK
SVC
SVD
DRIVER
DRIVER
LGATEX
PHASEX
UGATEX
BOOTX
OV FAULT
PGOOD_NB
CORE_I
DAC1
NB_I
DAC2
TEMP
MONITOR
NTC_NB
NTC
VR_HOT_L
T_MONITOR
OFFSET
FREQ
SLEWRATE
CONFIG
PROG
ENABLE
TELEMETRY
D/A
A/D IDROOP
IDROOP_NB
RTN
E/A
FB_NB
IDROOP_NB
CURRENT
SENSE
ISUMP_NB
ISUMN_NB
COMP_NB
VR2
MODULATOR
_
+
_
+
+
+
VR1
MODULATOR
VDD
GND
ISEN1_NB
ISEN2_NB
CURRENT
BALANCING
IBAL FAULT
PWM2_NB
SVT
FLOATING
DRIVER &
PWM
CONFIG
LOGIC
OC FAULT
CURRENT
A/D
IMON
IMON_NB
VSEN
VSEN_NB
VDDIO
CORE_I
NB_I
CORE_V
NB_V
NB_V
VOLTAGE
A/D
CORE_V
VOLTAGE
A/D
ISEN4
PWM4
FCCM_NB
ISL6377
Σ
5
Σ
FN8336.0
August 6, 2012
Page 6
ISL6377
1
48
GND PAD
(BOTTOM)
C
O
M
P
_
N
B
I
S
U
M
P
_
N
B
2
I
S
E
N
1
_
N
B
3
ISEN2_NB
4
IMON_NB
5
6
SVC
7
PWROK
8
SVD
9
VDDIO
10
SVT
11
VR_HOT_L
12
NTC
47
P
G
O
O
D
_
N
B
46
F
C
C
M
_
N
B
45
V
S
E
N
_
N
B
44
P
W
M
2
_
N
B
43
L
G
A
T
E
X
42 41 40
N
T
C
_
N
B
39
P
H
A
S
E
X
38
U
G
A
T
E
X
37
B
O
O
T
X
36
PWM4
35
34
BOOT2
33
UGATE2
32
PHASE2
31
LGATE2
30
VDDP
29
VDD
28
PWM_Y
27
LGATE1
26
PHASE1
25
UGATE1
1
3
I
S
E
N
1
1
4
I
S
U
M
P
1
5
I
S
U
M
N
1
6
V
S
E
N
1
7
I
M
O
N
1
8
F
B
192
0
C
O
M
P
2
1
I
S
E
N
4
2
2
P
G
O
O
D
2
3
R
T
N
37
2
4
I
S
E
N
2
ENABLE
I
S
E
N
3
F
B
_
N
B
I
S
U
M
N
_
N
B
B
O
O
T
1
Pin Configuration
ISL6377
(48 LD QFN)
TOP VIEW
Pin Descriptions
PIN NUMBER SYMBOL DESCRIPTION
1 ISEN2_NB Individual current sensing for Channel 2 of the Northbridge VR. When ISEN2_NB is pulled to +5V, the
controller will disable Channel 2 and the Northbridge VR will run single-phase.
2 NTC_NB Thermistor input to VR_HOT_L circuit to monitor Northbridge VR temperature.
3 IMON_NB Northbridge output current monitor. A current proportional to the Northbridge VR output current is
sourced from this pin.
4SVC
5 VR_HOT_L Thermal indicator signal to AMD CPU. Thermal overload open drain output indicator active LOW.
6 SVD Serial VID data bidirectional signal from the CPU processor master device to the VR.
7 VDDIO VDDIO is the processor memory interface power rail and this pin serves as the reference to the controller
8 SVT Serial VID Telemetry (SVT) data line input to the CPU from the controller IC. Telemetry and VID-on-the-fly
9 ENABLE Enable input. A high level logic on this pin enables both VRs.
10 PWROK System power-good input. When this pin is high, the SVI 2 interface is active and the I
11 NTC Thermistor input to VR_HOT_L circuit to monitor Core VR temperature.
12 ISEN4 ISEN4 is the individual current sensing for Channel 4. When ISEN4 is pulled to +5V, the controller disables
13 ISEN3 ISEN3 is the individual current sensing for Channel 3. When ISEN3 is pulled to +5V, the controller disables
14 ISEN2 Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to +5V, the controller
6
Serial VID clock input from the CPU processor master device.
IC for this processor I/O signal level.
complete signal provided from this pin.
running. While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This
pin must be low prior to the ISL6377 PGOOD output going high per the AMD SVI 2.0 Controller Guidelines.
Channel 4, and the Core VR runs in three-phase mode.
Channel 3, and the Core VR runs in two-phase mode.
disables Channel 2, and the Core VR runs in single-phase mode.
2
C protocol is
August 6, 2012
FN8336.0
Page 7
ISL6377
Pin Descriptions (Continued)
PIN NUMBER SYMBOL DESCRIPTION
15 ISEN1 Individual current sensing for Channel 1 of the Core VR. If ISEN2 is tied to +5V, this pin cannot be left
open and must be tied to GND with a 10kΩ resistor. If ISEN1 is tied to +5V, the Core portion of the IC is
shut down.
16 ISUMP Non-inverting input of the transconductance amplifier for current monitor and load line of Core output.
17 ISUMN Inverting input of the transconductance amplifier for current monitor and load line of Core output.
18 VSEN Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die.
19 RTN Output voltage sense return pin for both Core VR and Northbridge VR. Connect to the -sense pin of the
microprocessor die.
20 IMON Core output current monitor. A current proportional to the Core VR output current is sourced from this pin.
21 FB Output voltage feedback to the inverting input of the Core controller error amplifier.
22 COMP Core controller error amplifier output. A resistor from COMP to GND sets the Core VR offset voltage.
23 PGOOD Open-drain output to indicate the Core portion of the IC is ready to supply regulated voltage. Pull up
24 BOOT1 Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged,
25 UGATE1 Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UGATE1 pin to the gate
26 PHASE1 Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Conne ct the PHASE1 pin to the
27 LGATE1 Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LGATE1 pin to the gate
28 PWM_Y Floating PWM output used for either Channel 3 of the Core VR or Channel 1 of the Northbridge VR
29 VDD 5V bias power. A resistor [2Ω] and a decoupling capacitor should be used from the +5V supply. A high
30 VDDP Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1µF
31 LGATE2 Output of the Phase 2 low-side MOSFET gate driver of the Core VR. Connect the LGATE2 pin to the gate
32 PHASE2 Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PHASE2
33 UGATE2 Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UGATE2 pin to the gate
34 BOOT2 Connect an MLCC capacitor across the BOOT2 and PHASE2 pins. The boot capacitor is charged, through
35 PWM4 PWM output of Channel 4 of the Core VR. Disabled if ISEN4 is tied to +5V.
36 BOOTX Boot connection of the programmable internal driver used for either Channel 3 of the Core VR or
37 UGATEX High-side MOSFET gate driver portion of the programmable internal driver used for either Channel 3 of
externally to VDD or 3.3V through a resistor.
through an internal boot diode connected from the VDDP pin to the BOOT1 pin, each time the PHASE1
pin drops below VDDP minus the voltage dropped across the internal boot diode.
of the Phase 1 high-side MOSFET(s).
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of
Phase 1.
of the Phase 1 low-side MOSFET(s).
depending on the FCCM_NB resistor connected between FCCM_NB and GND.
quality, X7R dielectric MLCC capacitor is recommended.
of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended.
of the Phase 2 low-side MOSFET(s).
pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase 2.
of the Phase 2 high-side MOSFET(s).
an internal boot diode connected from the VDDP pin to the BOOT2 pin, each time the PHASE2 pin drops
below VDDP minus the voltage dropped across the internal boot diode.
Channel 1 of the Northbridge VR based on the configuration state selected by the FCCM_NB resistor.
Connect an MLCC capacitor across the BOOT1X and the PHASEX pins. The boot capacitor is charged,
through an internal boot diode connected from the VDDP pin to the BOOTX pin, each time the PHASEX
pin drops below VDDP minus the voltage dropped across the internal boot diode.
the Core VR or Channel 1 of the Northbridge VR based on the configuration state selected by the
FCCM_NB resistor. Connect the UGATEX pin to the gate of the high-side MOSFET(s) for either Phase 3 of
the Core VR or Phase 1 of the Northbridge VR based on the configuration state selected.
7
FN8336.0
August 6, 2012
Page 8
ISL6377
Pin Descriptions (Continued)
PIN NUMBER SYMBOL DESCRIPTION
38 PHASEX Phase connection of the programmable internal driver used for either Channel 3 of the Core VR or
Channel 1 of the Northbridge VR based on the configuration state selected by the FCCM_NB resistor.
Current return path for the high-side MOSFET gate driver of the floating internal driver. Connect the
PHASEX pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the
output inductor of either Phase 3 of the Core VR or Phase 1 of the Northbridge VR based on the
configuration state selected.
39 LGATEX Low-side MOSFET gate driver portion of floating internal driver used for either Channel 3 of the Core VR
or Channel 1 of the Northbridge VR based on the configuration state selected by the FCCM_NB resistor.
Connect the LGATEX pin to the gate of the low-side MOSFET(s) for either Phase 3 of the Core VR or Phase
1 of the Northbridge VR based on the configuration state selected.
40 PWM2_NB PWM output for Channel 2 of the Northbridge VR. Disabled when ISEN2_NB is tied to +5V.
41 FCCM_NB Diode emulation control signal for Intersil MOSFET Drivers. When FCCM_NB is LOW, diode emulation at
42 PGOOD_NB Open-drain output to indicate the Northbridge portion of the IC is ready to supply regulated voltage.
43 COMP_NB Northbridge VR error amplifier output. A resistor from COMP_NB to GND sets the Northbridge VR offset
44 FB_NB Output voltage feedback to the inverting input of the Northbridge controller error amplifier.
45 VSEN_NB Output voltage sense pin for the Northbridge controller. Connect to the +sense pin of the microprocessor
46 ISUMN_NB Inverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR.
47 ISUMP_NB Non-inverting input of the transconductance amplifier for current monitor and load line of the
48 ISEN1_NB Individual current sensing for Channel 1 of the Northb ridge VR . If ISEN2_NB is tied to +5V, this pin cann ot
GND (Bottom Pad) Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.
the driver this pin connects to is allowed. A resistor from FCCM_NB pin to GND configures the PWM_Y
and floating internal gate driver [BOOTX, UGATEX, PHASEX, LGATEX pins] to support Phase 3 of the Core
VR and Phase 1 of the Northbridge VR. The FCCM_NB resistor value also is used to set the slew rate for
the Core VR and Northbridge VR.
Pull-up externally to VDDP or 3.3V through a resistor.
voltage and is used to set the switching frequency for the Core VR and Northbridge VR.
die.
Northbridge VR.
be left open and must be tied to GND with a 10kΩ resistor. If ISEN1_NB is tied to +5V, the Northbridge
portion of the IC is shutdown.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL6377HRZ ISL6377 HRZ -10 to +100 48 Ld 6x6 QFN L48.6x6B
ISL6377IRZ ISL6377 IRZ -40 to +85 48 Ld 6x6 QFN L48.6x6B
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6377
8
PART
MARKING
TEMP.
RANGE (°C)
for details on reel specifications.
. For more information on MSL please see tech brief TB363.
PACKAGE
(Pb-free)
PKG.
DWG. #
August 6, 2012
FN8336.0
Page 9
ISL6377
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Start-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Differential Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Resistor Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VR Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Floating DriverX and PWM_Y Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VID-on-the-Fly Slew Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AMD Serial VID Interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pre-PWROK Metal VID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SVI Interface Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SVI Data Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SVI Bus Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Dynamic Load Line Slope Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Dynamic Offset Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Telemetry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Overcurrent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Current-Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Overvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal Monitor [NTC, NTC_NB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Fault Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interface Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Load Line Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Thermal Monitor Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9
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ISL6377
Absolute Maximum Ratings Thermal Information
Supply Voltage, V
Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)
Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . .PHASE - 0.3V (DC) to BOOTPHASE - 5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Open Drain Outputs, PGOOD, PGOOD_NB, VR_HOT_L. . . . . . . -0.3V to +7V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379
5. For θ
DD, VDDP
.
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
-0.3V to +9V (<10ns)
(<20ns Pulse Width, 10µJ) to BOOT LGATE Voltage
-2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V
Thermal Resistance (Typical) θ
48 Ld QFN Package (Notes 4, 5) . . . . . . . . 29 3.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(°C/W) θJC (°C/W)
JA
Recommended Operating Conditions
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Input Supply Voltage, V
Ambient Temperature HRZ . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V to 12.6V
IN
IRZ . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Electrical Specifications Operating Conditions: V
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +100°C.
PARAMETER SYMBOL TEST CONDITIONS
INPUT POWER SUPPLY
+5V Supply Current I
POWER-ON-RESET THRESHOLDS
VDD POR Threshold VDD_POR
SYSTEM AND REFERENCES
System Accuracy HRZ
Maximum Output Voltage V
Minimum Output Voltage V
CHANNEL FREQUENCY
Nominal Channel Frequency f
Adjustment Range 300 450 kHz
AMPLIFIERS
Current-Sense Amplifier Input Offset HRZ I
Error Amp DC Gain A
Error Amp Gain-Bandwidth Product GBW C
ISEN
Input Bias Current 20 nA
VDD
VDD_POR
%Error (V
IRZ
%Error (V
OUT(max)
OUT(min)
SW(nom)
IRZ I
v0
ENABLE = 1V 8 11 mA
ENABLE = 0V 1 µA
VDD rising 4.35 4.5 V
r
VDD falling 4.00 4.15 V
f
No load; closed loop, active mode range,
VID = 0.75V to 1.55V -0.5 +0.5 %
OUT)
VID = 0.25V to 0.74375V -10 +10 mV
No load; closed loop, active mode range,
)
VID = 0.75V to 1.55V -0.8 +0.8 %
OUT
VID = 0.25V to 0.74375V -12 +12 mV
VID = [00000000] 1.55 V
VID = [11111111] 0.0 V
= 5V, TA = -10°C to +100°C (HRZ), TA = -40°C to +85°C (IRZ), fSW = 300kHz, unless
DD
MIN
(Note 6) TYP
280 300 320 kHz
= 0A -0.15 +0.15 mV
FB
= 0A -0.20 +0.20 mV
FB
119 dB
= 20pF 17 MHz
L
MAX
(Note 6) UNITS
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ISL6377
Electrical Specifications Operating Conditions: V
= 5V, TA = -10°C to +100°C (HRZ), TA = -40°C to +85°C (IRZ), fSW = 300kHz, unless
DD
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +100°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
POWER-GOOD (PGOOD & PGOOD_NB) AND PROTECTION MONITORS
I
PGOOD Low Voltage V
PGOOD Leakage Current I
OL
OH
= 4mA 0.4 V
PGOOD
PGOOD = 3.3V -1 1 µA
PWROK High Threshold 750 mV
VR_HOT_L Pull-down 11 Ω
PWROK Leakage Current 1 µA
VR_HOT_L Leakage Current 1 µA
GATE DRIVER
UGATE Pull-Up Resistance R
UGATE Source Current I
UGATE Sink Resistance R
UGATE Sink Current I
LGATE Pull-Up Resistance R
LGATE Source Current I
LGATE Sink Resistance R
LGATE Sink Current I
UGATE to LGATE De ad ti me t
LGATE to UGATE De ad ti me t
UGPU
UGSRC
UGPD
UGSNK
LGPU
LGSRC
LGPD
LGSNK
UGFLGR
LGFUGR
200mA Source Current 1.0 1.5 Ω
UGATE - PHASE = 2.5V 2.0 A
250mA Sink Current 1.0 1.5 Ω
UGATE - PHASE = 2.5V 2.0 A
250mA Source Current 1.0 1.5 Ω
LGATE - VSSP = 2.5V 2.0 A
250mA Sink Current 0.5 0.9 Ω
LGATE - VSSP = 2.5V 4.0 A
UGATE falling to LGATE rising, no load 23 ns
LGATE falling to UGATE rising, no load 28 ns
PROTECTION
Overvoltage Threshold OV
Undervoltage Threshold OV
H
H
VSEN rising above setpoint for >1µs 275 325 375 mV
VSEN falls below setpoint for >1µs 275 325 375 mV
Current Imbalance Threshold One ISEN above another ISEN for >1.2ms 9 mV
Way Overcurrent Trip Threshold
[IMONx Current Based Detection]
Overcurrent Trip Threshold
[IMONx Voltage Based Detection]
IMONx
V
IMONx_OCP
WOC
All states, I
All states, I
I
= 11.25µA, R
IMONx
DROOP
DROOP
= 60µA, R
= 45µA,
= 135kΩ
IMON
= 135kΩ 15 µA
IMON
1.485 1.51 1.535 V
LOGIC THRESHOLDS
ENABLE Input Low V
ENABLE Input High V
ENABLE Leakage Current I
ENABLE
IL
IH
V
IH
HRZ 1.6 V
IRZ 1.65 V
ENABLE = 0V -1 01µA
1 V
ENABLE = 1V 18 35 µA
SVT Impedance 50 Ω
SVC, SVD Input Low V
SVC, SVD Input High V
IL
IH
% of VDDIO 30 %
% of VDDIO 70 %
SVC, SVD Leakage ENABLE = 0V, SVC, SVD = 0V and 1V -1 1 µA
ENABLE = 1V, SVC, SVD = 1V -5 1 µA
ENABLE = 1V, SVC, SVD = 0V -35 -20 -5 µA
PWM
PWM Output Low V
PWM Output High V
0L
0H
Sinking 5mA 1.0 V
Sourcing 5mA 3.5 V
PWM Tri-State Leakage PWM = 2.5V 0.5 µA
THERMAL MONITOR
NTC Source Current NTC = 0.6V 27 30 33 µA
NTC Thermal Warning Voltage 600 640 680 mV
11
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ISL6377
PWM
UGATE
LGATE
1V
1V
t
UGFLGR
t
RL
t
FU
t
RU
t
FL
t
LGFUGR
Electrical Specifications Operating Conditions: V
= 5V, TA = -10°C to +100°C (HRZ), TA = -40°C to +85°C (IRZ), fSW = 300kHz, unless
DD
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +100°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
NTC Thermal Warning Voltage
MIN
(Note 6) TYP
20 mV
MAX
(Note 6) UNITS
Hysteresis
NTC Thermal Shutdown Voltage 530 580 630 mV
SLEW RATE
VID-on-the-Fly Slew Rate Maximum Programmed 16 20 24 mV/µs
Minimum Programmed 8 10 12 mV/µs
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Gate Driver Timing Diagram
12
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ISL6377
FIGURE 6. R
3
™ MODULATOR CIRCUIT
CRM
GMVO
MASTER
CLOCK
VW
COMP
MASTER
CLOCK
PHASE
SEQUENCER
CLOCK1
CLOCK2
R
I
L1
GM
CLOCK1
PHASE1
CRS1
VW
S
Q
PWM1
L1
R
I
L2
GM
CLOCK2
PHASE2
CRS2
VW
S
Q
PWM2
L2
CO
VO
VCRM
VCRS1
VCRS2
MASTER CLOCK CIRCUIT
SLAVE CIRCUIT 1
SLAVE CIRCUIT 2
R
I
L3
GM
CLOCK3
PHASE3
CRS3
VW
S
Q
PWM3
L3
VCRS3
SLAVE CIRCUIT 3
CLOCK3
FIGURE 7. R
3
™ MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
COMP
VCRM
MASTER
CLOCK
PWM1
VW
CLOCK1
PWM2
CLOCK2
HYSTERETIC
WINDOW
PWM3
VCRS3
CLOCK3
VCRS2
VCRS1
VW
Theory of Operation
Multiphase R3™ Modulator
The ISL6377 is a multiphase regulator implementing two voltage
regulators, CORE VR and Northbridge (NB) VR, on one chip
controlled by AMD’s™ SVI2™ protocol. The CORE VR can be
programmed for 1-, 2-, 3- or 4-phase operation. The Northbridge VR
can be configured for 1- or 2-phase operation. Both regulators use
the Intersil patented R
R3™ modulator combines the best features of fixed frequency
PWM and hysteretic PWM while eliminating many of their
shortcomings. Figure 6 conceptually shows the multiphase R
modulator circuit, and Figure 7 shows the operation principles.
3
™ (Robust Ripple Regulator) modulator. The
3
™
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C
to g
, where gm is a gain factor. Crm voltage V
mVo
with a current source equal
rm
CRM
is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If the CORE VR is in
3-phase mode, the master clock signal is distributed to the three
phases, and the Clock 1~3 signals will be 120° out-of-phase. If
the Core VR is in 2-phase mode, the master clock signal is
distributed to Phases 1 and 2, and the Clock1 and Clock2 signals
will be 180° out-of-phase. If the Core VR is in 1-phase mode, the
master clock signal will be distributed to Phase 1 only and be the
Clock1 signal.
13
Each slave circuit has its own ripple capacitor C
, whose voltage
rs
mimics the inductor ripple current. A gm amplifier converts the
inductor voltage into a current source to charge and discharge
. The slave circuit turns on its PWM pulse upon receiving the
C
rs
clock signal, and the current source charges Crs. When Crs
voltage V
and the current source discharges C
Since the controller works with V
hits VW, the slave circuit turns off the PWM pulse,
Crs
.
rs
, which are large amplitude
crs
and noise-free synthesized signals, it achieves lower phase jitter
than conventional hysteretic mode and fixed PWM mode
controllers. Unlike conventional hysteretic mode converters, the
error amplifier allows the ISL6377 to maintain a 0.5% output
voltage accuracy.
Figure 8 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency. This allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the COMP voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the ISL6377 excellent response
speed.
The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.
FN8336.0
August 6, 2012
Page 14
ISL6377
FIGURE 8. R
3
™ MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
COMP
V
CRM
MASTER
CLOCK
PWM1
VCRS1
VW
CLOCK1
PWM2
VCRS2
CLOCK2
PWM3
CLOCK3
VCRS3
VW
UGATE
PHASE
IL
LGATE
FIGURE 9. DIODE EMULATION
IL
IL
V
CRS
IL
V
CRS
V
CRS
VW
CCM/DCM BOUNDARY
LIGHT DCM
DEEP DCM
VW
VW
FIGURE 10. PERIOD STRETCHING
Figure 10 shows the operation principle in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size and therefore is the same, making the inductor
current triangle the same in the three cases. The ISL6377 clamps
the ripple capacitor voltage V
inductor current. It takes the COMP voltage longer to hit V
naturally stretching the switching period. The inductor current
triangles move farther apart, such that the inductor current
average value is equal to the load current. The reduced switching
frequency helps increase light-load efficiency.
in DE mode to make it mimic the
CRS
CRS
,
Diode Emulation and Period Stretching
The ISL6377 can operate in diode emulation (DE) mode to
improve light-load efficiency. In DE mode, the low-side MOSFET
conducts when the current is flowing from source to drain and
does not allow reverse current, thus emulating a diode. As Figure 9
shows, when LGATE is on, the low-side MOSFET carries current,
creating negative voltage on the phase node due to the voltage
drop across the on-resistance. The ISL6377 monitors the current
by monitoring the phase node voltage. It turns off LGATE when the
phase node voltage reaches zero to prevent the inductor current
from reversing the direction and creating unnecessary power loss.
If the load current is light enough, as Figure 9 shows, the inductor
current reaches and stays at zero before the next phase node
pulse, and the regulator is in discontinuous conduction mode
(DCM). If the load current is heavy enough, the inductor current
will never reach 0A, and the regulator is in CCM, although the
controller is in DE mode.
14
Channel Configuration
Individual PWM channels of either VR can be disabled by
connecting the ISENx pin of the channel not required to +5V. For
example, placing the controller in a 3+1 configuration, as shown
in Figure 5, requires ISEN4 of the Core VR and ISEN2 of the
Northbridge VR to be tied to +5V. This disables Channel 4 of the
Core VR and Channel 2 of the Northbridge VR. ISEN1_NB must
be tied through a 10kΩ resistor to GND to prevent this pin from
pulling high and disabling the channel.
Connecting ISEN1 or ISEN1_NB to +5V will disable the
corresponding VR output. This feature allows debug of individual
VR outputs.
Power-On Reset
Before the controller has sufficient bias to guarantee proper
operation, the ISL6377 requires a +5V input supply tied to VDD
and VDDP to exceed the VDD rising power-on reset (POR)
threshold. Once this threshold is reached or exceeded, the
ISL6377 has enough bias to check the state of the SVI inputs
once ENABLE is taken high. Hysteresis between the rising and
the falling thresholds assure the ISL6377 does not inadvertently
turn off unless the bias voltage drops substantially (see
“Electrical Specifications” on page 10). Note that VIN must be
present for the controller to drive the output voltage.
FN8336.0
August 6, 2012
Page 15
ISL6377
VDD
SVC
SVD
ENABLE
PWROK
V
CORE
/ V
CORE_NB
1
7 8
FIGURE 11. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
PGOOD & PGOOD_NB
3
4
2
5
6
METAL_VID
V_SVI
Interval 1 to 2: ISL6377 waits to POR.
Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.
Interval 3 to 4: ENABLE locks pre-Metal VID code. Both outputs soft-start to this level.
Interval 4 to 5: PGOOD signal goes HIGH, indicating proper operation.
Interval 6 to 7: SVC and SVD data lines communicate change in VID code.
Interval 7 to 8: ISL6377 responds to VID-ON-THE-FLY code change and issues a VOTF for positive VID changes.
Interval 5 to 6: PGOOD and PGOOD_NB high is detected and PWROK is taken high. The ISL6377 is prepared for SVI commands.
SVT
TELEMETRY
TELEMETRY
VOTF
Post 8: Telemetry is clocked out of the ISL6377.
VDD
ENABLE
DAC
8ms
Metal VID
SLEW RATE
VID COMMAND
VOLTAGE
PGOOD
PWROK
VIN
FIGURE 12. TYPICAL SOFT-START WAVEFORMS
Start-up Timing
With VDD above the POR threshold, the controller start-up
sequence begins when ENABLE exceeds the logic high threshold.
Figure 12 shows the typical soft-start timing of the Core and
Northbridge VRs. Once the controller registers ENABLE as a high,
the controller checks that state of a few programming pins
during the typical 8ms delay prior to beginning soft-starting the
Core and Northbridge outputs. The pre-PWROK Metal VID is read
from the state of the SVC and SVD pins and programs the DAC,
the programming resistors on COMP, COMP_NB, and FCCM_NB
are read to configure internal drivers, switching frequency, slew
rate, output offsets. These programming resistors are discussed
in subsequent sections. The ISL6377 use a digital soft-start to
ramp up the DAC to the Metal VID level programmed. The
soft-start slew rate is programmed by the FCCM_NB resistor
which is used to set the VID-on-the-Fly slew rate as well. See the
VID-on-the-Fly Slew Rate Selection section for more details on
selecting the FCCM_NB resistor. PGOOD is asserted high at the
end of the soft-start ramp.
15
Voltage Regulation and Load Line
Implementation
After the soft-start sequence, the ISL6377 regulates the output
voltages to the pre-PWROK metal VID programmed, see Table 6.
The ISL6377 controls the no-load output voltage to an accuracy of
±0.5% over the range of 0.75V to 1.55V. A differential amplifier
allows voltage sensing for precise voltage regulation at the
microprocessor die.
FN8336.0
August 6, 2012
Page 16
FIGURE 13. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
X 1
E/A
Σ
DAC
SVID[7:0]
Rdroop
Idroop
VDAC
Vdroop
FB
COMP
VCC
SENSE
VSS
SENSE
RTN
VSS
INTERNAL TO IC
“CATCH” RESISTOR
“CATCH” RESISTOR
VR LOCAL VO
+
-
+-
+
+
-
SVC
SVD
I
sum
V
Cn
R
i
---------- -
=
(EQ. 1)
I
droop
5
4
-- -
I
sum
×
5
4
-- -
V
Cn
R
i
---------- -
×==
(EQ. 2)
V
droopRdroopIdroop
×=
(EQ. 3)
VCC
SENSE
V+
droop
V
DAC
VSS
SENSE
+=
(EQ. 4)
VCC
SENSE
VSS
SENSE
– V
DACRdroopIdroop
×–=
(EQ. 5)
FIGURE 14. CURRENT BALANCING CIRCUIT
V
O
ISEN3
L3
R
isen
C
isen
ISEN2
R
isen
C
isen
ISEN1
R
isen
C
isen
L2
L1
R
dcr3
R
dcr2
R
dcr1
PHASE3
PHASE2
PHASE1
I
L3
I
L2
I
L1
R
pcb3
R
pcb2
R
pcb1
L4
R
dcr4
I
L4
R
pcb4
PHASE4
R
isen
C
isen
ISEN4
V
ISEN1
R
dcr1Rpcb1
+()IL1×=
(EQ. 6)
V
ISEN2
R
dcr2Rpcb2
+()IL2×=
(EQ. 7)
V
ISEN3
R
dcr3Rpcb3
+()IL3×=
(EQ. 8)
V
ISEN4
R
dcr4Rpcb4
+()IL4×=
(EQ. 9)
ISL6377
amplifier regulates the inverting and non-inverting input voltages
to be equal as shown in Equation 4:
Rewriting Equation 4 and substituting Equation 3 gives Equation 5
the exact equation required for load-line implementation.
The VCC
The feedback is open circuit in the absence of the processor. As
Figure 13 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and to add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10Ω~100Ω, provide voltage
feedback if the system is powered up without a processor installed.
SENSE
and VSS
signals come from the processor die.
SENSE
As the load current increases from zero, the output voltage
droops from the VID programmed value by an amount
proportional to the load current, to achieve the load line. The
ISL6377 can sense the inductor current through the intrinsic DC
Resistance (DCR) of the inductors, as shown in Figures 3 and 4,
or through resistors in series with the inductors as shown in
Figure 5. In both methods, capacitor C
voltage represents the
n
total inductor current. An internal amplifier converts Cn voltage
into an internal current source, I
, with the gain set by resistor
sum
Ri, see Equation 1.
The I
current is used for load line implementation, current
sum
monitoring on the IMON pins and overcurrent protection.
Figure 13 shows the load-line implementation. The ISL6377
drives a current source (I
of the I
current, as described by Equation 2.
sum
) out of the FB pin which is a ratio
droop
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding, thus sustaining the load-line accuracy with
reduced cost.
flows through resistor R
I
droop
and creates a voltage drop as
droop
shown in Equation 3.
Phase Current Balancing
The ISL6377 monitors individual phase average current by
monitoring the ISEN1, ISEN2, ISEN3, and ISEN4 voltages.
Figure 14 shows the recommended current balancing circuit for
DCR sensing. Each phase node voltage is averaged by a low-pass
filter consisting of R
isen
and C
corresponding ISEN pin. R
phase-node pad in order to eliminate the effect of phase node
parasitic PCB DCR. Equations 6 through 9 give the ISEN pin
voltages:
, and is presented to the
isen
should be routed to the inductor
isen
is the droop voltage required to implement load line.
V
droop
Changing R
Since I
recommended to first scale I
then select an appropriate R
load line slope.
Differential Sensing
Figure 13 also shows the differential voltage sensing scheme.
VCC
from the processor die. A unity gain differential amplifier senses
the VSS
droop
sets the overcurrent protection level, it is
sum
and VSS
SENSE
SENSE
or scaling I
SENSE
voltage and adds it to the DAC output. The error
droop
sum
droop
are the remote voltage sensing signals
16
can change the load line slope.
based on OCP requirement,
value to obtain the desired
where R
R
pcb2
, R
dcr1
pcb3
, R
and R
dcr2
, R
and R
dcr3
are parasitic PCB DCR between the
pcb4
are inductor DCR; R
dcr4
inductor output side pad and the output voltage rail; and I
and IL4 are inductor average currents.
I
L3
August 6, 2012
,
pcb1
, IL2,
L1
FN8336.0
Page 17
ISL6377
FIGURE 15. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT
INTERNAL
TO IC
V
o
ISEN3
L3
R
isen
C
isen
ISE N 2
R
isen
C
isen
ISEN1
R
isen
C
isen
L2
L1
R
dcr3
R
dcr2
R
dcr1
PHASE3
PHASE2
PHASE1
I
L3
I
L2
I
L1
R
pcb3
R
pcb2
R
pcb1
R
isen
R
isen
R
isen
R
isen
R
isen
R
isen
V3p
V
3n
V2p
V
2n
V1p
V
1n
L4
R
dcr4
I
L4
R
pcb4
V
4n
V4p
PHASE4
R
isen
C
isen
R
isen
R
isen
R
isen
R
isen
R
isen
R
isen
ISE N 4
V
ISEN1V1pV2nV3nV4n
+++=
(EQ. 10)
V
ISEN2V1nV2pV3nV4n
+++=
(EQ. 11)
V
ISEN3V1nV2nV3pV4n
+++=
(EQ. 12)
V
ISEN4V1nV2nV3nV4p
+++=
(EQ. 13)
V1pV2nV3nV+
4n
++ V1nV2pV3nV
4n
+++=
(EQ. 14)
V1nV2pV3nV+
4n
++ V1nV2nV3pV
4n
+++=
(EQ. 15)
V1nV2nV3pV+
4n
++ V1nV2nV3nV
4p
+++=
(EQ. 16)
V1pV1n– V2pV2n–=
(EQ. 17)
V2pV2n– V3pV3n–=
(EQ. 18)
V3pV3n– V4pV4n–=
(EQ. 19)
V1pV1n– V2pV2n– V3pV3n– V4pV4n–===
(EQ. 20)
R
dcr1IL1
× R
dcr2IL2
× R
dcr3IL3
× R
dcr4IL4
×===
(EQ. 21)
The ISL6377 will adjust the phase pulse-width relative to the
other phases to make V
ISEN1=VISEN2=VISEN3
achieve IL1=IL2=IL3 =IL4, when R
and R
pcb1=Rpcb2=Rpcb3=Rpcb4
dcr1=Rdcr2=Rdcr3
.
=V
ISEN4
, thus to
=R
dcr4
Using the same components for L1, L2, L3 and L4 provides a
good match of R
determines R
pcb1
dcr1
, R
pcb2
dcr2
, R
dcr3
pcb3
and R
and R
. Board layout
dcr4
. It is recommended
pcb4
, R
, R
to have a symmetrical layout for the power delivery path between
each inductor and the output voltage rail, such that
R
pcb1=Rpcb2=Rpcb3=Rpcb4
.
The ISL6377 will make V
ISEN1
shown in Equations 14 and 16:
Rewriting Equation 14 gives Equation 17:
Rewriting Equation 15 gives Equation 18:
Rewriting Equation 16 gives Equation 19:
Combining Equations 17 through 19 gives:
Therefore:
= V
ISEN2
= V
ISEN3
= V
ISEN4
as
Sometimes, it is difficult to implement symmetrical layout. For
the circuit shown in Figure 14, asymmetric layout causes
, R
different R
current imbalance. Figure 15 shows a differential sensing current
balancing circuit recommended for ISL6377. The current sensing
traces should be routed to the inductor pads so they only pick up
the inductor DCR voltage. Each ISEN pin sees the average voltage
of three sources: its own, phase inductor phase-node pad, and
the other two phase inductor output side pads. Equations 10
through 13 give the ISEN pin voltages:
pcb1
, R
pcb2
pcb3
and R
17
values, thus creating a
pcb4
Current balancing (I
R
dcr1=Rdcr2=Rdcr3 =Rdcr4
L1=IL2=IL3 =IL4
. R
) is achieved when
, R
pcb1
pcb2
, R
pcb3
and R
pcb4
do
not have any effect.
Since the slave ripple capacitor voltages mimic the inductor
currents, the R
3
™ modulator can naturally achieve excellent
current balancing during steady state and dynamic operations.
Figure 16 shows the current balancing performance of a three
phase evaluation board with load transient of 12A/51A at
different rep rates. The inductor currents follow the load current
dynamic change with the output capacitors supplying the
difference. The inductor currents can track the load current well
at a low repetition rate, but cannot keep up when the repetition
rate gets into the hundred-kHz range, where it is out of the
control loop bandwidth. The controller achieves excellent current
balancing in all cases installed.
FN8336.0
August 6, 2012
Page 18
FIGURE 16. CURRENT BALANCING DURING DYNAMIC OPERATION.
CH1: I
L1
, CH2: I
LOAD
, CH3: IL2, CH4: I
L3
REP RATE = 10kHz
REP RATE = 25kHz
REP RATE = 50kHz
REP RATE = 100kHz
REP RATE = 200kHz
ISL6377
Modes of Operation
CONFIG. ISEN4 ISEN3 ISEN2 PSI0_L & PSI1_L MODE
4-phase
Core VR
Config.
3-phase
Core VR
Config.
2-phase
Core VR
Config.
1-phase
Core VR
Config.
The Core VR can be configured for 4-, 3-, 2- or 1-phase operation.
Table 1 shows Core VR configurations and operational modes,
programmed by the ISEN4, ISEN3 and ISEN2 pin status and the
PSI0_L & PSI1_L commands via the SVI 2 interface. The SVI 2
interface description of these bits is outlined in Table 9.
The ISENx pins disable the channel which they are related. For
example, to setup a 3-phase configuration the ISEN4 pin is tied to
5V. This disables Channel 4 of the controller on the Core side.
In a 3-phase configuration, the Core VR operates in 3-phase CCM,
with PSI0_L and PSI_L both high. If PSI0_L is taken low via the
SVI 2 interface, the Core VR sheds Phase 3. The Core VR then
operates 2-Phase and remains in CCM. When both PSI0_L and
PSI1_L are taken low, the Core VR sheds Phase 2 and the Core
VR enters 1-Phase Diode Emulation (DE) mode.
TABLE 1. CORE VR MODES OF OPERATION
To Powe r
Stage
Tied to 5V To Power
Tied to 5V Tied to 5V To Power
Tied to 5V Tied to 5V Tied to 5V 11 1-phase CCM
To Power
Stage
Stage
To Power
Stage
To Power
Stage
Stage
11 4-phase CCM
01 2-phase CCM
00 1-phase DE
11 3-phase CCM
01 2-phase CCM
00 1-phase DE
11 2-phase CCM
01 1-phase CCM
00 1-phase DE
01 1-phase CCM
00 1-phase DE
For 2-phase configurations, the Core VR operates in 2-phase CCM
with PSI0_L and PSI_L both high. If PSI0_L is taken low via the
SVI 2 interface, the Core VR sheds Phase 2 and the Core VR
operates in 1-phase and remains in CCM. When both PSI0_L and
PSI1_L are taken low, the Core VR operates in 1-phase DE mode.
In a 1-phase configuration, the Core VR operates in 1-phase CCM
and remains in this mode when PSI0_L is taken low. When both
PSI0_l and PSI1_L are taken low, the controller enters DE mode.
The Core VR can be disabled completely by connecting ISEN1 to +5V.
ISL6377 Northbridge VR can be configured for 2- or 1-phase
operation. Table 2 shows the Northbridge VR configurations and
operational modes, which are programmed by the ISEN2_NB pin
status and the PSI0_L and PSI1_L bits of the SVI 2 command.
TABLE 2. NORTHBRIDGE VR MODES OF OPERATION
CONFIG. ISEN2_NB PSI0_L & PSI1_L MODE
2-phase NB VR Config. To Power Stage 11 2-phase CCM
01 1-phase CCM
00 1-phase DE
1-phase NB VR Config. Tied to 5V 11 1-phase CCM
01 1-phase CCM
00 1-phase DE
18
FN8336.0
August 6, 2012
Page 19
ISL6377
In a 1-phase configuration, the ISEN2_NB pin is tied to +5V. The
Northbridge VR operates in 1-phase CCM when both PSI0_L and
PSI1_L are high and continues in this mode when PSI0_L is
taken low. The controller enters 1-phase DE mode when both
PSI0_L and PSI1_L are low.
The Northbridge VR can be disabled completely by tieing
ISEN1_NB to 5V.
Dynamic Operation
Core and Northbridge VRs behave the same during dynamic
operation. The controller responds to VID-on-the-fly changes by
slewing to the new voltage at the slew rate programmed, see
Table 4. During negative VID transitions, the output voltage
decays to the lower VID value at the slew rate determined by the
load.
3
™ modulator intrinsically has voltage feed-forward. The
The R
output voltage is insensitive to a fast slew rate input voltage
change.
Adaptive Body Diode Conduction Time
Reduction
In DCM, the controller turns off the low-side MOSFET when the
inductor current approaches zero. During on-time of the low-side
MOSFET, phase voltage is negative, and the amount is the
MOSFET r
voltage drop, which is proportional to the
DS(ON)
inductor current. A phase comparator inside the controller
monitors the phase voltage during on-time of the low-side
MOSFET and compares it with a threshold to determine the zero
crossing point of the inductor current. If the inductor current has
not reached zero when the low-side MOSFET turns off, it will flow
through the low-side MOSFET body diode, causing the phase
node to have a larger voltage drop until it decays to zero. If the
inductor current has crossed zero and reversed the direction
when the low-side MOSFET turns off, it will flow through the
high-side MOSFET body diode, causing the phase node to have a
spike until it decays to zero. The controller continues monitoring
the phase voltage after turning off the low-side MOSFET. To
minimize the body diode-related loss, the controller also adjusts
the phase comparator threshold voltage accordingly in iterative
steps such that the low-side MOSFET body diode conducts for
approximately 40ns.
Resistor Configuration Options
The ISL6377 uses the COMP, COMP_NB and FCCM_NB pins to
configure some functionality within the IC. Resistors from these
pins to GND are read during the first portion of the soft-start
sequence. The following sections outline how to select the
resistor values for each of these pins to correctly program the
output voltage offset of each output, the configuration of the
floating DriverX and PWM_Y output, VID-on-the-Fly slew rate, and
switching frequency used for both VRs.
VR Offset Programming
A positive or negative offset is programmed for the Core VR using
a resistor to ground from the COMP pin and the Northbridge in a
similar manner from the COMP_NB pin. Table 3 provides the
resistor value to select the desired output voltage offset. The 1%
tolerance resistor value shown in the table must be used to
program the corresponding Core or NB output voltage offset. The
MIN and MAX tolerance values provide margin to insure the 1%
tolerance resistor will be read correctly.
TABLE 3. COMP & COMP_NB OUTPUT VOLTAGE OFFSET SELECTION
RESISTOR VALUE [kΩ]
MIN
TOLERANCE
5.54 5.62 5.70 -43.75 18.75
7.7 6 7.8 7 7.9 8 -3 7.5 31 . 25
11.33 11.5 11.67 -31.25 43.76
16.65 16.9 17.15 -25 50
19.3 19.6 19.89 -18.75 37.5
24.53 24.9 25.27 -12.5 25
33.49 34.0 34.51 -6.25 12.5
40.58 41.2 41. 81 6.25 0
51.52 52.3 53.08 18.75 18.75
72.10 73.2 74.29 31.25 31.25
93.87 95.3 96.72 43.76 43.76
119.19 121 112.81 50 50
151.69 154 156.31 37.5 37.5
179.27 182 184.73 25 25
206.85 210 213.15 12.5 12.5
1% TOLERANCE
VALUE
OPEN 0 0
MAX
TOLERANCE
COMP
V
CORE OFFSET
[mV]
COMP_NB
OFFSET
[mV]
Floating DriverX and PWM_Y Configuration
The ISL6377 allows for one internal driver and one PWM output
to be configured to opposite VRs depending on the desired
configuration of the Northbridge VR. Internal DriverX can be used
as Channel 1 of the Northbridge VR with PWM_Y used for
Channel 3 of the Core VR. Using this partitioning, a 2+1 or 1+1
configured ISL6377 would not require an external driver.
If routing of the driver signals would be a cause of concern due to
having an internal driver on the Northbridge VR, then the
ISL6377 can be configured to use PWM_Y as Channel 1 on the
Northbridge VR. DriverX would then be used as Channel 3 of the
Core VR. This allows the placement of the external drivers for the
Northbridge VR to be closer to the output stage(s) depending on
the number of active Phases, providing placement and layout
flexibility to the Northbridge VR.
The floating internal driver and PWM output are configured
based on the programming resistor from FCCM_NB to GND. The
FCCM_NB programming resistor value also sets the slew rate and
switching frequency of the Core and Northbridge VRs. These
features are outlined in the following sections. Table 4 shows
which resistor values sets the configuration and slew rate for the
ISL6377. The resistor value shown in the table must be used and
the resistor tolerance must be 1%. The MIN and MAX tolerance
around each resistor value is the same as Table 3 and provides
margin to insure the 1% tolerance resistor will be read correctly.
19
FN8336.0
August 6, 2012
Page 20
ISL6377
TABLE 4. FCCM_NB RESISTOR SELECTION
SLEW RATE FOR CORE
RESISTOR VALUE
[kΩ]
5.62 20
7. 87 1 5
11.5 12.5
16.9 10
19.6 20
24.9 15
34.0 12.5
41.2 10
52.3 20
73.2 15
95.3 12.5
121 10
154 20
182 15
210 12.5
OPEN 10
AND NORTHBRIDGE
[mV/µs] DriverX PWM_Y
Core VR
Channel 3
NB VR
Channel 1
NB VR
Channel 1
Core VR
Channel 3
VID-on-the-Fly Slew Rate Selection
The FCCM_NB resistor is also used to select the slew rate for VID
changes commanded by the processor. Once selected, the slew
rate is locked in during soft-start and is not adjustable during
operation. The lowest slew rate which can be selected is
10mV/µs which is above the minimum of 7.5mV/µs required by
the SVI2 specification. The slew rate selected sets the slew rate
for both Core and Northbridge VRs. The controller does not allow
for independent selection of slew rate.
CCM Switching Frequency
The Core and Northbridge VR switching frequency is set by the
programming resistors on COMP_NB and FCCM_NC. When the
ISL6377 is in continuous conduction mode (CCM), the switching
frequency is not absolutely constant due to the nature of the R
modulator. As explained in “Multiphase R3™ Modulator” on
page 13, the effective switching frequency increases during load
insertion and decreases during load release to achieve fast
response. Thus, the switching frequency is relatively constant at
steady state. Variation is expected when the power stage
condition, such as input voltage, output voltage, load, etc.
changes. The variation is usually less than 10% and does not
have any significant effect on output voltage ripple magnitude.
Table 5 defines the switching frequency based on the resistor
values used to program the COMP_NB and FCCM_NB pins. Use
the previous tables related to COMP_NB and FCCM_NB to
determine the correct resistor value in these ranges to program
the desired output offset, Slew Rate and DriverX/PWM_Y
configuration.
3
™
TABLE 5. SWITCHING FREQUENCY SELECTION
FREQUENCY
[kHz]
300 57.6 to OPEN 19.1 to 41.2
350 5.62 to 41.2 19.1 to 41.2
400 57.6 to OPEN 5.62 to 16.9
450 5.62 to 41.2 5.62 to 16.9
COMP_NB
RANGE [kΩ]
FCCM_NB
RANGE [kΩ]
or
154 to OPEN
or
154 to OPEN
or
57.6 to 121
or
57.6 to 121
The controller monitors SVI commands to determine when to
enter power-saving mode, implement dynamic VID changes, and
shut down individual outputs.
AMD Serial VID Interface 2.0
The on-board Serial VID Interface 2.0 (SVI 2) circuitry allows the
AMD processor to directly control the Core and Northbridge
voltage reference levels within the ISL6377. Once the PWROK
signal goes high, the IC begins monitoring the SVC and SVD pins
for instructions. The ISL6377 uses a digital-to-analog converter
(DAC) to generate a reference voltage based on the decoded SVI
value. See Figure 11 for a simple SVI interface timing diagram.
Pre-PWROK Metal VID
Typical motherboard start-up begins with the controller decoding
the SVC and SVD inputs to determine the pre-PWROK Metal VID
setting (see Table 6). Once the ENABLE input exceeds the rising
threshold, the ISL6377 decodes and locks the decoded value into
an on-board hold register.
TABLE 6. PRE-PWROK METAL VID CODES
SVC SVD OUTPUT VOLTAGE (V)
00 1.1
01 1.0
1 0 0.9
1 1 0.8
Once the programming pins are read, the internal DAC circuitry
begins to ramp Core and Northbridge VRs to the decoded
pre-PWROK Metal VID output level. The digital soft-start circuitry
ramps the internal reference to the target gradually at a fixed
rate of approximately 5mV/µs until the output voltage reaches
~250mV and then at the programmed slew rate. The controlled
ramp of all output voltage planes reduces in-rush current during
the soft-start interval. At the end of the soft-start interval, the
PGOOD and PGOOD_NB outputs transition high, indicating both
output planes are within regulation limits.
If the ENABLE input falls below the enable falling threshold, the
ISL6377 tri-states both outputs. PGOOD and PGOOD_NB are
pulled low with the loss of ENABLE. The Core and Northbridge VR
output voltages decay, based on output capacitance and load
leakage resistance. If bias to VDD falls below the POR level, the
20
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ISL6377
ISL6377 responds in the manner previously described. Once VDD
and ENABLE rise above their respective rising thresholds, the
internal DAC circuitry re-acquires a pre-PWROK metal VID code,
and the controller soft-starts.
SVI Interface Active
Once the Core and Northbridge VRs have successfully soft-started
and PGOOD and PGOOD_NB signals transition high, PWROK can
be asserted externally to the ISL6377. Once PWROK is asserted
to the IC, SVI instructions can begin as the controller actively
monitors the SVI interface. Details of the SVI Bus protocol are
provided in the “AMD Serial VID Interface 2.0 (SVI2)
Specification”. See AMD publication #48022.
Once a VID change command is received, the ISL6377 decodes
the information to determine which VR is affected and the VID
target is determined by the byte combinations in Table 7. The
internal DAC circuitry steps the output voltage of the VR
commanded to the new VID level. During this time, one or more
of the VR outputs could be targeted. In the event either VR is
commanded to power-off by serial VID commands, the PGOOD
signal remains asserted.
If the PWROK input is de-asserted, then the controller steps both
the Core and the Northbridge VRs back to the stored pre-PWROK
metal VID level in the holding register from initial soft-start. No
attempt is made to read the SVC and SVD inputs during this time.
If PWROK is re-asserted, then the ISL6377 SVI interface waits for
instructions.
If ENABLE goes low during normal operation, all external
MOSFETs are tri-stated and both PGOOD and PGOOD_NB are
pulled low. This event clears the pre-PWROK metal VID code and
forces the controller to check SVC and SVD upon restart, storing
the pre-PWROK metal VID code found on restart.
A POR event on VCC during normal operation shuts down both
regulators, and both PGOOD outputs are pulled low. The
pre-PWROK metal VID code is not retained. Loss of VIN during
operation will typically cause the controller to enter a fault
condition on one or both outputs as the output voltage collapses.
The controller will shutdown both Core and Northbridge VRs and
latch off. The pre-PWROK metal VID code is not retained during
the process of cycling ENABLE to reset the fault latch and restart
the controller.
VID-on-the-Fly Transition
Once PWROK is high, the ISL6377 detects this flag and begins
monitoring the SVC and SVD pins for SVI instructions. The
microprocessor follows the protocol outlined in the following
sections to send instructions for VID-on-the-fly transitions. The
ISL6377 decodes the instruction and acknowledges the new VID
code. For VID codes higher than the current VID level, the
ISL6377 begins stepping the commanded VR outputs to the new
VID target at the fixed slew rate of 10mV/µs. Once the DAC
ramps to the new VID code, a VID-on-the-Fly Complete (VOTFC)
request is sent on the SVI lines.
When the VID codes are lower than the current VID level, the
ISL6377 checks the state of power state bits in the SVI
command. If power state bits are not active, the controller begins
stepping the regulator output to the new VID target. If the power
state bits are active, the controller allows the output voltage to
decay and slowly steps the DAC down with the natural decay of
the output. This allows the controller to quickly recover and move
to a high VID code if commanded. The controller issues a VOTFC
request on the SVI lines once the SVI command is decoded and
prior to reaching the final output voltage.
VOTFC requests do not take priority over telemetry per the AMD
SVI 2 specification.
SVI Data Communication Protocol
The SVI WIRE protocol is based on the I2C bus concept. Two wires
[serial clock (SVC) and serial data (SVD)], carry information
between the AMD processor (master) and VR controller (slave) on
the bus. The master initiates and terminates SVI transactions
and drives the clock, SVC, during a transaction. The AMD
processor is always the master, and the voltage regulators are
the slaves. The slave receives the SVI transactions and acts
accordingly. Mobile SVI WIRE protocol timing is based on
high-speed mode I
additional details.
2
C. See AMD publication #48022 for
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ISL6377
.
SVID[7:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V)
0000_0000 1.55000 0010_0000 1.35000 0100_0000 1.15000 0110_0000 0.95000
0000_0001 1.54375 0010_0001 1.34375 0100_0001 1.14375 0110_0001 0.94375
0000_0010 1.53750 0010_0010 1.33750 0100_0010 1.13750 0110_0010 0.93750
0000_0011 1.53125 0010_0011 1.33125 0100_0011 1.13125 0110_0011 0.93125
0000_0100 1.52500 0010_0100 1.32500 0100_0100 1.12500 0110_0100 0.92500
0000_0101 1.51875 0010_0101 1.31875 0100_0101 1.11875 0110_0101 0.91875
0000_0110 1.51250 0010_0110 1.31250 0100_0110 1.11250 0110_0110 0.91250
0000_0111 1.50625 0010_0111 1.30625 0100_0111 1.10625 0110_0111 0.90625
0000_1000 1.50000 0010_1000 1.30000 0100_1000 1.10000 0110_1000 0.90000
0000_1001 1.49375 0010_1001 1.29375 0100_1001 1.09375 0110_1001 0.89375
0000_1010 1.48750 0010_1010 1.28750 0100_1010 1.08750 0110_1010 0.88750
0000_1011 1.48125 0010_1011 1.28125 0100_1011 1.08125 0110_1011 0.88125
0000_1100 1.47500 0010_1100 1.27500 0100_1100 1.07500 0110_1100 0.87500
0000_1101 1.46875 0010_1101 1.26875 0100_1101 1.06875 0110_1101 0.86875
0000_1110 1.46250 0010_1110 1.26250 0100_1110 1.06250 0110_1110 0.86250
0000_1111 1.45625 0010_1111 1.25625 0100_1111 1.05625 0110_1111 0.85625
0001_0000 1.45000 0011_0000 1.25000 0101_0000 1.05000 0111_0000 0.85000
0001_0001 1.44375 0011_0001 1.24375 0101_0001 1.04375 0111_0001 0.84375
0001_0010 1.43750 0011_0010 1.23750 0101_0010 1.03750 0111_0010 0.83750
0001_0011 1.43125 0011_0011 1.23125 0101_0011 1.03125 0111_0011 0.83125
0001_0100 1.42500 0011_0100 1.22500 0101_0100 1.02500 0111_0100 0.82500
0001_0101 1.41875 0011_0101 1.21875 0101_0101 1 .01875 0111_0101 0.81875
0001_0110 1.41250 0011_0110 1.21250 0101_0110 1.01250 0111_0110 0.81250
0001_0111 1.40625 0011_0111 1.20625 0101_0111 1.00625 0111_0111 0.80625
0001_1000 1.40000 0011_1000 1.20000 0101_1000 1.00000 0111_1000 0.80000
0001_1001 1.39375 0011_1001 1.19375 0101_1001 0.99375 0111_1001 0.79375
0001_1010 1.38750 0011_1010 1.18750 0101_1010 0.98750 0111_1010 0.78750
0001_1011 1.38125 0011_1011 1.18125 0101_1011 0.98125 0111_1011 0.78125
0001_1100 1.37500 0011_1100 1.17500 0101_1100 0.97500 0111_1100 0.77500
0001_1101 1.36875 0011_1101 1.16875 0101_1101 0.96875 0111_1101 0.76875
0001_1110 1.36250 0011_1110 1.16250 0101_1110 0.96250 0111_1110 0.76250
0001_1111 1.35625 0011_1111 1.15625 0101_1111 0.95625 0111_1111 0.75625
1000_0000 0.75000 1010_0000 0.55000* 1100_0000 0.35000* 1110_0000 0.15000*
1000_0001 0.74375 1010_0001 0.54375* 1100_0001 0.34375* 1110_0001 0.14375*
1000_0010 0.73750 1010_0010 0.53750* 1100_0010 0.33750* 1110_0010 0.13750*
1000_0011 0.73125 1010_0011 0.53125* 1100_0011 0.33125* 1110_0011 0.13125*
1000_0100 0.72500 1010_0100 0.52500* 1100_0100 0.32500* 1110_0100 0.12500*
1000_0101 0.71875 1010_0101 0.51875* 1100_0101 0.31875* 1110_0101 0.11875*
1000_0110 0.71250 1010_0110 0.51250* 1100_0110 0.31250* 1110_0110 0.11250*
1000_0111 0.70625 1010_0111 0.50625* 1100_0111 0.30625* 1110_0111 0.10625*
TABLE 7. SERIAL VID CODES
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ISL6377
TABLE 7. SERIAL VID CODES (Continued)
SVID[7:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V)
1000_1000 0.70000 1010_1000 0.50000* 1100_1000 0.30000* 1110_1000 0.10000*
1000_1001 0.69375 1010_1001 0.49375* 1100_1001 0.29375* 1110_1001 0.09375*
1000_1010 0.68750 1010_1010 0.48750* 1100_1010 0.28750* 1110_1010 0.08750*
1000_1011 0.68125 1010_1011 0.48125* 1100_1011 0.28125* 1110_1011 0.08125*
1000_1100 0.67500 1010_1100 0.47500* 1100_1100 0.27500* 1110_1100 0.07500*
1000_1101 0.66875 1010_1101 0.46875* 1100_1101 0.26875* 1110_1101 0.06875*
1000_1110 0.66250 1010_1110 0.46250* 1100_1110 0.26250* 1110_1110 0.06250*
1000_1111 0.65625 1010_1111 0.45625* 1100_1111 0.25625* 1110_1111 0.05625*
1001_0000 0.65000 1011_0000 0.45000* 1101_0000 0.25000* 1111_0000 0.05000*
1001_0001 0.64375 1011_0001 0.44375* 1101_0001 0.24375* 1111_0001 0.04375*
1001_0010 0.63750 1011_0010 0.43750* 1101_0010 0.23750* 1111_0010 0.03750*
1001_0011 0.63125 1011_0011 0.43125* 1101_0011 0.23125* 1111_0011 0.03125*
1001_0100 0.62500 1011_0100 0.42500* 1101_0100 0.22500* 1111_0100 0.02500*
1001_0101 0.61875 1011_0101 0.41875* 1101_0101 0.21875* 1111_0101 0.01875*
1001_0110 0.61250 1011_0110 0.41250* 1101_0110 0.21250* 1111_0110 0.01250*
1001_0111 0.60625 1011_0111 0.40625* 1101_0111* 0.20625* 1111_0111 0.00625*
1001_1000 0.60000* 1011_1000 0.40000* 1101_1000 0.20000* 1111_1000 OFF*
1001_1001 0.59375* 1011_1001 0.39375* 1101_1001 0.19375* 1111_1001 OFF*
1001_1010 0.58750* 1011_1010 0.38750* 1101_1010 0.18750* 1111_1010 OFF*
1001_1011 0.58125* 1011_1011 0.38125* 1101_1011 0.18125* 1111_1011 OFF*
1001_1100 0.57500* 1011_1100 0.37500* 1101_1100 0.17500* 1111_1100 OFF*
1001_1101 0.56875* 1011_1101 0.36875* 1101_1101 0.16875* 1111_1101 OFF*
1001_1110 0.56250* 1011_1110 0.36250* 1101_1110 0.16250* 1111_1110 OFF*
1001_1111 0.55625* 1011_1111 0.35625* 1101_1111 0.15625* 1111_1111 OFF*
NOTE:
*Indicates a VID not required for AMD Family 10h processors. Loosened AMD requirements at these levels.
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ISL6377
FIGURE 17. SVD PACKET STRUCTURE
1 2 3 4 5 6 7 12 141516171310
SVD
SVC
S
T
A
R
T
P
S
I
1
_
L
VID Bits [7:1]
1189 1819 20 21 22 23 24 25 26 27
VID
Bit [0]
P
S
I
0
_
L
ACK ACKACK
SVI Bus Protocol
The AMD processor bus protocol is similar to SMBus send byte
protocol for VID transactions. The AMD SVD packet structure is
shown in Figure 17. The description of each bit of the three bytes
that make up the SVI command are shown in Table 8. During a
transaction, the processor sends the start sequence followed by
each of the three bytes which end with an optional acknowledge
bit. The ISL6377 does not drive the SVD line during the ACK bit.
Finally, the processor sends the stop sequence. After the
ISL6377 has detected the stop, it can then proceed with the
commanded action from the transaction.
TABLE 8 . SV D DATA PACKET
BITS DESCRIPTION
1:5 Always 11000b
6 Core domain selector bit, if set then the following data byte
contains VID, power state, telemetry control, load line trim and
offset trim apply to the Core VR.
7 Northbridge domain selector bit, if set then the following data
byte contains VID, power state, telemetry control, load line trim
and offset trim apply to the Northbridge VR.
8Always 0b
9Acknowledge Bit
10 PSI0_L
11:17 VID Code bits [7:1]
18 Acknowledge Bit
19 VID Code bit [0]
20 PSI1_L
21 TFN (Telemetry Functionality)
22:24 Load Line Slope Trim
25:26 Offset Trim [1:0]
27 Acknowledge Bit
Power States
SVI2 defines two power state indicator levels, see Table 9. As
processor current consumption reduces the power state indicator
level changes to improve VR efficiency under low power
conditions.
For the Core VR operating in 4-phase mode, when PSI0_L is
asserted Channels 3 and 4 are tri-stated. The controller
continues to operate in 2-phase CCM. The shedding of phases
improves the efficiency of the VR at the light to moderate load
levels of the CPU in this power state. When PSI1_L is asserted
the Core VR sheds Channel 2 and Channel 1 enters diode
emulation mode to further boost light load efficiency in this
power state.
For the Northbridge VR operating in 2-phase mode, when PSI0_L
is asserted Channel 2 is tri-stated and Channel 1 enters diode
emulation mode to boost efficiency. When PSI1_L is asserted the
Core VR continues to operate in this fashion.
It is possible for the processor to assert or deassert PSI0_L and
PSI1_L out of order. PSI0_L takes priority over PSI1_L. If PSI0_L
is deasserted while PSI1_L is still asserted, the ISL6377 will
return the selected VR back full channel CCM operation. For
example, if the Core VR is configured for 4-Phase operation and
both PSI0_L and PSI1_L are asserted low during a command, the
VR will shed three phases and operate in 1-Phase DE mode. If an
SVI command follows which takes PSI0_L high, but leaves
PSI1_L low, the VR will exit power savings mode and being
operation in 4-Phase CCM mode.
TABLE 9. PSI0_L, PSI1_L AND TFN DEFINITION
FUNCTION BIT DESCRIPTION
PSI0_L 10 Power State Indicate level 0. When this signal is
asserted (active Low) the processor is in a low
enough power state for the ISL6377 to take action
to boost efficiency by dropping phases and entering
1-Phase DE.
PSI1_L 20 Power State Indicate level 1. When this signal is
asserted (active Low) the processor is in a low
enough power state for the ISL6377 to take action
to boost efficiency by dropping phases and entering
1-Phase DE.
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ISL6377
Dynamic Load Line Slope Trim
The ISL6377 supports the SVI2 ability for the processor to
manipulate the load line slope of the Core and Northbridge VRs
independently using the serial VID interface. The slope
manipulation applies to the initial load line slope. A load line
slope trim will typically coincide with a VOTF change. See
Table 10 for more information about the load line slope trim
feature of the ISL6377. The Disable LL selection is not
recommended unless operation without a LL is required and
considered during the compensation of the VR.
TABLE 10. LOAD LINE SLOPE TRIM DEFINITION
LOAD LINE SLOPE TRIM [2:0] DESCRIPTION
000 Disable LL
001 -40% mΩ Change
010 -20% mΩ Change
011 No Change
100 +20% mΩ Change
101 +40% mΩ Change
110 +60% mΩ Change
111 +80% mΩ Change
Dynamic Offset Trim
The ISL6377 supports the SVI2 ability for the processor to
manipulate the output voltage offset of the Core and Northbridge
VRs. This offset is in addition to any output voltage offset set via
the COMP resistor reader. The dynamic offset trim can disable
the COMP resistor programmed offset of either output when
Disable All Offset’ is selected.
TABLE 11. OFFSET TRIM DEFINITION
OFFSET TRIM [1:0] DESCRIPTION
00 Disable All Offset
01 -25mV Change
10 0mV Change
11 +25mV Change
Telemetry
The ISL6377 can provide voltage and current information to the
AMD CPU through the telemetry system outlined by the AMD
SVI2 specification. The telemetry data is transmitted through the
SVC and SVT lines of the SVI2 interface.
Current telemetry is based on a voltage generated across a
133kΩ resistor placed from the IMON pin to GND. The current
flowing out of the IMON pin is proportional to the load current in
the VR. The I
Line Implementation” on page 15, provides the base conversion
from the load current to the internal amplifier created I
current. The I
create the IMON current which flows out of the IMON pin. The
current will measure 36µA when the load current is at full
I
sum
load based on a droop current designed for 45µA at the same
load current. The difference between the I
current defined in “Voltage Regulation and Load
sum
current is then divided down by a factor of 4 to
sum
current and the
sum
sum
droop current is provided in Equation 2. The IMON current will
measure 11.25µA at full load current for the VR and the IMON
voltage will be 1.2V. The load percentage which is reported by the
IC is based on the this voltage. When the load is 25% of the full
load, the voltage on the IMON pin will be 25% of 1.2V or 0.3V.
The SVI interface allows the selection of no telemetry, voltage
only, or voltage and current telemetry on either or both of the VR
outputs. The TFN bit along with the Core and Northbridge domain
selector bits are used by the processor to change the
functionality of telemetry, see Table 12 for more information.
TAB LE 12. T FN TR UT H TABLE
TFN, Core, NB
BITS [21,6,7]
1,0,1 Telemetry is in voltage and current mode. Therefore,
voltage and current are sent for VDD and VDDNB
domains by the controller.
1,0,0 Telemetry is in voltage mode only. Only the voltage of
VDD and VDDNB domains is sent by the controller.
1,1,0 Telemetry is disabled.
1,1,1 Reserved
DESCRIPTION
Protection Features
Core VR and Northbridge VR both provide overcurrent,
current-balance, undervoltage, and overvoltage fault protections.
The controller also provides over-temperature protection. The
following discussion is based on Core VR and also applies to the
Northbridge VR.
Overcurrent
The IMON voltage provides a means of determining the load
current at any moment in time. The overcurrent protection (OCP)
circuitry monitors the IMON voltage to determine when a fault
occurs. Based on the previous description in “Voltage Regulation
and Load Line Implementation” on page 15, the current which
flows out of the IMON pin is proportional to the I
current is created from the sensed voltage across Cn which is
I
sum
a measure of the load current based upon the sensing element
selected. The IMON current is generated internally and is 1/4 of
the I
current. The EDC or IDDspike current value for the AMD
sum
CPU load is used to set the maximum current level for droop and
the IMON voltage of 1.2V which indicates 100% loading for
telemetry. The I
current level at maximum load, or IDDspike, is
sum
36µA and this translates to an IMON current level of 9µA. The
IMON resistor is 133kΩ and the 9µA flowing through the IMON
resistor results in a 1.2V level at maximum loading of the VR.
The overcurrent threshold is 1.5V on the IMON pin. Based on a
1.2V IMON voltage equating to 100% loading, the additional 0.3V
provided above this level equates to a 25% increase in load current
before an OCP fault is detected. The EDC or IDDspike current is
used to set the 1.2V on IMON for full load current. So the OCP level
is 1.25 times the EDC or IDDspike current level. This additional
margin above the EDC or IDDspike current allows the AMD CPU to
enter and exit the IDDspike performance mode without issue
unless the load current is out of line with the IDDspike expectation,
thus the need for overcurrent protection.
current. The
sum
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August 6, 2012
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ISL6377
NTC
R
NTC
V
NTC
-
+
30µA
INTERNAL TO
ISL6377
FIGURE 18. CIRCUITRY ASSOCIATED WITH THE THERMAL MONITOR
FEATURE OF THE ISL6377
R
s
MONITOR
R
+V
R
p
WAR NING
640mV
SHUTDOWN
580mV
VR_HOT_L
When the voltage on the IMON pin meets the overcurrent
threshold of 1.5V, this triggers an OCP event. Within 2µs of
detecting an OCP event, the controller asserts VR_HOT_L low to
communicate to the AMD CPU to throttle back. A fault timer
begins counting while IMON is at or above the 1.5V threshold. The
fault timer lasts 7.5µs to 11µs and then the controller takes action
by tri-stating the active channels. This provides the CPU time to
recover and reduce the load current. If the OCP conditions are
relieved, then the fault timer is cleared and VR_HOT_L is taken
high clearing the fault condition. If the load current is not reduced
and the OCP condition is maintained, the output voltage will fall
below the undervoltage threshold due to the lack of switching or a
way-overcurrent fault could occur. Either of these fault conditions
will cause the controller to drop PGOOD of that output. When
PGOOD is taken low, a fault flag from this VR is sent to the other
VR and it is shutdown within 10µs and PGOOD of the other output
is taken low.
The ISL6377 also features a way-overcurrent [WOC] feature which
immediately takes the controller into shutdown. This protection is
also referred to as fast overcurrent protection for short-circuit
protection. If the IMON current reaches 15µA, WOC is triggered.
Active channels are tri-stated and the controller is placed in
shutdown and PGOOD is pulled low. There is no fault timer on the
WOC fault, the controller takes immediate action. The other
controller output is also shutdown within 10µs.
out of the NTC pin creates a voltage that is compared to a
warning threshold of 640mV. When the voltage at the NTC pin
falls to this warning threshold or below, the controller asserts
VR_HOT_L to alert the AMD CPU to throttle back load current to
stabilize the motherboard temperature. A thermal fault counter
begins counting toward a minimum shutdown time of 100µs.
The thermal fault counter is an up/down counter, so if the
voltage at the NTC pin rises above the warning threshold, it will
count down and extend the time for a thermal fault to occur. The
warning threshold does have 20mV of hysteresis.
If the voltage at the NTC pin continues to fall down to the
shutdown threshold of 580mV or below, the controller goes into
shutdown and triggers a thermal fault. The PGOOD pin is pulled
low and tri-states the power MOSFETs. A fault on either side will
shutdown both VRs.
Current-Balance
The controller monitors the ISENx pin voltages to determine
current-balance protection. If the ISENx pin voltage difference is
greater than 9mV for 1ms, the controller will declare a fault and
latch off.
Undervoltage
If the VSEN voltage falls below the output voltage VID value plus
any programmed offsets by -325mV, the controller declares an
undervoltage fault. The controller de-asserts PGOOD and
tri-states the power MOSFETs.
Overvoltage
If the VSEN voltage exceeds the output voltage VID value plus any
programmed offsets by +325mV, the controller declares an
overvoltage fault. The controller de-asserts PGOOD and turns on the
low-side power MOSFETs. The low-side power MOSFETs remain on
until the output voltage is pulled down below the VID set value. Once
the output voltage is below this level, the lower gate is tri-stated. If
the output voltage rises above the overvoltage threshold again, the
protection process is repeated. when all power MOSFETs are turned
off. This behavior provides the maximum amount of protection
against shorted high-side power MOSFETs while preventing output
ringing below ground.
Thermal Monitor [NTC, NTC_NB]
The ISL6377 features two thermal monitors which use an
external resistor network which includes an NTC thermistor to
monitor motherboard temperature and alert the AMD CPU of a
thermal issue. Figure 18 shows the basic thermal monitor circuit
on the Core VR NTC pin. The Northbridge VR features the same
thermal monitor. The controller drives a 30µA current out of the
NTC pin and monitors the voltage at the pin. The current flowing
As the board temperature rises, the NTC thermistor resistance
decreases and the voltage at the NTC pin drops. When the
voltage on the NTC pin drops below the over-temperature trip
threshold, then VR_HOT is pulled low. The VR_HOT signal is used
to change the CPU operation and decrease power consumption.
With the reduction in power consumption by the CPU, the board
temperature decreases and the NTC thermistor voltage rises.
Once the over-temperature threshold is tripped and VR_HOT is
taken low, the over-temperature threshold changes to the reset
level. The addition of hysteresis to the over-temperature
threshold prevents nuisance trips. Once both pin voltages exceed
the over-temperature reset threshold, the pull-down on VR_HOT
is released. The signal changes state and the CPU resumes
normal operation. The over-temperature threshold returns to the
trip level.
26
FN8336.0
August 6, 2012
Page 27
ISL6377
SVC, SVD
INTERNAL TO
ISL6377
FIGURE 19. PROTECTION DEVICES ON THE SVC AND SVD PINS
GND
VDD
CN
R
SUM
R
O
R
NTCS
R
NTC
R
P
DCRLDCR
L
R
SUM
R
O
PHASE2 PHASE3
I
O
L
PHASE1
R
O
R
SUM
RI
VCN
+
-
L
PHASE4
R
SUM
R
O
DCRDCR
I
SUM+
I
SUM-
FIGURE 20. DCR CURRENT-SENSING NETWORK
VCns()
R
ntcnet
R
ntcnet
R
sum
N
-------------- -
+
------------------------------------------
DCR
N
-------------
×
⎝⎠
⎜⎟
⎜⎟
⎜⎟
⎛⎞
I
o
s()× Acs× s()=
(EQ. 22)
R
ntcnet
R
ntcsRntc
+()Rp×
R
ntcsRntcRp
++
----------------------------------------------------
=
(EQ. 23)
Acss()
1
s
ω
L
------ -
+
1
s
ω
sns
------------ -
+
-----------------------
=
(EQ. 24)
Table 13 summarizes the fault protections.
TABLE 13. FAULT PROTECTION SUMMARY
FAULT DURATION
FAULT TYPE
BEFORE
PROTECTION PROTECTION ACTION
FAULT
RESET
Overcurrent 7.5µs to 11.5µs PWM tri-state
Phase Current
Unbalance
Way-Overcurrent
(1.5xOC)
Undervoltage
-325mV
Overvoltage
+325mV
1ms
Immediately
PWM tri-state, PGOOD
latched low
PGOOD latched low.
PWM tri-state.
PGOOD latched low.
Actively pulls the output
ENABLE
toggle or
VDD
toggle
voltage to below VID
value, then tri-state.
NTC Thermal 100µs min PGOOD latched low.
PWM tri-state.
Fault Recovery
All of the previously described fault conditions can be reset by
bringing ENABLE low or by bringing VDD below the POR
threshold. When ENABLE and VDD return to their high operating
levels, the controller resets the faults and soft-start occurs.
Interface Pin Protection
The SVC and SVD pins feature protection diodes which must be
considered when removing power to VDD and VDDIO, but leaving
it applied to these pins. Figure 19 shows the basic protection on
the pins. If SVC and/or SVD are powered but VDD is not, leakage
current will flow from these pins to VDD.
Key Component Selection
Inductor DCR Current-Sensing Network
Figure 20 shows the inductor DCR current-sensing network for a
4-phase solution. An inductor current flows through the DCR and
creates a voltage drop. Each inductor has two resistors in R
connected to the pads to accurately sense the inductor
and R
o
current by sensing the DCR voltage drop. The R
sum
and Ro
resistors are connected in a summing network as shown, and feed
the total current information to the NTC network (consisting of
, R
R
ntcs
and Rp) and capacitor Cn. R
ntc
is a negative
ntc
temperature coefficient (NTC) thermistor, used to temperature
compensate the inductor DCR change.
The inductor output side pads are electrically shorted in the
schematic but have some parasitic impedance in actual board
layout, which is why one cannot simply short them together for the
current-sensing summing network. It is recommended to use
1Ω~10Ω R
to create quality signals. Since Ro value is much smaller
o
than the rest of the current sensing circuit, the following analysis
ignores it.
The summed inductor current information is presented to the
capacitor C
. Equations 22 thru 26 describe the frequency
n
domain relationship between inductor total current Io(s) and Cn
voltage V
Cn
(s):
sum
27
FN8336.0
August 6, 2012
Page 28
ISL6377
ω
L
DCR
L
-------------
=
(EQ. 25)
ω
sns
1
R
ntcnet
R
sum
N
-------------- -
×
R
ntcnet
R
sum
N
-------------- -
+
------------------------------------------
C
n
×
--------------------------------------------------------
=
(EQ. 26)
C
n
L
R
ntcnet
R
sum
N
-------------- -
×
R
ntcnet
R
sum
N
-------------- -
+
------------------------------------------
DCR×
-------------------------------------------------------------- -
=
(EQ. 27)
FIGURE 21. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
o
i
V
o
FIGURE 22. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL
o
i
V
o
FIGURE 23. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE
o
i
V
o
FIGURE 24. OUTPUT VOLTAGE RING-BACK PROBLEM
o
i
V
o
L
i
RING
BACK
where N is the number of phases.
Transfer fu nctio n A
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC R
value decrease as its temperature decreases. Proper selection of
, R
R
sum
, Rp and R
ntcs
represents the inductor total DC current over the temperature
range of interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC
network and the R
always a fraction of the inductor DCR voltage. It is recommended
to have a higher ratio of Vcn to the inductor DCR voltage so the
droop circuit has a higher signal level to work with.
A typical set of parameters that provide good temperature
compensation are: R
and R
= 10kΩ (ERT-J1VR103J). The NTC network parameters
ntc
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current sensing network parameters to minimize engineering time.
(s) also needs to represent real-time Io(s) for the controller to
V
Cn
achieve good transient response. Transfer function A
pole w
and a zero wL. One needs to match wL and w
sns
Acs(s) is unity gain at all frequencies. By forcing wL equal to w
and solving for the solution, Equation 27 gives C
(s) always has unity gain at DC. The inductor
cs
parameters ensures that VCn
ntc
resistors form a voltage divider, Vcn is
sum
= 3.65kΩ, Rp=11kΩ, R
sum
ntcs
value.
n
= 2.61kΩ
(s) has a
cs
sns
ntc
so
sns
There is excessive overshoot if load insertion occurs during this
time, which may negatively affect the CPU reliability.
For example, given N = 4, R
R
ntcs
=2.61kΩ, R
= 10kΩ, DCR = 0.88mΩ and L = 0.36µH,
ntc
= 3.65kΩ, Rp = 11kΩ,
sum
Equation 27 gives Cn=0.518µF.
Assuming the compensator design is correct, Figure 21 shows the
expected load transient response waveforms if C
selected. When the load current I
output voltage V
If C
value is too large or too small, VCn(s) does not accurately
n
also has a square response.
core
has a square change, the
core
represent real-time Io(s) and worsens the transient response.
Figure 22 shows the load transient response when C
small. V
a system failure. Figure 23 shows the transient response when
is too large. V
C
n
sags excessively upon load insertion and may create
core
is sluggish in drooping to its final value.
core
28
is correctly
n
is too
n
FN8336.0
August 6, 2012
Page 29
Figure 24 shows the output voltage ring-back problem during load
FIGURE 25. OPTIONAL CIRCUITS FOR RING-BACK REDUCTION
Cn.2
Rntcs
Rntc
Rp
Ri
ISUM+
ISUM-
Rip
Cip
OPTIONAL
Vcn
Cn.1
Rn
OPTIONAL
FIGURE 26. RESISTOR CURRENT-SENSING NETWORK
CN
R
SUM
R
O
DCRLDCR
L
R
SUM
R
O
PHASE2 PHASE3
I
O
PHASE1
R
O
R
SUM
RI
VCN
RSEN RSEN
+
-
PHASE4
RSENRSEN
DCR
L
DCR
L
R
SUM
R
O
I
SUM+
I
SUM-
VCns()
R
sen
N
-------------
I
o
s()× A
Rsen
× s()=
(EQ. 28)
A
Rsen
s()
1
1
s
ω
sns
------------ -
+
-----------------------
=
(EQ. 29)
ω
Rsen
1
R
sum
N
-------------- -
C
n
×
-----------------------------
=
(EQ. 30)
transient response. The load current i
has a fast step change, but
o
the inductor current iL cannot accurately follow. Instead, iL
responds in first-order system fashion due to the nature of the
current loop. The ESR and ESL effect of the output capacitors
makes the output voltage V
dip quickly upon load current change.
o
However, the controller regulates Vo according to the droop current
, which is a real-time representation of iL; therefore, it pulls
i
droop
Vo back to the level dictated by iL, causing the ring-back problem.
This phenomenon is not observed when the output capacitor has
very low ESR and ESL, as is the case with all ceramic capacitors.
Figure 25 shows two optional circuits for reduction of the
ring-back. C
is the capacitor used to match the inductor time
n
constant. It usually takes the parallel of two (or more) capacitors
to get the desired value. Figure 25 shows that two capacitors
and C
(C
n.1
component to reduce the V
C
provides the desired Cn capacitance. At the beginning of io
n.2
) are in parallel. Resistor Rn is an optional
n.2
ring-back. At steady state, C
o
change, the effective capacitance is less because Rn increases
the impedance of the C
to dip when C
is too small, and this effect reduces the Vo
n
branch. As Figure 22 shows, Vo tends
n.1
ring-back. This effect is more pronounced when C
larger than C
. It is also more pronounced when Rn is bigger.
n.2
However, the presence of Rn increases the ripple of the Vn signal
if C
is too small. It is recommended to keep C
n.2
2200pF. R
should be determined through tuning the load transient response
value usually is a few ohms. C
n
waveforms on an actual board.
R
and Cip form an R-C branch in parallel with Ri, providing a
ip
lower impedance path than R
and C
ip
selection of Rip and Cip values, i
, and Vo will not ring back. The recommended value for Rip is
i
L
100Ω. C
transient response waveforms on an actual board. The
recommended range for C
should be noted that the R
waveform. Instead of being triangular as the real inductor
current, i
affect i
OCP accuracy. User discretion is advised.
at the beginning of io change. Rip
i
do not have any effect at steady state. Through proper
can resemble io rather than
should be determined through tuning the load
ip
may have sharp spikes, which may adversely
droop
average value detection and therefore may affect
droop
droop
is 100pF~2000pF. However, it
ip
-Cip branch may distort the i
ip
29
n.1
, C
n.2
n.2
ISL6377
+
n.1
is much
n.1
greater than
and Rn values
droop
Resistor Current-Sensing Network
Figure 26 shows the resistor current-sensing network for a
4-phase solution. Each inductor has a series current sensing
. R
resistor, R
sen
and Ro are connected to the R
sum
accurately capture the inductor current information. The R
resistors are connected to capacitor Cn. R
and R
o
form a filter for noise attenuation. Equations 28 thru 30 give the
VCn(s) expression.
Transfer fun ction A
Current-sensing resistor R
(s) always has unity gain at DC.
Rsen
value does not have significant
sen
variation over-temperature, so there is no need for the NTC
network.
The recommended values are R
= 1kΩ and Cn= 5600pF.
sum
Overcurrent Protection
Refer to Equation 2 on page 16 and Figures 20, 24 and 26;
resistor R
sets the I
i
current and IMON current. Tables 1 and 2 show the internal OCP
threshold based on the IMON pin voltage. Since the R
impacts both the droop current and the IMON current, fine
adjustments to I
For example, the OCP threshold is 1.5V on the IMON pin which
equates to an IMON current of 11.25µA using a 133kΩ IMON
resistor. The corresponding I
current which is proportional to droop
sum
will require changing the R
droop
is 45µA which results in an
sum
pads to
sen
and Cn
sum
resistor
i
resistor.
comp
August 6, 2012
sum
FN8336.0
Page 30
ISL6377
V
Cn
R
ntcnet
R
ntcnet
R
sum
N
-------------- -
+
------------------------------------------
DCR
N
-------------
×
⎝⎠
⎜⎟
⎜⎟
⎜⎟
⎛⎞
I
o
×=
(EQ. 31)
I
droop
5
4
-- -
1
R
i
-----
R
ntcnet
R
ntcnet
R
sum
N
-------------- -
+
------------------------------------------
DCR
N
-------------
×× I
o
××=
(EQ. 32)
R
i
5
4
-- -
R
ntcnet
DCR× Io×
NR
ntcnet
R
sum
N
-------------- -
+
⎝⎠
⎛⎞
× I
droop
×
--------------------------------------------------------------------------------- -
×=
(EQ. 33)
R
i
5
4
-- -
R
ntcsRntc
+()Rp×
R
ntcsRntcRp
++
----------------------------------------------------
DCR× I
omax
×
N
R
ntcsRntc
+()Rp×
R
ntcsRntcRp
++
----------------------------------------------------
R
sum
N
-------------- -
+
⎝⎠
⎜⎟
⎛⎞
× I
droopmax
×
-----------------------------------------------------------------------------------------------------------------------------
×=
(EQ. 34)
V
Cn
R
sen
N
-------------
I
o
×=
(EQ. 35)
I
droop
5
4
-- -
1
R
i
-----
R
sen
N
-------------
I
o
×××=
(EQ. 36)
R
i
5
4
-- -
R
senIo
×
NI
droop
×
---------------------------
×=
(EQ. 37)
R
i
5
4
-- -
R
senIomax
×
NI
droopmax
×
--------------------------------------
×=
(EQ. 38)
LL
V
droop
I
o
------------------ -
5
4
-- -
R
droop
R
i
-------------------
×
R
ntcnet
R
ntcnet
R
sum
N
-------------- -
+
------------------------------------------
DCR
N
-------------
××==
(EQ. 39)
LL
V
droop
I
o
------------------ -
5
4
-- -
R
senRdroop
×
NR
i
×
---------------------------------------
×==
(EQ. 40)
R
droop
I
o
I
droop
----------------
LL×=
(EQ. 41)
FIGURE 27. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
i
o
V
o
VID
Z
out
(s) = LL
LOAD
VR
I
of 56.25µA. At full load current, I
droop
36µA and the resulting I
is 45µA. The ratio of I
droop
relative to full load current is 1.25. Therefore, the OCP current
trip level is 25% higher than the full load current.
For inductor DCR sensing, Equation 31 gives the DC relationship
(s) and Io(s):
of V
cn
Substitution of Equation 31 into Equation 2 gives Equation 32:
Therefore:
omax
, the I
current is
sum
sum
at OCP
Load Line Slope
See Figure 13 for load-line implementation.
For inductor DCR sensing, substitution of Equation 32 into
Equation 3 gives the load-line slope expression:
For resistor sensing, substitution of Equation 36 into Equation 3
gives the load line slope expression:
Substitution of Equation 33 and rewriting Equation 39, or
substitution of Equation 37 and rewriting Equation 40, gives the
same result as in Equation 41:
Substitution of Equation 23 and application of the OCP condition
in Equation 33 gives Equation 34:
where I
is the full load current and I
omax
droopmax
is the
corresponding droop current. For example, given N = 4,
R
=3.65kΩ, R
sum
DCR = 0.88mΩ, I
= 11kΩ, R
p
= 100A and I
omax
= 2.61kΩ, R
ntcs
droopmax
= 10kΩ,
ntc
= 45μA.
Equation 34 gives Ri=529Ω.
For resistor sensing, Equation 35 gives the DC relationship of
(s) and Io(s).
V
cn
Substitution of Equation 35 into Equation 2 gives Equation 36:
Therefore:
One can use the full-load condition to calculate R
example, given I
LL = 2.1mΩ, Equation 41 gives R
It is recommended to start with the R
omax
= 100A, I
droopmax
= 4.67kΩ.
droop
droop
= 45µA and
value calculated by
droop
. For
Equation 41 and fine-tune it on the actual board to get accurate
load-line slope. One should record the output voltage readings at
no load and at full load for load-line slope calculation. Reading
the output voltage at lighter load instead of full load will increase
the measurement error.
Compensator
Figure 21 shows the desired load transient response waveforms.
Figure 27 shows the equivalent circuit of a voltage regulator (VR)
with the droop function. A VR is equivalent to a voltage source
(= VID) and output impedance Z
out
(s). If Z
load-line slope LL, i.e., a constant output impedance, then in the
entire frequency range, V
will have a square response when Io
o
has a square change.
(s) is equal to the
out
Substitution of Equation 37 and application of the OCP condition
in Equation 33 gives Equation 38:
where I
is the full load current and I
omax
corresponding droop current. For example, given N = 4,
=1mΩ, I
R
sen
gives R
= 694Ω.
i
= 100A and I
omax
droopmax
30
droopmax
is the
= 45µA, Equation 38
Intersil provides a Microsoft Excel-based spreadsheet to help
design the compensator and the current sensing network so that
VR achieves constant output impedance as a stable system.
A VR with active droop function is a dual-loop system consisting of
a voltage loop and a droop loop, which is a current loop. However,
neither loop alone is sufficient to describe the entire system. The
spreadsheet shows two loop gain transfer functions, T1(s) and
FN8336.0
August 6, 2012
Page 31
ISL6377
FIGURE 28. LOOP GAIN T1(s) MEASUREMENT SET-UP
Q2
Q1
L
i
O
C
OUT
V
O
V
IN
GATE
DRIVER
COMP
MOD.
LOAD LINE SLOPE
EA
VID
CHANNEL BCHANNEL A
EXCITATION OUTPUT
ISOLATION
TRANSFORMER
20
LOOP GAIN =
CHANNEL B
CHANNEL A
NETWORK
ANALYZER
+
+
+
-
Ω
FIGURE 29. LOOP GAIN T2(s) MEASUREMENT SET-UP
Q2
Q1
L
I
O
C
O
V
O
V
IN
GATE
DRIVER
COMP
MOD.
LOAD LINE SL OPE
EA
VID
CHANNEL B
CHANNEL A
EXCITATI ON OUTPUT
ISOLATION
TRANSFORMER
20
LOOP GAIN =
CHANNEL B
CHANNEL A
NETWORK
ANALYZER
+
+
+
-
Ω
NTC
R
NTC
30µA
INTERNAL TO
ISL6377
FIGURE 30. THERMAL MONITOR FEATURE OF THE ISL6377
R
s
MONITOR
R
+V
WARNING
640mV
SHUTDOWN
580mV
VR_HOT_L
330kΩ
8.45kΩ
0.64V
30μA
--------------- -
21.3kΩ=
(EQ. 42)
T2(s), that describe the entire system. Figure 28 conceptually
shows T1(s) measurement set-up, and Figure 29 conceptually
shows T2(s) measurement set-up. The VR senses the inductor
current, multiplies it by a gain of the load-line slope, adds it on top
of the sensed output voltage, and then feeds it to the
compensator. T1 is measured after the summing node, and T2 is
measured in the voltage loop before the summing node. The
spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)
can actually be measured on an ISL6377 regulator.
Current Balancing
Refer to Figures 14 through 20 for information on current
balancing. The ISL6377 achieves current balancing through
matching the ISEN pin voltages. R
isen
and C
form filters to
isen
remove the switching ripple of the phase node voltages. It is
recommended to use a rather long R
isenCisen
time constant such
that the ISEN voltages have minimal ripple and represent the DC
current flowing through the inductors. Recommended values are
= 10kΩ and Cs= 0.22µF.
R
s
Thermal Monitor Component Selection
The ISL6377 features two pins, NTC and NTC_NB, which are used
to monitor motherboard temperature and alert the AMD CPU if a
thermal issues arises. The basic function of this circuitry is
outlined in the “Thermal Monitor [NTC, NTC_NB]” section on
page 26. Figure 30 shows the basic configuration of the NTC
resistor, R
warning and shutdown voltages at the NTC pin.
, and offset resistor, RS, used to generate the
NTC
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s), therefore
has a higher impact on system stability.
T2(s) is the voltage loop gain with closed droop loop, thus having
a higher impact on output voltage response.
Design the compensator to get stable T1(s) and T2(s) with sufficient
phase margin and an output impedance equal to or smaller than
the load-line slope.
31
As the board temperature rises, the NTC thermistor resistance
decreases and the voltage at the NTC pin drops. When the
voltage on the NTC pin drops below the thermal warning
threshold of 0.640V, then VR_HOT_L is pulled low. When the
AMD CPU detects VR_HOT_L has gone low, it will begin throttling
back load current on both outputs to reduce the board
temperature.
If the board temperature continues to rise, the NTC thermistor
resistance will drop further and the voltage at the NTC pin could
drop below the thermal shutdown threshold of 0.580V. Once this
threshold is reached, the ISL6377 shuts down both Core and
Northbridge VRs indicating a thermal fault has occurred prior to
the thermal fault counter triggering a fault.
Selection of the NTC thermistor can vary depending on how the
resistor network is configured. The equivalent resistance at the
typical thermal warning threshold voltage of 0.64V is defined in
Equation 42.
FN8336.0
August 6, 2012
Page 32
ISL6377
0.58V
30μA
--------------- -
19.3kΩ=
(EQ. 43)
21.3kΩ 19.3kΩ–()
0.03939 0.03308–()
------------------------------------------------------
317kΩ=
(EQ. 44)
330kΩ 0.03939⋅()330kΩ 0.03308⋅()– 2.082kΩ=
(EQ. 45)
19.3kΩ 10.916kΩ– 8.384kΩ=
(EQ. 46)
FIGURE 31. TYPICAL POWER COMPONENT PLACEMENT
INDUCTOR
VIAS TO
GROUND
PLANE
VIN
VOUT
PHASE
NODE
GND
OUTPUT
CAPACITORS
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
SCHOTTKY
DIODE
HIGH-SIDE
MOSFETS
The equivalent resistance at the typical thermal shutdown
threshold voltage of 0.58V required to shutdown both outputs is
defined in Equation 43.
The NTC thermistor value correlates to the resistance change
between the warning and shutdown thresholds and the required
temperature change. If the warning level is designed to occur at a
board temperature of +100°C and the thermal shutdown level at
a board temperature of +105°C, then the resistance change of
the thermistor can be calculated. For example, a Panasonic NTC
thermistor with B = 4700 has a resistance ratio of 0.03939 of its
nominal value at +100°C and 0.03308 of its nominal value at
+105°C. Taking the required resistance change between the
thermal warning threshold and the shutdown threshold and
dividing it by the change in resistance ratio of the NTC thermistor
at the two temperatures of interest, the required resistance of
the NTC is defined in Equation 44.
The closest standard thermistor to the value calculated with
B = 4700 is 330kΩ. The NTC thermistor part number is
ERTJ0EV334J. The actual resistance change of this standard
thermistor value between the warning threshold and the
shutdown threshold is calculated in Equation 45.
COMPONENT PLACEMENT
There are two sets of critical components in a DC/DC converter;
the power components and the small signal components. The
power components are the most critical because they switch
large amounts of energy. The small signal components connect
to sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first and these include
MOSFETs, input and output capacitors, and the inductor. It is
important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each
power train. Symmetrical layout allows heat to be dissipated
equally across all power trains. Keeping the distance between
the power train and the control IC short helps keep the gate drive
traces short. These drive signals include the LGATE, UGATE,
PGND, PHASE and BOOT.
Since the NTC thermistor resistance at +105°C is less than the
required resistance from Equation 43, additional resistance in
series with the thermistor is required to make up the difference.
A standard resistor, 1% tolerance, added in series with the
thermistor will increase the voltage seen at the NTC pin. The
additional resistance required is calculated in Equation 46.
The closest, standard 1% tolerance resistor is 8.45kΩ.
The NTC thermistor is placed in a hot spot on the board, typically
near the upper MOSFET of Channel 1 of the respective output.
The standard resistor is placed next to the controller.
Layout Guidelines
PCB Layout Considerations
POWER AND SIGNAL LAYERS PLACEMENT ON THE PCB
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board. The ground-plane
layer should be adjacent to the signal layer to provide shielding.
32
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible (see Figure 31). Input high-frequency
capacitors should be placed close to the drain of the upper
MOSFETs and the source of the lower MOSFETs. Place the output
inductor and output capacitors between the MOSFETs and the
load. High-frequency output decoupling capacitors (ceramic)
should be placed as close as possible to the decoupling target
(microprocessor), making use of the shortest connection paths to
any internal planes. Place the components in such a way that the
area under the IC has less noise traces with high dV/dt and di/dt,
such as gate signals and phase node signals.
Table 14 shows layout considerations for the ISL6377 controller
by pin.
FN8336.0
August 6, 2012
Page 33
ISL6377
V
ISEN3
L3
Risen
ISEN2
ISEN1
L2
L1
Risen
Risen
Phase1
Phase2
Phase3
Ro
Ro
Ro
GND
Cisen
Cisen
Cisen
Cvsum n
Vsumn
ISEN4
L3
Risen
Phase1
Ro
Cisen
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6377 CONTROLLER
ISL6377 PIN SYMBOL LAYOUT GUIDELINES
BOTTOM PAD GND Connect this ground pad to the ground plane through a low impedance path. A minimum of 5 vias are recommended to
connect this pad to the internal ground plane layers of the PCB
1 ISEN2_NB Each ISEN pin has a capacitor (C
Place C
1. ISEN1_NB pin to ISEN2_NB pin
capacitors as close as possible to the controller and keep the following loops small:
isen
2. Any ISENx_NB pin to GND
2 NTC_NB The NTC thermistor must be placed close to the thermal source that is monitored to determine Northbridge thermal
throttling. Placement at the hottest spot of the Northbridge VR is recommended. Additional standard resistors in the
resistor network on this pin should be placed near the IC.
3 IMON_NB Place the IMON_NB resistor close to this pin and make keep a tight GND connection.
4 SVC Use good signal integrity practices and follow AMD recommendations.
5 VR_HOT_L Follow AMD recommendations. Placement of the pull-up resistor near the IC is recommended.
6 SVD Use good signal integrity practices and follow AMD recommendations.
7 VDDIO Use good signal integrity practices and follow AMD recommendations.
8 SVT Use good signal integrity practices and follow AMD recommendations.
9 ENABLE No special considerations.
10 PWROK Use good signal integrity practices and follow AMD recommendations.
11 NTC The NTC thermistor must be placed close to the thermal source that is monitored to determine Core thermal throttling.
Placement at the hottest spot of the Core VR is recommended. Additional standard resistors in the resistor network on
this pin should be placed near the IC.
12 ISEN4
13 ISEN3 Each ISEN pin has a capacitor (C
C
capacitors as close as possible to the controller and keep the following loops small:
14 ISEN2
15 ISEN1
isen
1. Any ISEN pin to another ISEN pin
2. Any ISEN pin to GND
The red traces in the following drawing show the loops to be minimized.
) decoupling it to VSUMN_NB, then through another capacitor (C
isen
) decoupling it to VSUMN and then through another capacitor (C
isen
vsumn_nb
) to GND. Place
vsumn
) to GND.
33
FN8336.0
August 6, 2012
Page 34
ISL6377
INDUCTOR
CURRENT-SENSING TRACES
VIAS
INDUCTOR
CURRENT-SENSING TRACES
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6377 CONTROLLER (Continued)
ISL6377 PIN SYMBOL LAYOUT GUIDELINES
16 ISUMP Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces
in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces on
a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed
on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two
preferred ways of routing current sensing traces.
these signals near sensitive analog signal traces or crossing over them. Routing PHASE1 to the Core VR Channel 1 highside MOSFET source pin instead of a general connection to PHASE1 copper is recommended for better performance.
proximity to the pin with the filter resistor nearby the IC.
proximity to the pin.
these signals near sensitive analog signal traces or crossing over them. Routing PHASE2 to the Core VR Channel 2 highside MOSFET source pin instead of a general connection to PHASE2 copper is recommended for better performance.
these signals near sensitive analog signal traces or crossing over them. Routing PHASEX to the high-side MOSFET source
pin instead of a general connection to the PHASEX copper is recommended for better performance.
17 IS UM N
18 VSEN Place the filter on these pins in close proximity to the controller for good coupling.
19 RTN
20 IMON Place the IMON resistor close to this pin and make keep a tight GND connection.
21 FB Place the compensation components in general proximity of the controller.
22 COMP
23 PGOOD No special consideration.
24 BOOT1 Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.
25 UGATE1 These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing
26 PHASE1
27 LGATE1 Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.
28 PWM_Y No special considerations.
29 VDD A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor in close
30 VDDP A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor in close
31 LGATE2 Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.
32 PHASE2 These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing
33 UGATE2
34 BOOT2 Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.
35 PWM4 No special considerations.
36 BOOTX Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.
37 UGATEX These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing
38 PHASEX
39 LGATEX Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.
40 PWM2_NB No special considerations.
41 FCCM_NB No special considerations.
42 PGOOD_NB No special consideration.
34
FN8336.0
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ISL6377
INDUCTOR
CURRENT-SENSING TRACES
VIAS
INDUCTOR
CURRENT-SENSING TRACES
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6377 CONTROLLER (Continued)
ISL6377 PIN SYMBOL LAYOUT GUIDELINES
43 COMP_NB Place the compensation components in general proximity of the controller.
44 FB_NB
45 VSEN_NB Place the filter on this pin in close proximity to the controller for good coupling.
46 ISUMN_NB Place the current sensing circuit in general proximity of the controller.
47 ISUMP_NB
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces
in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces on
a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed
on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two
preferred ways of routing current sensing traces.
48 ISEN1_NB Each ISEN pin has a capacitor (C
Place C
1. ISEN1_NB pin to ISEN2_NB pin
2. Any ISENx_NB pin to GND
capacitors as close as possible to the controller and keep the following loops small:
isen
) decoupling it to VSUMN_NB, then through another capacitor (C
isen
vsumn_nb
) to GND.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE REVISION CHANGE
August 6, 2012 FN8336.0 Initial Release.
Products
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for a
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35
FN8336.0
August 6, 2012
Page 36
Package Outline Drawing
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
SIDE VIEW
TOP VIEW
BOTTOM VIEW
located within the zone indicated. The pin #1 inden tifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
6.00
A
B
PIN 1
INDEX AREA
(4X)
0.15
6
6.00
4.4
37
44X
0.40
4X
PIN #1 INDEX AREA
48
6
4 .40 ± 0.15
1
AB
48X 0.45 ± 0.10
24
13
48X 0.20
4
0.10 CM
36
25
12
MAX 1.00
SEATING PLANE
BASE PLANE
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
0.10
C
0.08 C
C
SEE DETAIL "X"
( 5. 75 TYP )
( 4. 40 )
( 48X 0 . 20 )
( 48X 0 . 65 )
( 44 X 0 . 40 )
0.05 M
C
L48.6x6B
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/09
ISL6377
36
FN8336.0
August 6, 2012
Page 37
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