Datasheet isl6333 Datasheets

Page 1

ISL6333, ISL6333A, ISL6333B, ISL6333C

Data Sheet

Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

The ISL6333 three-phase PWM family of control ICs provide a precision voltage regulation system for advanced microprocessors. The integration of power MOSFET drivers into the controller IC marks a departure from the separate PWM controller and driver configuration of previous multi-phase product families. By reducing the number of external parts, this integration is optimized for a cost and space saving power management solution.

The ISL6333 controllers are designed to be compatible with Intel VR11.1 Applications. Features that make these controllers compatible include an IMON pin for output current monitoring, and a Power State Indicator (PSI#) pin for phase dropping and higher efficiency during light load states. An 8-bit VID input is used to select the desired output voltage from the VR11 DAC table. A circuit is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. The output voltage can also be positively or negatively offset through the use of a single external resistor.

The ISL6333 controllers also include advanced control loop features for optimal transient response to load application and removal. One of these features is highly accurate, fully differential, continuous DCR current sensing for load line programming and channel current balance. Active Pulse Positioning (APP) Modulation and Adaptive Phase Alignment (AP A) are two other unique features, allowing for quicker initial response to high di/dt load transients. With this quicker initial response to load transients, the number of output bulk capacitors can be reduced, helping to reduce cost.

Integrated into the ISL6333 controllers are user-programmable current sense resistors, which require only a single external resistor to set their values. No external current sense resistors are required. Another unique feature of the ISL6333 controllers is the addition of a dynamic VID compensation pin that allows optimizing compensation to be added for well-controlled dynamic VID response.

Protection features of these controller ICs include a set of sophisticated overvoltage, undervoltage, and overcurrent protection. Furthermore, the ISL6333 controllers include protection against an open circuit on the remote sensing inputs. Combined, these features provide advanced protection for the microprocessor and power system.

March 19, 2009

FN6520.1

Features

• Intel VR11.1 Compatible

- IMON Pin for Output Current Monitoring

- Power State Indicator (PSI#) Pin for Phase Dropping and Higher Efficiency During Light Load States

• CPURST_N Input to Eliminate Required Extensive External Circuit for proper PSI# Operation of Intel’s Eaglelake Chipset Platform (ISL6333B, ISL6333C Only)

• Integrated Multi-Phase Power Conversion

- 3-Phase or 2-Phase Operation with Internal Drivers

• Precision Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over-Temperature

- Adjustable Reference-Voltage Offset

• Optimal Transient Response

- Active Pulse Positioning (APP) Modulation

- Adaptive Phase Alignment (APA)

• Fully Differential, Continuous DCR Current Sensing

- Integrated Programmable Current Sense Resistors

- Accurate Load Line Programming

- Precision Channel Current Balancing

• Gate Voltage Optimization Technology (ISL6333, ISL6333B Only)

• Power Saving Diode Emulation Mode (ISL6333, ISL6333B Only)

• Optimized for use with Coupled Inductors

• Variable Gate Drive Bias: +5V to +12V

• Microprocessor Voltage Identification Inputs

- 8-bit VID Input for Selecting VR11 DAC Voltages

- Dynamic VID Technology

• Dynamic VID Compensation

• Overcurrent Protection and Channel Current Limit

• Multi-tiered Overvoltage Protection

• Digital Soft-Start

• Selectable Operation Frequency up to 1.0MHz Per Phase

• Pb-free (RoHS Compliant)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Page 2

ISL6333, ISL6333A, ISL6333B, ISL6333CISL6333, ISL6333A, ISL6333B, ISL6333C

Ordering Information

PART NUMBER

(Note)

ISL6333CRZ* ISL6333 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 ISL6333IRZ* ISL6333 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 ISL6333ACRZ* ISL6333A CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 ISL6333AIRZ* ISL6333A IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 ISL6333BCRZ* ISL6333B CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 ISL6333BIRZ* ISL6333B IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 ISL6333CCRZ* ISL6333C CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 ISL6333CIRZ* ISL6333C IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

Pinouts

ISL6333 (48 LD QFN)

TOP VIEW

RSET

OFS

VCC

REF

APA

COMP

DVC

IDROOP

VDIFF

ISEN1+

ISEN1-

ISEN2+

ISEN2-

ISEN3+

ISEN3-

PVCC1

BYP1

LGATE1

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

IMON

VSEN

RGND

PSI#

GND (PIN 49)

VID7

VID6

VID5

VID4

VID3

VID2

BOOT1

UGATE1

PHASE1

VR_RDY

PUVCC

PHASE2

UGATE2

BOOT2

LGATE2

PVCC2_3

LGATE3

BOOT3

UGATE3

PHASE3

VID1

VID0

FN6520.1

March 19, 2009

Page 3

Pinouts (Continued)

ISL6333, ISL6333A, ISL6333B, ISL6333CISL6333, ISL6333A, ISL6333B, ISL6333C

ISL6333A (48 LD QFN)

TOP VIEW

ISEN1+

ISEN1-

ISEN2+

ISEN2-

ISEN3+

ISEN3-

PVCC1

PVCC2

LGATE1

BOOT1

UGATE1

PHASE1

48 47 46 45 44 43 42 41 40 39 38 37

RSET

OFS

VCC

REF

APA

COMP

DVC

IDROOP

VDIFF

PSI#

GND (PIN 49)

VID7

VID6

VID5

VID4

VID3

13 14 15 16 17 18 19 20 21 22 23 24

IMON

VSEN

RGND

ISL6333B (48 LD QFN)

TOP VIEW

VR_RDY

PUVCC

PHASE2

UGATE2

BOOT2

LGATE2

PVCC3

LGATE3

BOOT3

UGATE3

PHASE3

VID2

VID1

VID0

RSET

OFS

VCC

REF

APA

COMP

DVC

CPURST_N

VDIFF

ISEN1+

ISEN1-

ISEN2+

ISEN2-

ISEN3+

ISEN3-

PVCC1

BYP1

LGATE1

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

IMON

VSEN

RGND

PSI#

GND (PIN 49)

VID7

VID6

VID5

VID4

VID3

BOOT1

VID2

UGATE1

PHASE1

VR_RDY

PUVCC

PHASE2

UGATE2

BOOT2

LGATE2

PVCC2_3

LGATE3

BOOT3

UGATE3

PHASE3

VID1

VID0

FN6520.1

March 19, 2009

Page 4

Pinouts (Continued)

ISL6333, ISL6333A, ISL6333B, ISL6333CISL6333, ISL6333A, ISL6333B, ISL6333C

ISL6333C (48 LD QFN)

TOP VIEW

ISEN1+

ISEN1-

ISEN2+

ISEN2-

ISEN3+

ISEN3-

PVCC1

PVCC2

LGATE1

BOOT1

UGATE1

PHASE1

48 47 46 45 44 43 42 41 40 39 38 37

RSET

OFS

VCC

REF

APA

COMP

DVC

CPURST_N

VDIFF

13 14 15 16 17 18 19 20 21 22 23 24

IMON

VSEN

RGND

PSI#

GND (PIN 49)

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VR_RDY

PUVCC

PHASE2

UGATE2

BOOT2

LGATE2

PVCC3

LGATE3

BOOT3

UGATE3

PHASE3

Controller Descriptions and Comments

DIODE

EMULATION

CONTROLLER

MODE (DEM)

ISL6333 YES YES YES Enable/Disable NO ISL6333A NO NO YES Enable/Disable NO ISL6333B YES YES NO Always Enabled YES ISL6333C NO NO NO Always Enabled YES

CONTROLLER COMMENTS

ISL6333 When PSI# is set high, the controller operates normally in continuous conduction mode (CCM) with all active channels firing.

When the PSI# pin is set low, the controller transitions to single phase operation and changes to diode emulation mode (DEM). The controller also utilizes it’s new Gate Voltage Optimization T echnology (GVOT) to reduce Channel 1’s lower MOSFET gate drive voltage. This controller yields the highest low load efficiency.

ISL6333A When PSI# is set high, the controller operates normally in continuous conduction mode (CCM) with all active channels firing.

When the PSI# pin is set low, the controller transitions to single phase operation only.

ISL6333B Same feature set as the ISL6333 controller with two additional changes. The CPURST_N pin is added to eliminate extensive

external circuitry required for proper PSI# operation of Intel’s Eaglelake Chipset Platform. The droop pin has been removed and the droop current now flows out of the FB pin. The droop feature is always active. This controller yields the highest low load efficiency.

ISL6333C Same feature set as the ISL6333A controller with two additional changes. The CPURST_N pin is added to eliminate extensive

GATE VOL T AGE OPTIMIZA TION

TECHNOLOGY

(GVOT) DROOP PIN ENABLE/DISABLE DROOP CPURST_N PIN

FN6520.1

March 19, 2009

Page 5

ISL6333, ISL6333A, ISL6333B, ISL6333CISL6333, ISL6333A, ISL6333B, ISL6333C

Integrated Driver Block Diagram

PWM

LOW POWER

STATE

SOFT-START

AND

FAULT LOGIC

GATE

CONTROL

LOGIC

SHOOT-

THROUGH

PROTECTION

LVCC

UVCC

BOOT

UGATE

20kΩ

PHASE

10kΩ

LGATE

FN6520.1

March 19, 2009

Page 6

Block Diagram - ISL6333

OPEN SENSE

LINE PREVENTION

VSEN

RGND

VDIFF

APA

UNDERVOLTAGE

DETECTION

LOGIC

OVERVOLTAGE

DETECTION

LOGIC

I_AVG I_TRIP

OCP

ISL6333, ISL6333A, ISL6333B, ISL6333CISL6333, ISL6333A, ISL6333B, ISL6333C

VR_RDY

ADAPTIVE PHASE

SOFT-START

AND

FAULT LOGIC

ALLIGNMENT

CIRCUITRY

LOW POWER

0.85V

STATE

CIRCUITRY

POWER-ON

RESET

LDO

MOSFET

DRIVER

VCC

PVCC1 PVCC2_3

PUVCC

BYP1 PSI#

BOOT1 UGATE1 PHASE1 LGATE1

VID7 VID6

VID5 VID4 VID3 VID2 VID1 VID0

DVC

REF

COMP

OFS

IDROOP

IMON

DYNAMIC

VID D/A

OFFSET

OCP

1kΩ

OCP

RGND

E/A

I_AVG

OCP

CLOCK AND

MODULAT O R

WAVEFORM

GENERATOR

APP AND APA

MODULAT OR

APP AND APA

MODULATOR

APP AND APA

MODULATOR

I_AVG

CHANNEL CURRENT BALANCE

AND

CURRENT

LIMIT

PWM1

PWM2

PWM3

∑

BOOT2

MOSFET

DRIVER

MOSFET

DRIVER

1 N

CHANNEL

DETECT

CH3

CURRENT

SENSE

CH2

CURRENT

SENSE

CH1

CURRENT

SENSE

ISEN1

ISEN3

ISEN2

UGATE2 PHASE2 LGATE2

BOOT3 UGATE3 PHASE3 LGATE3

ISEN3-

ISEN3+

ISEN2-

ISEN2+

RSET

ISEN1+

ISEN1-

GND

FN6520.1

March 19, 2009

Page 7

Block Diagram - ISL6333A

OPEN SENSE

LINE PREVENTION

VSEN

RGND

VDIFF

APA

UNDERVOLTAGE

DETECTION

LOGIC

OVERVOLTAGE

DETECTION

LOGIC

I_AVG I_TRIP

OCP

ISL6333, ISL6333A, ISL6333B, ISL6333CISL6333, ISL6333A, ISL6333B, ISL6333C

VR_RDY

ADAPTIVE PHASE

SOFT-START

AND

FAULT LOGIC

ALLIGNMENT

CIRCUITRY

LOW POWER

0.85V

STATE

CIRCUITRY

POWER-ON

RESET

MOSFET

DRIVER

VCC

PVCC1 PVCC3

PUVCC

PVCC2 PSI#

BOOT1 UGATE1 PHASE1 LGATE1

VID7 VID6

VID5 VID4 VID3 VID2 VID1 VID0

DVC

REF

COMP

OFS

IDROOP

IMON

DYNAMIC

VID D/A

OFFSET

OCP

1kΩ

OCP

RGND

E/A

I_AVG

OCP

CLOCK AND

MODULAT O R

WAVEFORM

GENERATOR

APP AND APA

MODULAT OR

APP AND APA

MODULATOR

APP AND APA

MODULATOR

I_AVG

CHANNEL CURRENT BALANCE

AND

CURRENT

LIMIT

PWM1

PWM2

PWM3

∑

BOOT2

MOSFET

DRIVER

MOSFET

DRIVER

1 N

CHANNEL

DETECT

CH3

CURRENT

SENSE

CH2

CURRENT

SENSE

CH1

CURRENT

SENSE

ISEN1

ISEN3

ISEN2

UGATE2 PHASE2 LGATE2

BOOT3 UGATE3 PHASE3 LGATE3

ISEN3-

ISEN3+

ISEN2-

ISEN2+

RSET

ISEN1+

ISEN1-

GND

FN6520.1

March 19, 2009

Page 8

Block Diagram - ISL6333B

OPEN SENSE

LINE PREVENTION

VSEN

RGND

VDIFF

APA

UNDERVOLTAGE

DETECTION

LOGIC

OVERVOLTAGE

DETECTION

LOGIC

I_AVG I_TRIP

OCP

ISL6333, ISL6333A, ISL6333B, ISL6333CISL6333, ISL6333A, ISL6333B, ISL6333C

VR_RDY

ADAPTIVE PHASE

SOFT-START

AND

FAULT LOGIC

ALLIGNMENT

CIRCUITRY

0.85V

LOW POWER

STATE

CIRCUITRY

POWER-ON

RESET

LDO

MOSFET

DRIVER

VCC

PVCC1 PVCC2_3

PUVCC

BYP1 PSI#

CPURST_N

BOOT1 UGATE1 PHASE1 LGATE1

VID7 VID6

VID5 VID4 VID3 VID2 VID1 VID0

DVC

REF

COMP

OFS

IMON

DYNAMIC

VID D/A

OFFSET

OCP

1kΩ

OCP

RGND

E/A

I_AVG

OCP

CLOCK AND

MODULATOR

WAVEFORM

GENERATOR

APP AND APA

MODULAT O R

APP AND APA

MODULAT OR

APP AND APA

MODULAT OR

I_AVG

CHANNEL CURRENT BALANCE

AND

CURRENT

LIMIT

PWM1

PWM2

PWM3

∑

BOOT2

MOSFET

DRIVER

MOSFET

DRIVER

1 N

CHANNEL

DETECT

CH3

CURRENT

SENSE

CH2

CURRENT

SENSE

CH1

CURRENT

SENSE

ISEN3

ISEN2

ISEN1

UGATE2 PHASE2 LGATE2

BOOT3 UGATE3 PHASE3 LGATE3

ISEN3-

ISEN3+

ISEN2-

ISEN2+

RSET

ISEN1+

ISEN1-

GND

FN6520.1

March 19, 2009

Page 9

Block Diagram - ISL6333C

OPEN SENSE

LINE PREVENTION

VSEN

RGND

VDIFF

APA

UNDERVOLTAGE

DETECTION

LOGIC

OVERVOLTAGE

DETECTION

LOGIC

I_AVG

I_TRIP

OCP

ISL6333, ISL6333A, ISL6333B, ISL6333CISL6333, ISL6333A, ISL6333B, ISL6333C

VR_RDY

ADAPTIVE PHASE

SOFT-START

AND

FAULT LOGIC

ALLIGNMENT

CIRCUITRY

0.85V

LOW POWER

STATE

CIRCUITRY

POWER-ON

RESET

MOSFET

DRIVER

VCC

PVCC1 PVCC3

PUVCC

PVCC2

PSI#

CPURST_N

BOOT1 UGATE1 PHASE1 LGATE1

VID7 VID6

VID5 VID4 VID3 VID2 VID1 VID0

DVC

REF

COMP

OFS

IMON

DYNAMIC

VID D/A

OFFSET

OCP

1kΩ

OCP

RGND

E/A

I_AVG

OCP

CLOCK AND

MODULAT OR

WAVEFORM

GENERAT OR

CHANNEL CURRENT BALANCE

CURRENT

APP AND AP A

MODULATOR

APP AND APA

MODULATOR

APP AND APA

MODULATOR

I_AVG

AND

LIMIT

PWM1

PWM2

PWM3

∑

BOOT2

MOSFET

DRIVER

MOSFET

DRIVER

1 N

CHANNEL

DETECT

CH3

CURRENT

SENSE

CH2

CURRENT

SENSE

CH1

CURRENT

SENSE

ISEN1

ISEN3

ISEN2

UGATE2 PHASE2 LGATE2

BOOT3 UGATE3 PHASE3 LGATE3

ISEN3-

ISEN3+

ISEN2-

ISEN2+

RSET

ISEN1+

ISEN1-

GND

FN6520.1

March 19, 2009

Page 10

ISL6333, ISL6333A, ISL6333B, ISL6333CISL6333, ISL6333A, ISL6333B, ISL6333C

Typical Application Diagram - ISL6333, ISL6333B

+5V VCC

VDIFF DVC

IDROOP

VSENRGND

RSET

BYP1

+12V

PVCC1

RGND

+5V

COMP

APA

VCC

OFS FS REF

IMON SS

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

CPURST_N

PSI#

VR_RDY

ISL6333/B

PUVCC

BOOT1

UGATE1

PHASE1

LGATE1

ISEN1-

ISEN1+

PVCC2_3

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2-

ISEN2+

BOOT3

UGATE3

PHASE3

1.8Ω

+12V

LOAD

GND

*NOTE: ISL6333 - Connect the IDROOP pin to the FB pin. The CPURST_N pin does not exist.

*NOTE: ISL6333B - The CPURST_N pin should connect to the CPURST_N signal. The IDROOP pin does not exist.

LGATE3

ISEN3-

ISEN3+

FN6520.1

March 19, 2009

Page 11

ISL6333, ISL6333A, ISL6333B, ISL6333CISL6333, ISL6333A, ISL6333B, ISL6333C

Typical Application Diagram - ISL6333, ISL6333B with NTC Thermal Compensation

+5V VCC

VDIFF DVC

IDROOP

RGND

VSEN

RSET

BYP1

+12V

PVCC1

RGND

+5V

COMP

APA

VCC

OFS FS REF

IMON SS

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

CPURST_N

PSI#

VR_RDY

ISL6333/B

PUVCC

BOOT1

UGATE1

PHASE1

LGATE1

ISEN1-

ISEN1+

PVCC2_3

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2-

ISEN2+

BOOT3

UGATE3

PHASE3

1.8Ω

+12V

NTC

PLACE IN CLOSE

PROXIMITY

LOAD

GND

*NOTE: ISL6333 - Connect the IDROOP pin to the FB pin. The CPURST_N pin does not exist.

*NOTE: ISL6333B - The CPURST_N pin should connect to the CPURST_N signal. The IDROOP pin does not exist.

LGATE3

ISEN3-

ISEN3+

FN6520.1

March 19, 2009

Page 12

ISL6333, ISL6333A, ISL6333B, ISL6333CISL6333, ISL6333A, ISL6333B, ISL6333C

Typical Application Diagram - ISL6333A, ISL6333C

+5V VCC

VDIFF DVC

VSENRGND

RSET

RGND

+5V

IDROOP

COMP

APA

VCC

OFS FS REF

IMON SS

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

CPURST_N

PSI#

VR_RDY

ISL6333A

PVCC1 PVCC2

PUVCC

BOOT1

UGATE1

PHASE1

LGATE1

ISEN1-

ISEN1+

PVCC3

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2-

ISEN2+

BOOT3

UGATE3

PHASE3

1.8Ω

+12V

LOAD

GND

*NOTE: ISL6333A - Connect the IDROOP pin to the FB pin. The CPURST_N pin does not exist.

*NOTE: ISL6333C - The CPURST_N pin should connect to the CPURST_N signal. The IDROOP pin does not exist.

LGATE3

ISEN3-

ISEN3+

FN6520.1

March 19, 2009

Page 13

ISL6333, ISL6333A, ISL6333B, ISL6333C

Absolute Maximum Ratings

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V

Absolute BOOT Voltage, V PHASE Voltage, V

UGATE Voltage, V

LGATE Voltage, V

PHASE

UGATE

- 3.5V (<100ns Pulse Width, 2µJ) to V

LGATE

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC + 0.3V

Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V

. . . . . . .GND - 0.3V to GND + 36V

BOOT

. . . . . . . . . GND - 8V (<400ns, 20µJ) to 24V

. . . . . . . .V

(<200ns, V

PHASE

BOOT - PHASE

- 0.3V to V

. . . . . . . . . . . GND - 0.3V to PVCC + 0.3V

BOOT BOOT

= 12V) + 0.3V + 0.3V

Thermal Information

Thermal Resistance θJA (°C/W) θJC (°C/W)

QFN Package (Notes 1, 2). . . . . . . . . . 28 1.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .+5V to 12V ±5%

Ambient Temperature

ISL6333CRZ, ISL6333ACRZ, ISL6333BCRZ,

ISL6333CCRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL6333IRZ, ISL6333AIRZ, ISL6333BIRZ,

ISL6333CIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

Tech Brief TB379.

2. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

3. Limits established by characterization and are not production tested.

Electrical Specifications Recommended Operating Conditions. Unless otherwise specified, parts are 100% tested at +25°C;

temperature limits are established by characterization and are not production tested.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

BIAS SUPPLIES

Input Bias Supply Current I Lower Gate Drive Bias Current -

PVCC1 Pin Lower Gate Drive Bias Current -

PVCC2_3 Pin (ISL6333, ISL6333B Only)

Lower Gate Drive Bias Current - PVCC3 Pin (ISL6333A, ISL6333C Only)

Upper Gate Drive Bias Current PUVCC Pin

VCC POR (Powe r-On Res et) Thre shold VCC rising 4.25 4.41 4.50 V

PVCC POR (Power-On Reset) Threshold

BYP1 POR (Power-On Reset) Threshold

PWM MODULATOR

Oscillator Frequency Accuracy, F

(ISL6333CRZ, ISL6333ACRZ, ISL6333BCRZ, ISL6333CCRZ)

Oscillator Frequency Accuracy, F

(ISL6333IRZ, ISL6333AIRZ, ISL6333BIRZ, ISL6333CIRZ) (Note 3)

Adjustment Range of Switching Frequency

; EN = high 13 16.7 19.5 mA

VCC

; EN = high 0.7 1.8 4 mA

PVCC1

PVCC2_3

PVCC3

UVCC

; EN = high 1.5 2.6 5 mA

; EN = high 0.6 1 1.4 mA

VCC falling 3.75 3.85 4.00 V PVCC1, PVCC2_3, PUVCC rising 4.30 4.42 4.55 V PVCC1, PVCC2_3, PUVCC falling 3.70 3.83 3.95 V BYP1 rising 4.20 4.40 4.55 V BYP1 falling 3.70 3.80 3.90 V

= 100kΩ (± 0.1%) 225 250 275 kHz

= 100kΩ (± 0.1%) 215 250 280 kHz

(Note 3) 0.08 - 1.0 MHz

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ISL6333, ISL6333A, ISL6333B, ISL6333C

Electrical Specifications Recommended Operating Conditions. Unless otherwise specified, parts are 100% tested at +25°C;

temperature limits are established by characterization and are not production tested. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Oscillator Ramp Amplitude, V

P-P

CONTROL THRESHOLDS

EN Rising Threshold 0.84 0.86 0.88 V EN Hysteresis 96 104 120 mV

REFERENCE AND DAC

System Accuracy (1.000V to 1.600V) -0.5 - 0.5 % System Accuracy (0.600V to 1.000V) -1.0 - 1.0 % System Accuracy (0.400V to 0.600V) -2.0 - 2.0 % DAC Input Low Voltage - - 0.4 V DAC Input High Voltage 0.8 - - V

PSI# INPUT

PSI# Input Low Voltage Threshold - - 0.4 V PSI# Input High Voltage Threshold 0.8 - - V

PIN-ADJUSTABLE OFFSET

OFS Sink Current Accuracy (Negative Offset)

OFS Source Current Accuracy (Positive Offset)

ERROR AMPLIFIER

DC Gain R Gain-Bandwidth Product CL = 100pF, RL = 10k to ground,

Slew Rate C Maximum Output Voltage Load = 1mA 4.00 4.196 - V Minimum Output Voltage Load = -1mA - 1.231 1.60 V

SOFT-START RAMP

Soft-Start Ramp Rate R Adjustment Range of Soft-Start Ramp

Rate (Note 3)

CURRENT SENSING

IDROOP Current Sense Offset R IDROOP Current Sense Gain R

OVERCURRENT PROTECTION

Overcurrent Trip Level - Average Channel

Overcurrent Trip Level - Individual Channel

IMON Pin Clamped Overcurrent Level 1.1 1.127 1.15 V

OVERVOLTAGE AND UNDERVOLTAGE PROTECTION

Undervoltage Threshold VSEN falling 0.48*VDAC 0.503*VDAC 0.525*VDAC V Undervoltage Hysteresis VSEN rising 0.02*VDAC 0.084*VDAC 0.15*VDAC V

(Note 3) - 1.50 - V

= 32.4kΩ from OFS to VCC -52.0 -50.3 -48.0 µA

OFS

= 6.04kΩ from OFS to GND 47.0 48.7 51.0 µA

OFS

= 10k to ground, (Note 3) - 96 - dB

-40-MHz

(Note 3)

= 100pF, Load = ±400µA, (Note 3) - 20 - V/µs

= 100kΩ 1.15 1.274 1.37 mV/µs

0.156 - 6.25 mV/µs

= 40.2kΩ, V

SET

= 40.2kΩ, V

SET

ISEN1+ ISEN1

= V

= 0V -2.5 0 2.5 µA

ISEN2+

= 24mV 77.5 81.2 85 µA

ISEN2

Normal operation 88 100 110 µA Dynamic VID change 120 140 160 µA Normal operation 120 138 160 µA Dynamic VID change 170 195 222 µA

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March 19, 2009

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ISL6333, ISL6333A, ISL6333B, ISL6333C

Electrical Specifications Recommended Operating Conditions. Unless otherwise specified, parts are 100% tested at +25°C;

temperature limits are established by characterization and are not production tested. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Overvoltage Threshold During Soft-Start

Overvoltage Threshold VR11, VSEN rising VDAC + 160mV VDAC + 175mV VDAC + 194mV V Overvoltage Hysteresis VSEN falling 90 108 120 mV

SWITCHING TIME (Note 3)

UGATE Rise Time t

RUGATE; VPVCC

= 12V , 3nF load, 10% to

90%

LGATE Rise Time t

UGATE Fall Time t

LGATE Fall Time t

RLGATE; VPVCC

90%

FUGATE; VPVCC

10%

FLGATE; VPVCC

= 12V, 3nF load, 10% to

= 12V , 3nF load, 90% to

= 12V, 3nF load, 90% to

10%

UGATE Turn-On Non-Overlap t

LGATE Turn-On Non-Overlap t

PDHUGATE

adaptive

PDHLGATE

adaptive

; V

= 12V, 3nF load,

PVCC

= 12V, 3nF load,

PVCC

GATE DRIVE RESISTANCE (Note 3)

Upper Drive Source Resistance V Upper Drive Sink Resistance V Lower Drive Source Resistance V Lower Drive Sink Resistance V

= 12V, 15mA source current - 2.0 - Ω

PVCC

= 12V, 15mA sink current - 1.35 - Ω

PVCC

= 12V, 15mA source current - 1.35 - Ω

PVCC

= 12V, 15mA sink current - 0.90 - Ω

PVCC

OVER-TEMPERATURE SHUTDOWN (Note 3)

Thermal Shutdown Setpoint - 160 - °C Thermal Recovery Setpoint - 100 - °C

1.260 1.280 1.300 V

-26-ns

-18-ns

-12-ns

-10-ns

Timing Diagram

UGATE

LGATE

PDHUGATE

FLGATE

RUGATE

PDHLGATE

FUGATE

RLGATE

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ISL6333, ISL6333A, ISL6333B, ISL6333C

Functional Pin Description

VCC

VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1µF ceramic capacitor.

PVCC1 (ISL6333, ISL6333B Only)

This pin is the input to an internal LDO that regulates the voltage on the BYP1 pin and should be connected to a +12V supply. It is very important that this pin is decoupled using a quality 1.0µF ceramic capacitor.

PVCC2_3 (ISL6333, ISL6333B Only)

This pin is the power supply pin for Channels 2 and 3 lower MOSFET drivers, and should be connected to a +12V supply. Decouple this pin with a quality 1.0µF ceramic capacitor.

PVCC1, PVCC2, and PVCC3 (ISL6333A, ISL6333C Only)

These pins are the power supply pins for Channels 1, 2, and 3 lower MOSFET drivers, and should be connected to a +12V supply. Decouple these pins with quality 1.0µF ceramic capacitors

PUVCC

This pin is the power supply pin for Channels 1, 2, and 3 upper MOSFET drivers, and can be connected to any voltage from +5V to +12V depending on the desired MOSFET gate-drive level. Decouple this pin with a quality

1.0µF ceramic capacitor.

BYP1 (ISL6333, ISL6333B Only)

This pin is the output of an internal LDO which powers Channel 1 lower MOSFET driver. A quality 1.0µF ceramic capacitor should be placed from this pin to ground.

GND

GND is the bias and reference ground for the IC.

This pin is a threshold-sensitive (approxima tely 0.86V) enable input for the controllers. Held low , this pin disable s controller operation. Pulled high, the pin enables the controller for operation.

A resistor, RFS, tied from this pin to ground sets the channel switching frequency of the controller. Refer to Equation 46 for proper resistor calculation.

The FS pin also determines whether the controllers operate in the coupled inductor mode or the standard inductor mode of operation. Tying the R controllers to operate in standard inductor mode. Tying the R

resistor to VCC sets the controllers to operate in

coupled inductor mode.

resistor to ground will set the

VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7

These are the inputs for the internal DAC that provide the reference voltage for output regulation. These pins respond to TTL logic thresholds. These pins are internally pulled high to approximately 1.2V, by 40µA internal current sources. The internal pull-up current decreases to 0 as the VID voltage approaches the internal pull-up voltage. All VID pins are compatible with external pull-up voltages not exceeding the IC’s bias voltage (VCC).

VSEN and RGND

VSEN and RGND are inputs to the precision dif ferential remote-sense amplifier and should be connected to the sense pins of the remote load.

VDIFF

VDIFF is the output of the differential remote-sense amplifier . The voltage on this pin is equal to the difference between VSEN and RGND.

FB and COMP

These pins are the internal error amplifier inverting input and output respectively. The FB pin, COMP pin, and the VDIFF pins are tied together through external R-C networks to compensate the regulator.

DVC

A series resistor and capacitor can be connected from the DVC pin to the FB pin to compensate and smooth dynamic VID transitions.

IDROOP (ISL6333, ISL6333A Only)

The IDROOP pin is the average channel-current sense output. Connecting this pin directly to FB allows the converter to incorporate output voltage droop proportional to the output current. If voltage droop is not desired leave this pin unconnected.

IMON

The IMON pin is the average channel-current sense output. This pin is used as a load current indicator to monitor the output load current.

APA

This is the Adaptive Phase Alignment set pin. A 100µA current flows into the APA pin and by tying a resistor from this pin to COMP the trip level for the Adaptive Phase Alignment circuitry can be set.

REF

The REF input pin is the positive input of the error amplifier. It is internally connected to the DAC output through a 1kΩ resistor. A cap acitor is used between the REF pin and gro und to smooth the voltage transition during soft-start and Dynamic VID transitions. This pin can also be bypassed to RGND if desired.

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ISL6333, ISL6333A, ISL6333B, ISL6333C

RSET

Connect this pin to VCC through a resistor to set the ef fective value of the internal R recommended a 0.1µF ceramic capacitor be placed in parallel with this resistor for noise immunization.

current sense resistors. It is

ISEN

OFS

The OFS pin provides a means to program a DC current for generating an offset voltage across the resistor between FB and VSEN. The offset current is generated via an external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left unconnected.

ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, and ISEN3+

These pins are used for differentially sensing the corresponding channel output currents. The sensed currents are used for channel balancing, protection and load line regulation.

Connect ISEN1-, ISEN2-, and ISEN3- to the node between the RC sense elements surrounding the inductor of their respective channel. Tie the ISEN+ pins to the VCORE side of their corresponding channel’s sense capacitor.

Tying ISEN3 - to VCC programs the part for two-phase operation.

UGATE1, UGATE2, and UGATE3

Connect these pins to their corresponding upper MOSFET gates through 1.8Ω resistors. These pins are used to control the upper MOSFETs and are monitored for shoot-through prevention purposes.

BOOT1, BOOT2, and BOOT3

These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect these pins to appropriately chosen external bootstrap capacitors. Internal bootstrap diodes connected to the PVCC pin provides the necessary bootstrap charge.

PHASE1, PHASE2, and PHASE3

Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return path for the upper MOSFET drives.

LGATE1, LGATE2, and LGATE3

These pins are used to control the lower MOSFET s. Connect these pins to the corresponding lower MOSFETs’ gates.

A resistor, RSS, placed from SS to ground or VCC, will set the soft-start ramp slope. Refer to Equations 20 and 21 for proper resistor calculation.

On the ISL6333 and ISL6333B the SS pin also determines what voltage level the internal LDO regulates the BYP1 pin to when PSI# is low. Tying the R

resistor to ground

regulates BYP1 to 5.75V. Tying the R regulates BYP1 to 7.75V.

resistor to VCC,

VR_RDY

VR_RDY indicates whether VDIFF is within specified overvoltage and undervoltage limits af ter a fixed de lay from the end of soft-start. It is an open-drain logic output. If VDIFF exceeds these limits, an overcurrent event occurs, or if the part is disabled, VR_RDY is pulled low. VR_RDY is always low prior to the end of soft-start.

PSI#

The PSI# pin is a digital logic input pin used to indicate whether the controllers should be in a low power state of operation or not. When PSI# is HIGH the controllers will run in it’s normal power state. When PSI# is LOW the controllers will change their operating state to improve light load efficiency. The controllers resume normal operation when this pin is pulled HIGH again.

CPURST_N (ISL6333B, ISL6333C Only)

The CPURST_N pin is a digital logic input pin used in conjunction with the PSI# pin to indicate whether the ISL6333B and ISL6333C should be in a lower power state of operation or not. If CPURST_N is high, the operating state of the controllers can be changed to improve light load efficiency by setting PSI# low. If CPURST_N is low, the controllers cannot be put into it’s light load operating state. Once CPURST_N toggles high again, there is a 50ms delay before the controllers are allowed to enter a low power state.

Operation

Multi-phase Power Conversion

Microprocessor load current profiles have changed to the point that using single-phase regulators is no longer a viable solution. Designing a regulator that is cost-effective, thermally sound, and efficient has become a challenge that only multi-phase converters can accomplish. The ISL6333 family of controllers help simplify implementation by integrating vital functions and requiring minimal external components. The block diagrams provide a top level view of multi-phase power conversion using the ISL6333 family of controllers.

Interleaving

The switching of each channel in a multi-phase converter is timed to be symmetrically out-of-phase with each of the other channels. In a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a result, the three-phase converter has a combined ripple frequency 3x greater than the ripple frequency of any one phase. In addition, the peak-to-peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (Equations 1 and 2). Increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification.

FN6520.1

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ISL6333, ISL6333A, ISL6333B, ISL6333C

IL1 + IL2 + IL3, 7A/DIV

, 7A/DIV

PWM3, 5V/DIV

IL2, 7A/DIV

PWM2, 5V/DIV

IL1, 7A/DIV

PWM1, 5V/DIV

1µs/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (I

, IL2, and IL3)

combine to form the AC ripple current and the DC load current. The ripple component has three times the ripple frequency of each individual channel current. Each PWM pulse is terminated 1/3 of a cycle after the PWM pulse of the previous phase. The peak-to-peak current for each phase is about 7A, and the DC components of the inductor currents combine to feed the load.

T o understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel peak-to-peak inductor current.

VINV

----------------------------------------------------------=

–()V

In Equation 1, V

OUT

V⋅IN⋅

and V

⋅

OUT

are the input and output

OUT

(EQ. 1)

voltages respectively, L is the single-channel inductor value, and f

is the switching frequency.

The output capacitors conduct the ripple component of the inductor current. In the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Compare Equation 1 to the expression for the peak-to-peak current after the summation of N symmetrically phase-shifted inductor currents in Equation 2. Peak-to-peak ripple current decreases by an amount proportional to the number of channels. Output voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors.

CPP()

------------------------------------------------------------------- -=

⋅–()V

OUT

⋅

OUT

V⋅IN⋅

(EQ. 2)

VINNV

Another benefit of interleaving is to reduce input ripple current. Input capacitance is determined in part by the maximum input ripple current. Multi-phase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input

capacitance. The example in Figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current.

The converter depicted in Figure 2 delivers 1.5V to a 36A load from a 12V input. The RMS input capacitor current is 5.9A. Compare this to a single-phase conve rter also step ping down 12V to 1.5V at 36A. The single-phase converter has

11.9A

input capacitor current. The single-phase converter

RMS

must use an input capacitor bank with twice the RMS current capacity as the equivalent three-phase converter .

INPUT-CAPACITOR CURRENT, 10A/DIV

CHANNEL 3 INPUT CURRENT

CHANNEL 2 INPUT CURRENT

CHANNEL 1 INPUT CURRENT

1µs/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND

INPUT-CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER

Active Pulse Positioning (APP) Modulated PWM Operation

The controllers use a proprietary Active Pulse Positioning (APP) modulation scheme to control the internal PWM signals that command each channel’s driver to turn their upper and lower MOSFETs on and off. The time interval in which a PWM signal can occur is generated by an internal clock, whose cycle time is the inverse of the switching frequency set by the resistor connected to the FS pin. The advantage of Intersil’s proprietary Active Pulse Positioning (APP) modulator is that the PWM signal has the ability to turn on at any point during this PWM time interval, and turn off immediately after the PWM signal transitions high. This is important because it allows the controllers to quickly respond to output voltage drops associated with current load spikes, while avoiding the ring back affects associated with other modulation schemes.

The PWM output state is driven by the position of the error amplifier output signal, V signal relative to the proprietary modulator ramp waveform as illustrated in Figure 4. At the beginning of each PWM time interval, this modified V internal modulator waveform. As long as the modified V

voltage is lower then the modulator waveform

COMP

voltage, the PWM signal is commanded low. The internal MOSFET driver detects the low state of the PWM signal and

minus the current correction

COMP

signal is compared to the

COMP

FN6520.1

March 19, 2009

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ISL6333, ISL6333A, ISL6333B, ISL6333C

turns off the upper MOSFET and turns on the lower synchronous MOSFET. When the modified V

COMP

voltage crosses the modulator ramp, the PWM output transitions high, turning off the synchronous MOSFET and turning on the upper MOSFET. The PWM signal will remain high until the modified V

voltage crosses the modulator ramp

COMP

again. When this occurs the PWM signal will transition low again.

During each PWM time interval, the PWM signal can only transition high once. Once PWM transitions high it cannot transition high again until the beginning of the next PWM time interval. This prevents the occurrence of double PWM pulses occurring during a single period.

EXTERNAL CIRCUIT

APA

FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION

APA

APA,TRIP

COMP

ISL6333 INTERNAL CIRCUIT

100µA

LOW

PASS

FILTER

ERROR

AMPLIFIER

APA

CIRCUITRY

TO APA

Adaptive Phase Alignment (APA)

To further improve the transient response, the controllers also implement Intersil’s proprietary Adaptive Phase Alignment (APA) technique, which turns on all of the channels together at the same time during large current step, high di/dt transient event s. As Figure 3 sh ows, the APA circuitry works by monitoring the voltage on the APA pin and comparing it to a filtered copy of the voltage on the COMP pin. The voltage on the APA pin is a copy of the COMP pin voltage that has been negatively offset. If the APA pin exceeds the filtered COMP pin voltage an APA event occurs and all of the channels are forced on.

The APA trip level is the amount of DC offset between the COMP pin and the APA pin. This is the voltage excursion that the APA and COMP pin must have during a transient event to activate the Adaptive Phase Alig nment circuitry. This APA trip level is set through a resistor, R connects from the APA pin to the COMP pin. A 100µA current flows across R

into the APA pin to set the APA

APA

trip level as described in Equation 3. An APA trip level of 500mV is recommended for most applications. A 1000pF capacitor , C

, should also be placed across the R

APA

resistor to help with noise immunity.

APA TRIP()RAPA

100 106–×⋅=

APA

, that

APA

(EQ. 3)

Number of Active Channels

The default number of active channels on the controllers is three for 3-phase operation. If 2-phase operation is desired, the ISEN3- pin should be tied to the VCC pin. This will disable Channel 3, so only Channel 1 and 2 will fire. In 2-phase operation all of the Channel 3 pins should be left unconnected including the PHASE3, LGATE3, UGATE3, BOOT3, and ISEN3+ pins.

PSI# (Low Power State) Operation

The controllers are designed to operate in both their normal power state for high efficiency at heavy loads, and a low power state to increase the regulator’s light load efficiency. The power state of the regulator is controlled by the PSI# pin, which is a digital logic input. When this pin is set HIGH the regulators will operate in their normal power state, with all active channels firing in continuous conduction mode (CCM). When the PSI# pin is set LOW the controllers change their operating state to the low power state to increase light load efficiency. The different controllers have different low power operating states as described in Table 1 and the following sections.

TABLE 1. POWER STATE OPERATION DESCRIPTION

CONTROLLER PSI#

ISL6333,

ISL6333B

ISL6333A,

ISL6333C

HIGH 3/2-phase CCM Yes

LOW 1-phase DEM Yes

HIGH 3/2-phase CCM No

LOW 1-phase CCM No

PHASE COUNT

It’s important to note that during soft-start and dynamic VID transitions the PSI# pin is ignored and the controllers are forced to run in their normal power state. The state of the PSI# pin is considered again at the end of a successful soft-start sequence or dynamic VID transition.

ISL6333, ISL6333B LOW POWER STATE

On the ISL6333 and ISL6333B, when the PSI# pin is set LOW, the controllers change their operating state in multiple ways. First, all active channels are turned off accept for Channel 1. Channel 1 continues to operate but does so in diode emulation mode (DEM). DEM only allows the upper and lower MOSFETs to turn on to allow positive current to flow through the output inductor. If the inductor current falls to 0A during a switching cycle, both the lower and upper MOSFET s are turned off to allow no negative current to build up in the inductor. This helps to decrease the conduction losses of the MOSFETs and the inductor at very low load currents.

When the ISL6333 and ISL6333B are operating in DEM, it’s important for the controllers to know whether the output inductors are standard inductors or coupled inductors. PWM operation is optimized for use with coupled inductors by

CCM OR

DEM GVOT

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ISL6333, ISL6333A, ISL6333B, ISL6333C

minimizing switching losses and body-diode conduction losses. The FS pin determines whether the controllers operate in the coupled inductor mode or the standard inductor mode of operation. Tying the FS pin resistor, R

, to ground will set the controllers to operate in standard inductor mode. Tying the R

resistor to VCC sets the

controllers to operate in coupled inductor mode. When PSI# is set LOW, the ISL6333 and ISL6333B also

utilize the new Gate Voltage Optimization Technology (GVOT) to reduce Channel 1 lower MOSFET gate drive voltage. The controllers are designed to optimize the Channel 1 lower MOSFET gate drive voltage to ensure high efficiency in both normal and low power states. In the low power state where the converter load current is low, MOSFET driving loss is a higher percentage of the power loss associated with the lower MOSFET. In low power state, the lower gate drive voltage can therefore be reduced to decrease the driving losses of the lower MOSFETs an d increase the system efficiency. More information about this can be found in the “Gate Voltage Optimization Technology (GVOT) (ISL6333, ISL6333B Only)” on page 27.

When the PSI# pin is set HIGH, the controllers will immediately begin returning the regulator to it’s normal power state, by turning on all the active channels, placing them in CCM mode, and increasing the Channel 1 lower gate drive voltage back to it’s original level.

ISL6333A, ISL6333C LOW POWER STATE

On the ISL6333A and ISL6333C, when the PSI# pin is set LOW, the controllers change their operating state by turning off all active channels accept for Channel 1. This is the only change made to the regulator. Channel 1 continues to operate in CCM just as it does in the normal power state. When the PSI# pin is set HIGH, the controllers immediately begin returning the regulator to it’s normal power state, by turning on all the active channels.

CPURST_N Operation (ISL6333B, ISL6333C Only)

The ISL6333B and ISL6333C both include a CPURST_N pin which can be utilized by microprocessors that have a CPURST_N output. The CPURST_N pin is a digital input used in conjunction with the PSI# pin to indicate whether the controllers should be in a lower power state of operation or not. If CPURST_N is HIGH, the operating state of the controllers is controlled by the PSI# pin. If CPURST_N is LOW, the controllers wi ll onl y run in their n ormal power state and cannot be put into their light load power state. Once CPURST_N toggles HIGH again, there is a 50ms delay before the controllers recognize the state of the PSI# pin.

expense of using expensive heat sinks and exotic magnetic materials.

In order to realize the thermal advantage, it is important that each channel in a multi-phase converter be controlled to carry equal amounts of current at any load level. To achieve this, the currents through each channel must be sensed continuously every switching cycle. The sensed currents, I

, from each active channel are summed together and

SEN

divided by the number of active channels. The resulting cycle average current, I

, provides a measure of the total

AVG

load-current demand on the converter during each switching cycle. Channel current balance is achieved by comparing the sensed current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current-balance method is illustrated in Figure 4, with error correction for Channel 1 represented. In the figure, the cycle average current, I sensed current, I

COMP

NOTE: CHANNEL 3 IS OPTIONAL.

FIGURE 4. CHANNEL-1 PWM FUNCTION AND

FILTER

CURRENT-BALANCE ADJUSTMENT

, is compared with the Channel 1

AVG

, to create an error signal IER.

SEN1

f(s)

SEN1

AVG

MODULATOR

RAMP

WAVEFORM

÷ N

PWM1

SEN3

SEN2

TO GATE CONTROL LOGIC

The filtered error signal modifies the pulse width commanded by V I

toward zero. The same method for error signal

to correct any unbalance and force

COMP

correction is applied to each active channel.

PWM

SWITCHING PERIOD

Channel Current Balance

One important benefit of multi-phase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. By doing this the designer avoids the complexity of driving parallel MOSFETs and the

SEN

FIGURE 5. CONTINUOUS CURRENT SAMPLING

TIME

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ISL6333, ISL6333A, ISL6333B, ISL6333C

Continuous Current Sensing

In order to realize proper current-balance, the currents in each channel are sensed continuously every switching cycle. During this time the current-sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current, I scaled version of the inductor current.

The controllers support inductor DCR current sensing to continuously sense each channel’s current for channel-current balance. The internal circuitry, shown in Figure 6 represents one channel of the controller. This circuitry is repeated for each channel in the converter, but may not be active depending on how many channels are operating.

MOSFET

DRIVER

SENSE

FIGURE 6. INDUCTOR DCR CURRENT SENSING

Inductor windings have a characteristic distributed resistance or DCR (Direct Current Resistance). For simplicity, the inductor DCR is considered as a separate lumped quantity, as shown in Figure 6. The channel current I

, flowing through the inductor, passes through the DCR.

Equation 4 shows the S-domain equivalent voltage, V across the inductor.

VLs() ILsL DCR+⋅()⋅=

A simple R-C network across the inductor (R extracts the DCR voltage, as shown in Figure 6. The voltage across the sense capacitor, V proportional to the channel current I

-----------------------------------------

s()

. This sensed current, I

UGATE

LGATE

ISL6333 INTERNAL

CIRCUIT

SEN

CONFIGURATION

sL⋅

⎛⎞

-------------

⎝⎠

DCR

⋅⋅ 1+()

1C1

DCR I

VC(s)

ISEN

, can be shown to be

⋅⋅=

, is simply a

SEN

DCR

INDUCTOR

VL(s)

VC(s)

ISEN-

ISEN+

RSET

SET

, shown in Equation 5.

and C)

VCC

OUT

(EQ. 4)

(EQ. 5)

If the R

network components are selected such that

1-C1

their time constant matches the inductor L/DCR time constant, then V

is equal to the voltage drop across the

DCR. The capacitor voltage V

effective internal sense resistance, R current through R

ISEN

current. This current, I

, is then replicated across the

. This develops a

ISEN

which is proportional to the inductor

, is continuously sensed and is

SEN

then used by the controllers for load-line regulation, channel-current balancing, and overcurrent detection and limiting. Equation 6 shows that the proportion between the channel-current, I by the value of the effective sense resistance, R

, and the sensed current, I

SEN

ISEN

, is driven

, and

the DCR of the inductor.

DCR

SENIL

The effective internal R

----------------- -

⋅=

ISEN

resistance is important to the

ISEN

(EQ. 6)

current sensing process because it sets the gain of the load line regulation loop as well as the gain of the channel-current balance loop and the overcurrent trip level. The effective internal R through use of the R from the R internal R

ISEN

resistance is user programmable and is set

ISEN

pin to the VCC pin programs the effective

SET

resistance according to Equation 7.

ISEN

--------- -

⋅=

SET

400

pin. Placing a single resistor, R

SET

(EQ. 7)

Output Voltage Setting

The controllers use a digital to analog converter (DAC) to generate a reference voltage based on the logic signals at the VID pins. The DAC decodes the logic signals into one of the discrete voltages shown in Table 2. Each VID pin is pulled up to an internal 1.2V voltage by a weak current source (40µA), which decreases to 0A as the voltage at the VID pin varies from 0 to the internal 1.2V pull-up voltage. External pull-up resistors or active-high output stages can augment the pull-up current sources, up to a voltage of 5V.

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

00000000OFF 00000001OFF

000000101.60000

000000111.59375

000001001.58750

000001011.58125

000001101.57500

000001111.56875

000010001.56250

000010011.55625

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March 19, 2009

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ISL6333, ISL6333A, ISL6333B, ISL6333C

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

000010101.55000

000010111.54375

000011001.53750

000011011.53125

000011101.52500

000011111.51875

000100001.51250

000100011.50625

000100101.50000

000100111.49375

000101001.48750

000101011.48125

000101101.47500

000101111.46875

000110001.46250

000110011.45625

000110101.45000

000110111.44375

000111001.43750

000111011.43125

000111101.42500

000111111.41875

001000001.41250

001000011.40625

001000101.40000

001000111.39375

001001001.38750

001001011.38125

001001101.37500

001001111.36875

001010001.36250

001010011.35625

001010101.35000

001010111.34375

001011001.33750

001011011.33125

001011101.32500

001011111.31875

001100001.31250

001100011.30625

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

001100101.30000

001100111.29375

001101001.28750

001101011.28125

001101101.27500

001101111.26875

001110001.26250

001110011.25625

001110101.25000

001110111.24375

001111001.23750

001111011.23125

001111101.22500

001111111.21875

010000001.21250

010000011.20625

010000101.20000

010000111.19375

010001001.18750

010001011.18125

010001101.17500

010001111.16875

010010001.16250

010010011.15625

010010101.15000

010010111.14375

010011001.13750

010011011.13125

010011101.12500

010011111.11875

010100001.11250

010100011.10625

010100101.10000

010100111.09375

010101001.08750

010101011.08125

010101101.07500

010101111.06875

010110001.06250

010110011.05625

FN6520.1

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ISL6333, ISL6333A, ISL6333B, ISL6333C

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

010110101.05000

010110111.04375

010111001.03750

010111011.03125

010111101.02500

010111111.01875

011000001.01250

011000011.00625

011000101.00000

011000110.99375

011001000.98750

011001010.98125

011001100.97500

011001110.96875

011010000.96250

011010010.95625

011010100.95000

011010110.94375

011011000.93750

011011010.93125

011011100.92500

011011110.91875

011100000.91250

011100010.90625

011100100.90000

011100110.89375

011101000.88750

011101010.88125

011101100.87500

011101110.86875

011110000.86250

011110010.85625

011110100.85000

011110110.84375

011111000.83750

011111010.83125

011111100.82500

011111110.81875

100000000.81250

100000010.80625

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

100000100.80000

100000110.79375

100001000.78750

100001010.78125

100001100.77500

100001110.76875

100010000.76250

100010010.75625

100010100.75000

100010110.74375

100011000.73750

100011010.73125

100011100.72500

100011110.71875

100100000.71250

100100010.70625

100100100.70000

100100110.69375

100101000.68750

100101010.68125

100101100.67500

100101110.66875

100110000.66250

100110010.65625

100110100.65000

100110110.64375

100111000.63750

100111010.63125

100111100.62500

100111110.61875

101000000.61250

101000010.60625

101000100.60000

101000110.59375

101001000.58750

101001010.58125

101001100.57500

101001110.56875

101010000.56250

101010010.55625

FN6520.1

March 19, 2009

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ISL6333, ISL6333A, ISL6333B, ISL6333C

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

101010100.55000

101010110.54375

101011000.53750

101011010.53125

101011100.52500

101011110.51875

101100000.51250

101100010.50625

101100100.50000 11111110OFF 11111111OFF

Voltage Regulation

The integrating compensation network shown in Figure 7, insures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the controllers to include the combined tolerances of each of these elements.

The output of the error amplifier, V modulator waveform to generate the PWM signals. The PWM signals control the timing of the Internal MOSFET drivers and regulate the converter output so that the voltage at FB is equal to the voltage at REF. This will regulate the output voltage to be equal to Equation 8. The internal and external circuitry that controls voltage regulation is illustrated in Figure 7.

OUTVREFVOFS

– V

–=

DROOP

The controllers incorporate an internal differential remote-sense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point resulting in a more accurate means of sensing output voltage. Connect the microprocessor sense pins to the non-inverting input, VSEN, and inverting input, RGND, of the remote-sense amplifier. The remote sense output, V connected to the inverting input of the error amplifier through an external resistor.

, is compared to the

COMP

(EQ. 8)

DIFF

, is

EXTERNAL CIRCUIT ISL6333 INTERNAL CIRCUIT

COMP

VID DAC

DROOP

OUT

FIGURE 7. OUTPUT VOLT AGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

REF

IDROOP

+ V

OFS

VDIFF

VSEN

RGND

)

ERROR

AMPLIFIER

AVG

OFS

DIFFERENTIAL REMOTE-SENSE AMPLIFIER

COMP

In other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output voltage spike that results from fast load current demand changes.

The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit.

As shown in Figure 7, a current proportional to the average current of all active channels, I through a load line regulation resistor R voltage drop across R

is proportional to the output current,

, flows from the IDROOP pin

AVG

. The resulting

effectively creating an output voltage droop with a steady-state value defined as Equation 9:

DROOPIAVGRFB

⋅=

(EQ. 9)

Load Line (Droop) Regulation

Some microprocessor manufacturers require a precisely controlled output resistance. This dependence of output voltage on load current is often termed “droop” or “load line” regulation. By adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load line regulation required by these manufacturers.

The regulated output voltage is reduced by the droop voltage V

. The output voltage as a function of load current is

DROOP

derived by combining Equations 6, 7, 8, and 9.

OUTVREFVOFS

–

In Equation 10, V

⎛⎞

–=

⎜⎟ ⎝⎠

is the reference voltage, V

REF

programmed offset voltage, I the converter, R

is the internal sense resistor connected

ISEN

DCR

OUT

-------------

---------------

⋅⋅⋅

SET

is the total output current of

OUT

400

--------- -

(EQ. 10)

is the

OFS

FN6520.1

March 19, 2009

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ISL6333, ISL6333A, ISL6333B, ISL6333C

to the ISEN+ pin, RFB is the feedback resistor , N is the active number of channels, and DCR is the Inductor DCR value.

Therefore the equivalent loadline impedance, i.e. droop impedance, is equal to Equation 11:

DCR

--------------R

SET

400

--------- -

(EQ. 11)

⋅⋅=

------------

Output-Voltage Offset Programming

The controllers allow the designer to accurately adjust the offset voltage by connecting a resistor, R pin to VCC or GND. When R

is connected between OFS

OFS

and VCC, the voltage across it is regulated to 1.6V. This causes a proportional current (I

) to flow into the OFS pin

OFS

and out of the FB pin, providing a negative offset. If R connected to ground, the voltage across it is regulated to

0.3V, and I

flows into the FB pin and out of the OFS pin,

OFS

providing a positive offset. The offset current flowing through the resistor between VSEN and FB will generate the desired offset voltage which is equal to the product (I These functions are shown in Figures 8 and 9.

VDIFF

OFS

ISL6333 INTERNAL CIRCUIT

VREF

, from the OFS

OFS

x RFB).

OFS

E/A

OFS

VDIFF

OFS

VCC

OFS

FIGURE 9. NEGATIVE OFFSET OUTPUT VOLT AGE

ISL6333 INTERNAL CIRCUIT

VREF

PROGRAMMING

E/A

GND

1.6V

0.3V

VCC

Dynamic VID

Modern microprocessors need to make changes to their core voltage as part of normal operation. They direct the controlle rs to do this by making changes to the VID inputs. The controllers are required to monitor the DAC inputs and respond to on-the-fly VID changes in a controlled manner, supervising a safe output voltage transition without discontinuity or disruption.

1.6V

OFS

GND

FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE

PROGRAMMING

GND

0.3V

VCC

Once the desired output offset voltage has been determined, use Equations 12 and 13 to set R

For Negative Offset (connect R

1.6 RFB⋅

OFS

--------------------------

OFFSET

For Positive Offset (connect R

0.3 RFB⋅

--------------------------

OFS

OFFSET

OFS

to VCC):

(EQ. 12)

to GND):

(EQ. 13)R

The controllers check for VID changes by comparing the internal DAC code to the VID pin inputs on the positive edge of an internal 5.55MHz clock. If a new code is established on the VID inputs and it remains stable for 3 consecutive readings (360ns to 540ns), the controllers recognize the new code and begins incr em en tin g/ de cre me nt in g th e DA C i n

6.25mV steps at a stepping frequency of 1.85MHz. This controlled slew rate of 6.25mV/540ns (11.6mV/µs) continues until the VID input and DAC are equal. Thus, the total time required for a VID change, t of the VID change (ΔV

VID

, is dependent only on the size

DVID

The time required for a ISL6333-based converter to make a

1.6V to 0.5V reference voltage change is about 95µs, as calculated using Equation 14.

DVID

540 10

⋅⋅=

⎛⎞

---------------------

⎝⎠

0.00625

(EQ. 14)

9–

VID

VID “Off” DAC Codes

The Intel VR11 VID tables include “Off” DAC codes, which indicate to the controllers to disable all regulation. Recognition of these codes is slightly different in that they must be stable for 4 consecutive readings of a 5.55MHz clock (540ns to 720ns) to be recognized. Once an “Off” code is recognized the controllers latch off, and must be reset by toggling the EN pin.

FN6520.1

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ISL6333, ISL6333A, ISL6333B, ISL6333C

Compensating Dynamic VID Transitions

During a VID transition, the resulting change in voltage on the FB pin and the COMP pin causes an AC current to flow through the error amplifier compensation components from the FB to the COMP pin. This current then flows through the feedback resistor, R undershoot at the end of the VID transition. In order to ensure the smooth transition of the output voltage during a VID change, a VID-on-the-fly compensation network is required. This network is composed of a resistor and capacitor in series, R

DVC

This VID-on-the-fly compensation network works by sourcing AC current into the FB node to offset the effects of the AC current flowing from the FB to the COMP pin during a VID transition. To create this compensation current the controllers set the voltage on the DVC pin to be 2x the voltage on the REF pin. Since the error amplifier forces the voltage on the FB pin and the REF pin to be equal, the resulting voltage across the series RC between DVC and FB is equal to the REF pin voltage. The RC compensation components, R create the desired amount of compensation current.

FIGURE 10. DYNAMIC VID COMPENSATION NETWORK

The amount of compensation current required is dependant on the modulator gain of the system, K1, and the error amplifier R-C components, R between the FB and COMP pins. Use Equations 15, 16, and 17 to calculate the RC component values, R for the VID-on-the-fly compensation network. For these equations: V is the oscillator ramp amplitude (1.5V); and R the error amplifier R-C components between the FB and COMP pins.

, and can cause the output voltage to overshoot or

and C

VDIFF

REF

, between the DVC and the FB pin.

DVC

and C

DVC

, can then be selected to

DVC

= I

DVC

REF

DAC

is the input voltage for the power train; V

ISL6333 INTERNAL CIRCUIT

and CC, that are in series

ERROR

AMPLIFIER

and C

DVC

and CC are

COMP

DVC

P-P

DVC

-----------

×=

------- -

---------------- -

K1 1–

(EQ. 15)

(EQ. 16)

(EQ. 17)

Driver Operation

Adaptive Zero Shoot-Through Deadtime Control

The integrated drivers incorporate an adaptive deadtime control technique to minimize deadtime and to prevent the upper and lower MOSFETs from conducting simultaneously . This result s in high efficiency from the reduced freewheeling time of the lower MOSFET body-diode conduction. This is accomplished by ensuring either rising gate turns on its MOSFET with minimum and sufficient delay after the other has turned off.

During turn-off of the lower MOSFET, the LGA TE volt age is monitored until it reaches 1.75V. At this time t he UGATE is released to rise. Once the PHASE is high, the advanced adaptive shoot-through circuitry monitors the PHASE and UGA TE voltages during a PWM falling edge and the subsequent UGATE turn-of f. If either the UGATE falls to less than 1.75V above the PHASE or the PHASE falls to less than +0.8V, the LGA TE is released t o turn on.

Internal Bootstrap Device

All three integrated drivers feature an internal bootstrap schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the PHASE node. This reduces voltage stress on the boot to phase pins.

The bootstrap capacitor should have a maximum voltage rating that’s at least 30% above PVCC and its capacitance value can be chosen from Equation 18:

GATE

--------------------------------------

BOOT_CAP

GATE

where Q at V

GS1

control MOSFETs. The ΔV allowable droop in the rail of the upper gate drive.

≥

ΔV

BOOT_CAP

QG1PVCC⋅

----------------------------------

GS1

is the amount of gate charge per upper MOSFET

⋅=

(EQ. 18)

gate-source voltage and NQ1 is the number of

BOOT_CAP

term is defined as the

FN6520.1

March 19, 2009

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ISL6333, ISL6333A, ISL6333B, ISL6333C

1.6

1.4

1.2

1.0

(µF)

0.8

BOOT_CAP

0.6

0.4

0.2 20nC

0.0

= 100nC

GATE

50nC

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0 ΔV

BOOT_CAP

(V)

FIGURE 11. BOOTSTRAP CAPACIT ANCE vs BOOT RIPPLE

1.0µF

VOLTAGE

PVCC1

ISL6333, ISL6333B INTERNAL CIRCUIT

SET BY STATE

GVOT

REG.

OF PSI# AND

SS PINS

EXTERNAL CIRCUIT

+12V

loss associated with the lower MOSFET. In low power state, the lower gate drive voltage can therefore be reduced to decrease the driving losses of the lower MOSFETs and increase the system efficiency.

This gate drive voltage optimization is accomplished by an internal linear regulator that regulates the Channel 1 lower gate drive voltage, LVCC1, to certain levels depending on the state of the PSI# and SS pins. The input and output of this internal regulator is the PVCC1 pin and BYP1 pin, respectively. The regulator input, PVCC1, should be connected to a +12V source and decoupled with a quality

1.0µF ceramic capacitor. The regulator output, BYP1, is internally connected to the lower gate drive of the Channel 1 MOSFET driver, LVCC1. The BYP1 pin should also be decoupled using a quality 1.0µF ceramic capacitor..

12.0 +40°C THERMAL

11.8

11.6

11.4

11.2

11.0

BYP1

LVCC1

LVCC2, LVCC3

UVCC1, UVCC2,

UVCC3

LVCC = LOWER GATE DRIVE UVCC = UPPER GATE DRIVE

+12V

+5V TO

+12V

1.0µ

1.0µF

PVCC2_3

PUVCC

FIGURE 12. INTERNAL GATE DRIVE CONNECTIONS AND

GAVE VOLTAGE OPTIMIZATION (GVOT)

Gate Voltage Optimization Technology (GVOT) (ISL6333, ISL6333B Only)

The ISL6333 and ISL6333B are designed to optimize the Channel 1 lower MOSFET gate drive voltage to ensure high efficiency in both normal and low power states. In the normal power state when the converter load current is high, the conduction losses of the lower MOSFET s play a large role in the overall system efficiency. In normal power state, the lower gate drive voltage should be higher to decrease the conduction losses of the lower MOSFETs and increase the system efficiency. In the low power state, where the converter load current is significantly smaller, MOSFET driving loss becomes a much higher percentage of power

10.8

BYP1, LVCC1 VOLTAGE (V)

10.6

10.4

0 20406080100120

AVERAGE LOAD CURRENT (mA)

FIGURE 13. BYP1, LVCC1 VOLTAGE WHEN PSI# IS HIGH

8.5

8.0

7.5

7.0

6.5

6.0

BYP1, LVCC1 VOLTAGE (V)

5.5

5.0

0 20 40 60 80 100 120

AVERAGE LOAD CURRENT (mA)

RSS TIED TO GND

+40°C THERMAL

RSS TIED TO VCC

FIGURE 14. BYP1, LVCC1 VOLTAGE WHEN PSI# IS LOW

As Figures 13 and 14 illustrate, the internal regulator has been designed so that its output voltage, BYP1, is dependent upon the average load current. In the normal

FN6520.1

March 19, 2009

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ISL6333, ISL6333A, ISL6333B, ISL6333C

power state, when PSI# is high, the ISL6333 and ISL6333B regulate BYP1 to around 11.2V at a 50mA average load current. In the low power state, when PSI# is low, BYP1 is regulated down to one of two voltages depending on the state of the SS pin. If the SS pin is tied to ground through the R

resistor, BYP1 is regulated down to 5.75V at a 50m A

average load current. If the SS pin is tied to VCC through the R

resistor, BYP1 is regulated down to 7.75V at a 50m A

average load current. It is possible to disable the internal GVOT regulator by

shorting the PVCC1 pin to the BYP1 pin. This essentially bypasses the internal regulator setting the Channel 1 lower gate drive voltage, LVCC1, to the voltage input on the PVCC1 pin.

Upper MOSFET Gate Drive Voltage Versatility

The controllers provide the user flexibility in choosing the upper MOSFET gate drive voltage for efficiency optimization. The controllers tie all the upper gate drive rails together to the PUVCC pin. Simply applying a voltage from +5V up to +12V on PUVCC sets all of the upper gate drive rail voltages simultaneously.

Initialization

Prior to initialization, proper conditions must exist on the EN, VCC, PVCC1, PVCC2_3, PUVCC, BYP1 and VID pins. When the conditions are met, the controllers begin soft-start. Once the output voltage is within the proper window of operation, the controllers assert VR_RDY.

ISL6333 INTERNAL CIRCUIT

VCC

PVCC1 PVCC2_3 PUVCC BYP1

POR

CIRCUIT

SOFT-START

AND

FAULT LOGIC

FIGURE 15. POWER SEQUENCING USING

THRESHOLD-SENSITIVE ENABLE (EN) FUNCTION

ENABLE COMPARATOR

0.86V

Enable and Disable

While in shutdown mode, the LGATE and UGATE signals are held low to assure the MOSFETs remain off. The following input conditions must be met before the controllers are released from shutdown mode to begin the soft-start startup sequence:

1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the controllers are guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, the controllers will not inadvertently turn off unless the bias voltage drops substantially (see “Electrical Specifications” on page 13).

2. The voltage on EN must be above 0.86V. The enable comparator holds the controllers in shutdown until the voltage at EN rises above 0.86V. The enable comparator has 104mV of hysteresis to prevent bounce.

3. The driver bias voltage applied at the PVCC1, PVCC2_3, PVCC2, PVCC3, PUVCC, and BYP1 pins must reach the internal power-on reset (POR) rising threshold. Hysteresis between the rising and falling thresholds assure that once enabled, the controllers will not inadvertently turn off unless the bias voltages drops substantially (see “Electrical Specifications” on page 13).

Once all of these conditions are met the controllers will begin the soft-start sequence and will ramp the output voltage up as described in “Soft-Start” on page 28.

Soft-Start

The soft-start function allows the converter to bring up the output voltage in a controlled fashion, resulting in a linear ramp-up. The soft-start sequence is composed of four periods, as shown in Figure 16. Once the controllers are released from shutdown and soft-start begins (as described in “Enable and Disable” on page 28), there will be a fixed delay period, t the controllers will begin the first soft-start ramp, increasing the output voltage until it reaches the 1.1V VBOOT voltage.

The controllers will then regulate the output voltage at 1.1V for another fixed delay period, t end of the t signals. It is recommended that the VID codes be set no later then 50µs into p e r i o d t controllers will initiate the second soft-start ramp, regulating the output voltage up to the VID voltage ± any offset or droop voltage.

The soft-start time is the sum of the 4 periods as shown in Equation 19.

SStd1td2td3td4

, of typically 1.10ms. After this de la y perio d,

, of typically 93µs. At the

period, the controllers will read the VID

+++=

. If the VID code is valid, the

(EQ. 19)

FN6520.1

March 19, 2009

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ISL6333, ISL6333A, ISL6333B, ISL6333C

, 500mV/DIV

OUT

VR_RDY

500µs/DIV

td3t

FIGURE 16. SOFT-START WAVEFORMS

During td2 and td4, the controllers digitally control the DAC voltage change at 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator, which is defined by the resistor R ramp times, t

and td4, can be calculated based on

on the SS pin. The soft-start

Equations 20 and 21:

1.1 R⋅

d4VVID

8103–μs()⋅⋅=

1.1– RSS8103–μs()⋅⋅⋅=

For example, when VID is set to 1.5V and the RSS is set at 100kΩ, the first soft-st art ramp time t second soft-start ramp time t

will be 320µs.

After the DAC voltage reaches the final VID setting, VR_RDY will be set to high with the fixed delay t typical value for t

is 93µs.

(EQ. 20)

(EQ. 21)

will be 880µs and the

. The

disturbance. The FB pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both MOSFETs of f. Once the internal ramping reference exceeds the FB pin potential, the output drives are enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the DAC setting. Should the output be pre-charged to a level exceeding the DAC setting, the output drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage down to the DAC-set level.

Fault Monitoring and Protection

The controllers actively monitor the output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common VR_RDY indicator is provided for linking to external system monitors. The schematic in Figure 18 outlines the interaction between the fault monitors and the VR_RDY signal.

AVG

100µA

1.280V

OCP

DAC

+175mV

OCL

REPEAT FOR

EACH CHANNEL

OCP

SOFT-START, FAULT

AND CONTROL LOGIC

140µA

IMON

OCP

OUTPUT PRECHARGED

ABOVE DAC LEVEL

OUTPUT PRECHARGED

BELOW DAC LEVEL

GND>

t2 t3

(0.5V/DIV)

OUT

EN (5V/DIV)

FIGURE 17. SOFT-START W A VEFORMS FOR ISL6333-BASED

MULTI-PHASE CONVERTER

Pre-Biased Soft-Start

The controllers also have the ability to start up into a pre-charged output, without causing any unnecessary

OVP

VDIFF

0.50xDAC

ISL6333 INTERNAL CIRCUITRY

VR_RDY

FIGURE 18. POWER GOOD AND PROTECTION CIRCUITRY

VR_RDY Signal

The VR_RDY pin is an open-drain logic output that signals whether or not the controllers are regulating the output voltage within the proper levels, and whether any fault conditions exist. This pin should be tied through a resistor to a voltage source that’s equal to or less then VCC.

VR_RDY indicates whether VDIFF is within specified overvoltage and undervoltage limits af ter a fixed de lay from

FN6520.1

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ISL6333, ISL6333A, ISL6333B, ISL6333C

the end of so ft-start. VR_RDY transitions low when an undervoltage, overvoltage, or overcurrent condition is detected or when the controllers are disabled by a reset from EN, POR, or one of the no-CPU VID codes. In the event of an overvoltage or overcurrent condition, or a no-CPU VID code, the controllers latch off and VR_RDY will not return high until EN is toggled and a successful soft-start is completed. In the case of an undervoltage event, VR_RDY will return high when the output voltage rises above the undervoltage hysteresis level. VR_RDY is al ways low pr ior t o the end of soft-start.

Overvoltage Protection

The controllers constantly monitor the difference between the VSEN and RGND voltages to detect if an overvoltage event occurs. During soft-start, while the DAC is ramping up, the overvoltage trip level is the higher of a fixed voltage 1.280V or DAC + 175mV . Upon successful soft-st art, the overvoltage trip level is only DAC + 175mV. When the output voltage rises above the OVP trip level actions are taken by the controllers to protect the microprocessor load.

At the inception of an overvoltage event, LGATE1, LGATE2, and LGATE3 are commanded high and the VR_RDY signal is driven low. This turns on the all of the lower MOSFETs and pulls the output voltage below a level that might cause damage to the load. The LGATE outputs remain high until VDIFF falls 110mV below the OVP threshold that tripped the overvoltage protection circuitry. The controllers will continue to protect the load in this fashion as long as the overvoltage condition recurs. Once an overvoltage condition ends the controllers latch off, and must be reset by toggling EN, or through POR, before a soft-start can be reinitiated.

There is an OVP condition that exists that will not latch off the controllers. During a soft-start sequence, if the VDIFF voltage is above the OVP threshold an overvoltage event will occur, but will be released once VDIFF falls 110mV below the OVP threshold. If VDIFF then rises above the OVP trip threshold a second time, the controllers will be latched off and cannot be restarted until the controllers are reset.

Pre-POR Overvoltage Protection

Prior to the controller and driver bias pins exceeding their POR levels, the controllers are designed to protect the load from any overvoltage events that may occur. This is accomplished by means of an internal 10kΩ resistor tied from PHASE to LGATE, which turns on the lower MOSFET to control the output voltage until the overvoltage event ceases or the input power supply cuts off. For complete protection, the low side MOSFET should have a gate threshold well below the maximum voltage rating of the load/microprocessor.

In the event that during normal operation the controller or driver bias voltages fall back below their POR threshold, the pre-POR overvoltage protection circui try re activates to protect from any more pre-POR overvoltage events.

Undervoltage Detection

The undervoltage threshold is set at DAC*0.50V of the VID code. When the output voltage (VDIFF) is below the undervoltage threshold, VR_RDY gets pulled low. No other action is taken by the controllers. VR_RDY will return high if the output voltage rises above DAC*0.60V.

Open Sense Line Prevention

In the case that either of the remote sense lines, VSEN or GND, become open, the controllers are designed to prevent the regulator from regulating. This is accomplished by means of a small 5µA pull-up current on VSEN, and a pull-down current on RGND. If the sense lines are opened at any time, the voltage difference between V

SEN

and R

GND

will increase until an overvoltage event occurs, at which point overvoltage protection activates and the controllers stop regulating. The control l e r s w i l l be lat c h e d o ff and c a n n o t be restarted until they are reset.

Overcurrent Protection

The controllers take advantage of the proportionality between the load current and the average current, I detect an overcurrent condition. Two different methods of detecting overcurrent events are available on the controllers. The first method continually compares the average sense current with a constant 100µA OCP reference current, as shown in Figure 18. Once the average sense current exceeds the OCP reference current, a comparator triggers the converter to begin overcurrent protection procedures.

For this first method the overcurrent trip threshold is dictated by the DCR of the inductors, the number of active channels, and the RSET pin resistor, R trip level, I

, using this method use Equation 22, where N is

OCP

. To calculate the overcurrent

SET

the number of active channels, DCR is the individual inductor’s DCR, and R

100 106–R

---------------------------------------------------------------

OCP

DCR 400⋅

is the RSET pin resistor value.

SET

N3⋅⋅ ⋅⋅

SET

During VID-on-the-fly transitions the overcurrent trip level for this method is boosted to prevent false overcurrent trip events that can occur. Starting from the beginning of a dynamic VID transition, the overcurrent trip level is boosted to 140µA. The OCP level will stay at this boosted level until 50µs after the end of the dynamic VID transition, at which point it will return to the typical 100µA trip level.

The second method for detecting overcurrent events continuously compares the voltage on the IMON pin, V to the overcurrent protection voltage, V

, as shown in

OCP

Figure 18. The average channel sense current flows out the IMON pin and through R

, creating the IMON pin

IMON

voltage which is proportional to the output current. When the IMON pin voltage exceeds the V

voltage threshold, the

OCP

overcurrent protection circu itry activates. Since th e IMON pin voltage is proportional to the output current, the overcurrent

, to

AVG

(EQ. 22)

IMON

FN6520.1

March 19, 2009

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ISL6333, ISL6333A, ISL6333B, ISL6333C

trip level, I R

IMON

OCP

, can be set by selecting the proper value for

OCP

, as shown in Equation 23.

OCPRSET

-----------------------------------------------------

DCR R

IOUT

N⋅⋅⋅

400⋅⋅

(EQ. 23)

Once the output current exceeds the overcurrent trip level, V

will exceed V

IMON

and a comparator will trigger the

OCP

converter to begin overcurrent protection procedures. At the beginning of an overcurrent shut down, the controllers

turn off both upper and lower MOSFETs and lowers VR_RDY. The controllers will then immediately attempt to soft-start. If the overcurrent fault remains, the trip-retry cycles will continue until either the controllers are disabled or the fault is cleared. If five overcurrent events occur without successfully completing soft-start, the controllers will latch off after the fifth try and must be reset by toggling EN before a soft-start can be re ini tia ted. Not e th at the ene rgy de li ver ed during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard.

OUTPUT CURRENT, 50A/DIV

OUTPUT VOLTAGE, 500mV/DIV

end of the dynamic VID transition, at which point it will return to the typical 140µA trip level.

MOSFETs General Design Guide

This design guide is intended to provide a high-level explanation of the steps necessary to create a multi-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications.

Power Stages

The first step in designing a multi-phase converter is to determine the number of phases. This determination depends heavily on the cost analysis, which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. Generally speaking, the most economical solutions are those in which each phase handles between 25A and 30A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFET s and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heat-dissipating surfaces.

FIGURE 19. OVERCURRENT BEHAVIOR IN HICCUP MODE

Individual Channel Overcurrent Limiting

The controllers have the ability to limit the current in each individual channel without shutting down the entire regulator. This is accomplished by continuously comparing the sensed currents of each channel with a constant 140µA OCL reference current, as shown in Figure 18. If a channel’s individual sensed current exceeds this OCL limit, the UGATE signal of that channel is immediately forced low, and the LGATE signal is forced high. This turns off the upper MOSFET(s), turns on the lower MOSFET(s), and stops the rise of current in that channel, forcing the current in the channel to decrease. That channel’s UGATE signal will not be able to return high until the sensed channel current falls back below the 140µA reference.

During VID-on-the-fly transitions the OCL trip level is boosted to prevent false overcurrent limiting events that can occur. Starting from the beginning of a dynamic VID transition, the overcurrent trip level is boosted to 196µA. The OCL level will stay at this boosted level until 50µs after the

MOSFETS

The choice of MOSFETs depends on the current each MOSFET will be required to conduct, the switching frequency , the capability of the MOSFETs to dissipate heat, and the availability and nature of heat sinking and air flow .

LOWER MOSFET POWER CALCULATION

The calculation for power loss in the lower MOSFET is simple, since virtually all of the loss in the lower MOSFET is due to current conducted through the channel resistance (r output current, I Equation 1), and d is the duty cycle (V

). In Equation 24, IM is the maximum continuous

DS(ON)

LOW 1()rDS ON()

is the peak-to-peak inductor current (see

P-P

OUT/VIN

⎛⎞

⎜⎟

----- N

⎝⎠

LP-P()

----------------------------------------+⋅=

1d–()⋅

(EQ. 24)

An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at I f

, and the length of dead times, td1 and td2, at the beginning

, V

, the switching frequency,

D(ON)

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March 19, 2009

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ISL6333, ISL6333A, ISL6333B, ISL6333C

and the end of the lower-MOSFET conduction interval respectively.

LOW 2()VDON()fS

⎛⎞

⋅⋅=

⎜⎟

------

-----------+

⎝⎠

P-P

⎛⎞

⎜⎟

td1⋅

-----------

------

–

⎜⎟

⎝⎠

P-P

td2⋅+

(EQ. 25)

The total maximum power dissipated in each lower MOSFET is approximated by the summation of P

LOW(1)

and P

LOW(2)

UPPER MOSFET POWER CALCULATION

In addition to r

losses, a large portion of the

DS(ON)

upper-MOSFET losses are due to currents conducted across the input voltage (V

) during switching. Since a substantially

higher portion of the upper-MOSFET losses are dependent on switching frequency , the po wer ca lculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times, the lower-MOSFET body-diode reverse-recovery charge, Q and the upper MOSFET r

conduction loss.

DS(ON)

When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 26, the required time for this commutation is t approximated associated power loss is P

UP 1()VIN

⎛⎞

⋅⋅⋅≈

----- -

⎝⎠

----------+

P-P

⎛⎞

----

⎜⎟

⎝⎠

and the

UP(1)

(EQ. 26)

At turn-on, the upper MOSFET begins to conduct and this transition occurs over a time t approximate power loss is P

⎛⎞

P-P

UP 2()VIN

⋅⋅⋅≈

----------

⎜⎟

–

----- 2

⎝⎠

. In Equation 27, the

UP(2)

⎛⎞

----

⎜⎟

⎝⎠

(EQ. 27)

A third component involves the lower MOSFET reverse-recovery charge, Q

. Since the inductor current has

fully commutated to the upper MOSFET before the lower-MOSFET body diode can recover all of Q

, it is

conducted through the upper MOSFET across VIN. The power dissipated as a result is P

UP 3()VINQrrfS

⋅⋅=

shown in Equation 28.

UP(3)

(EQ. 28)

Finally, the resistive part of the upper MOSFET is given in Equation 29 as P

UP 4()rDS ON()

UP(4).

⎛⎞

⎜⎟

----- N

⎝⎠

P-P

+⋅⋅≈

---------12

(EQ. 29)

The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 26, 27, 28 and 29. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies.

Package Power Dissipation

When choosing MOSFETs it is important to consider the amount of power being dissipated in the integrated drivers located in the controllers. Since there are a total of three drivers in the controller package, the total power dissipated by all three drivers must be less than the maximum allowable power dissipation for the QFN package.

Calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. Exceeding the

maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125°C. The maximum allowable IC power dissipation for the 7x7 QFN package is approximately 3.5W at room temperature. See “Layout Considerations” on page 38 for thermal transfer improvement suggestions.

When designing the controllers into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses, P

Qg_TOT

, due to the gate charge of MOSFETs and the integrated driver’s internal circuitry and their corresponding average driver current can be estimated with Equations 30 and 31, respectively.

Qg_TOTPQg_Q1PQg_Q2IQ

Qg_Q1

Qg_Q2QG2

-- -

⎛⎞

-- -

⋅ QG2NQ2⋅+

⎝⎠

In Equations 30 and 31, P power loss and P loss; the gate charge (Q

PVCC FSWNQ1N

⋅⋅ ⋅⋅⋅=

PVCC FSWNQ2N

⋅⋅⋅⋅=

N⋅

Qg_Q1

is the total lower gate drive power

Qg_Q2

and QG2) is defined at the

VCC⋅++=

PHASE

PHASEFSWIQ

(EQ. 30)

(EQ. 31)

+⋅⋅=

is the total upper gate drive

particular gate to source drive voltage PVCC in the corresponding MOSFET data sheet; I quiescent current with no load at both drive outputs; N N

are the number of upper and lower MOSFETs per phase,

respectively; N I

*VCC product is the quiescent power of the controller

is the number of active phases. The

PHASE

is the driver total

and

without capacitive load and is typically 75mW at 300kHz.

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ISL6333, ISL6333A, ISL6333B, ISL6333C

PVCC

BOOT

PHASE

HI1

LO1

UGATE

GI1R

FIGURE 20. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

PVCC

HI2

LO2

LGATE

GI2

FIGURE 21. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path resistance, P P

, and in the boot strap diode, P

DR_UP

power will be dissipated by the external gate resistors (R and R

) and the internal gate resistors (R

, the lower drive path resistance,

DR_UP

BOOT

. The rest of the

and R

GI1

GI2

) of the MOSFETs. Figures 20 and 21 show the typical upper and lower gate drives turn-on transition path. The total power dissipation in the controller itself, P

, can be roughly

estimated as calculated in Equation 32:

Inductor DCR Current Sensing Component Selection

The controllers sense each individual channel’s inductor current by detecting the voltage across the output inductor DCR of that channel (As described in the “Continuous Current Sensing” on page 21). As Figure 22 illustrates, an R-C network is required to accurately sense the inductor DCR voltage and convert this information into a current, which is proportional to the total output current. The time constant of this R-C network must match the time constant of the inductor L/DCR.

Follow the steps below to choose the component values for this RC network.

1. Choose an arbitrary value fo r C value is 0.1µF.

2. Plug the inductor L and DCR component values, and the value for C1 chosen in step 1, into Equation 33 to calculate the value for R1.

⋅

DCR C

-------------------------

Once the R-C network components have been chosen, the effective internal R R

resistance sets the gain of the load line regulation loop

ISEN

resistance must then be set. The

ISEN

as well as the gain of the channel-current balance loop and the overcurrent trip level. The effective internal R set through a single resistor on the R

UGATE

MOSFET

DRIVER

LGATE

ISL6333 INTERNAL

CIRCUIT

. The recommended

(EQ. 33)

resistance is

ISEN

pin, R

SET

INDUCTOR

VL(s)

DCR

VC(s)

SET

OUT

DRPDR_UPPDR_LOW PBOOTIQ

Qg_Q1

BOOT

DR_UP

DR_LOW

EXT1RG1

---------------------

⎛⎞

HI1

--------------------------------------

⎜⎟

⎝⎠

HI1REXT1

⎛⎞

HI2

--------------------------------------

⎜⎟

⎝⎠

HI2REXT2

GI1

-------------

+= R

LO1

----------------------------------------

LO1REXT1

LO2

----------------------------------------

LO2REXT2

EXT2RG2

VCC⋅()+++=

Qg_Q1

---------------------

⋅=

Qg_Q2

---------------------

⋅=

GI2

-------------

(EQ. 32)

SENSE

SEN

VC(s)

ISEN

ISEN-

ISEN+

RSET

SET

VCC

FIGURE 22. DCR SENSING CONFIGURATION

Use Equation 34 to calculate the value of R

SET

. In Equation 34, DCR is the DCR of the output inductor at room temperature, I

is the desired overcurrent trip level, and

OCP

N is the number of phases. It is recommended that the desired overcurrent trip level, I

, be chosen so that it’s

OCP

30% larger then the maximum load current expected.

FN6520.1

March 19, 2009

Page 34

ISL6333, ISL6333A, ISL6333B, ISL6333C

SET

DCR

----------------------------

100 10

6–

------------- -

⋅⋅=

OCP

400

--------- -

Due to errors in the inductance or DCR it may be necessary to adjust the value of R

to match the time constants

correctly. The ef fects of time constant mismatch can be seen in the form of droop overshoot or undershoot during the initial load transient spike, as shown in Figure 23. Follow the steps below to ensure the R-C and inductor L/DCR time constants are matched accurately.

1. Capture a transient event with the oscilloscope set to about L/DCR/2 (sec/div). For example, with L = 1µH and DCR = 1mΩ, set the oscilloscope to 500µs/div.

2. Record ΔV1 and ΔV2 as shown in Figure 23.

3. Select new values, R resistor based on the original value, R

, for the time constant

1(NEW)

1(OLD)

Equation 35.

V1Δ

----------

1NEW()R1OLD()

4. Replace R

with the new value and check to see that the

⋅=

error is corrected. Repeat the procedure if necessary.

ΔV

ΔI

(EQ. 34)

, using

(EQ. 35)

OUT

TRAN

RLLNR

⋅⋅

---------------------------------------

DCR

SET

⋅=

--------- -

400

(EQ. 37)

In Equation 37, RLL is the loadline resistance; N is the number of active channels; DCR is the DCR of the individual output inductors; and R

is the RSET pin resistor.

SET

If no loadline regulation is required on the ISL6333 and ISL6333A, the IDROO P pin shoul d be left unconnected. To choose the value for R

in this situation, please refer to

“Compensation Without Load-line Regulation” on page 35.

IMON Pin Resistor

A copy of the average sense current flows out of the IMON pin, and a resistor, R

, placed from this pin to ground can

IMON

be used to set the overcurrent protection trip level. Based on the desired overcurrent trip threshold, I resistor, R

IMON

, can be calculated from Equation 38.

IMON

N⋅

⋅

OCP

3.381

-------------- -

⋅=

400

SET

--------------------------------

DCR I

, the IMON pin

OCP

(EQ. 38)R

APA Pin Component Selection

A 100µA current flows into the APA pin and across R set the APA trip level. A 1000pF capacitor, C also be placed across the R immunity. Use Equation 39 to set R

resistor to help with noise

APA

to get the desired

APA

, should

APA trip level. An APA trip level of 500mV is recommended for most applications.

APA

APA TRIP()

---------------------------------

100 106–×

500mV

---------------------------- -

100 106–×

5kΩ===

APA

(EQ. 39)

Compensation

The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals.

FIGURE 23. TIME CONSTANT MISMATCH BEHAVIOR

Loadline Regulation Resistor

If load line regulation is desired on the ISL6333 and ISL6333A, the IDROOP pin should be connected to the FB pin in order for the internal average sense current to flow out across the loadline regulation resistor, labeled R Figure 7. The ISL6333B and ISL6333C always have the load line regulation enabled. The R

resistor value sets

the desired loadline required for the application. The desired loadline, R where V current I

DROOP

------------------------ -= I

, can be calculated by Equation 36

is the desired droop voltage at the full load

Based on the desired loadline, the loadline regulation resistor, RFB, can be calculated from Equation 37.

(EQ. 36)

COMPENSATION WITH LOAD-LINE REGULATION

The load-line regulated converter behaves in a similar manner to a peak current mode controller because the two poles at the output filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, R

and CC. See Figure 24.

Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately, there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator, by compensating the L-C poles and the ESR zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance.

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ISL6333, ISL6333A, ISL6333B, ISL6333C

C2 (OPTIONAL)

FIGURE 24. COMPENSATION CONFIGURATION FOR

LOAD-LINE REGULATED ISL6333 CIRCUIT

COMP

IDROOP

VDIFF

ISL6333

Select a target bandwidth for the compensated system, f0. The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. The values of the compensation components depend on the relationships of f to the L-C pole frequency and the ESR zero frequency. For each of the following three, there is a separate set of equations for the compensation components.

In Equation 40, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent series resistance of the bulk output filter capacitance; and V

P-P

is the peak-to-peak sawtooth signal amplitude, as described in the “Electrical Specifications” on page 13.

Once selected, the compensation values in Equation 40 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to R value of R

while observing the transient performance on an

. Slowly increase the

oscilloscope until no further improvement is noted. Normally, C

will not need adjustment. Keep the value of CC from

Equation 40 unless some performance issue is noted. The optional capacitor C

, is sometimes needed to bypass

noise away from the PWM comparator (see Figure 24). Keep a position available for C

, and be prepared to install a

high-frequency capacitor of between 22pF and 150pF in case any leading edge jitter problem is noted.

Case 1:

------------------------------- -f 2 π LC⋅⋅⋅

CRFB

2 π f0V

----------------------------------------------------------

⋅=

------------------------------------------------------= 2 π V

⋅⋅ ⋅ ⋅

P-PRFBf0

LC⋅⋅⋅ ⋅ ⋅

P-P

Case 2:

Case 3:

------------------------------- 2 π LC⋅⋅⋅

CRFB

-------------------------------------------------------------------------------------- -=

2 π⋅()2f

------------------------------------->

2 π C ESR⋅⋅ ⋅

CRFB

VPP2 π⋅()⋅

---------------------------------------------------------------- -

⋅=

VINESR C⋅⋅

----------------------------------------------------------------- -= 2 π V

-------------------------------------<≤ 2 π C ESR⋅⋅ ⋅

P-PRFB

2 π f0V

----------------------------------------------

P-PRFBf0

P-P

ESR⋅

LC⋅⋅⋅

LC⋅⋅⋅ ⋅ ⋅

L⋅⋅ ⋅ ⋅

L⋅⋅ ⋅ ⋅ ⋅

(EQ. 40)

COMPENSATION WITHOUT LOAD-LINE REGULATION

The non load-line regulated converter is accurately modeled

as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type III controller, as shown in Figure 25, provides the necessary compensation.

FIGURE 25. COMPENSATION CIRCUIT WITHOUT LOAD-LINE

REGULATION

The first step is to choose the desired bandwidth, f

COMP

VSEN

ISL6333

, of the

compensated system. Choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. The type-III compensator has an extra high-frequency pole, f

. This pole can be used for

added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. A good general rule is to choose f higher if desired. Choosing f

=10f0, but it can be

to be lower than 10f0 can

cause problems with too much phase shift below the system bandwidth.

FN6520.1

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ISL6333, ISL6333A, ISL6333B, ISL6333C

CESR⋅

--------------------------------------------

R1R

⋅=

LC⋅ C ESR⋅–

--------------------------------------------= R

-----------------------------------------------------------------------------------------------------=

2 π⋅()2f0f

⋅⋅ ⋅ ⋅ ⋅

⎛⎞

2π

⋅

⎝⎠

---------------------------------------------------------------------------------------- -= V

VIN2 π f

-----------------------------------------------------------------------------------------------------=

2 π⋅()

⋅⋅ ⋅ ⋅ ⋅

f0fHFLCR

⋅⋅ ⋅⋅⋅

2 π f

f0f

LC⋅()RFBV

LC⋅ 1–⋅⋅ ⋅()⋅

LC⋅()RFBV

P-P

(EQ. 41)

P-P

In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in Equation 41, R

is selected arbitrarily. The remaining

compensation components are then selected. In Equation 41, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and V

P-P

is the peak-to-peak sawtooth signal amplitude, as described in the “Electrical Specifications” on page 13.

Output Filter Design

The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. The output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand.

In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ΔI, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, ΔV Capacitors are characterized according to their capacita nce, ESR, and ESL (equivalent series inductance).

MAX

output-voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount as shown in Equation 42.

ΔVESL

-----

⋅ ESR ΔI⋅+≈

(EQ. 42)

The filter capacitor must have sufficiently low ESL and ESR so that ΔV < ΔV

MAX

Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation.

The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current (see “Interleaving” on page 17 and Equation 2), a voltage develops across the bulk capacitor ESR equal to I are selected, the maximum allowable ripple voltage, V

, determines the lower limit on the inductance.

P(MAX)

⎛⎞

⎝⎠

------------------------------------------------------------------- -

⋅≥ (EQ. 43)

ESR

(ESR). Thus, once the output capacitors

C(P-P)

NV⋅

–

⋅⋅

SVINVP-P MAX()

OUT

⋅

OUT

P-

Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ΔV

. This places an upper limit on inductance.

MAX

Equation 44 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. Equation 45 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels.

⋅⋅⋅

2NCV

---------------------------------

()

ΔI

ΔV

MAX

ΔIESR⋅()–⋅≤

(EQ. 44)

At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total

NC⋅⋅

1.25

-----------------------------

()

ΔI

⋅⋅≤

ΔV

ΔI ESR⋅()– VINVO–

MAX

⎛⎞ ⎝⎠

(EQ. 45)

Switching Frequency

There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper MOSFET loss calculation. These effects are

FN6520.1

March 19, 2009

Page 37

ISL6333, ISL6333A, ISL6333B, ISL6333C

outlined in the “MOSFETs General Design Guide” on page 31 and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small output-voltage ripple. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements.

Switching frequency is determined by the selection of the frequency-setting resistor, R are provided to assist in selecting the correct value for R

[]

RT10

10.61 1.035 fS()log⋅()–

500

100

(kΩ)

50k 100k 1M 2M

SWITCHING FREQUENCY (Hz)

FIGURE 26. R

. Figure 26 and Equation 46

vs SWITCHING FREQUENCY

(EQ. 46)

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient enough to handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases.

For a three-phase design, use Figure 27 to determine the input-capacitor RMS current requirement set by the duty cycle, maximum sustained output current (I of the peak-to-peak inductor current (I

Select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25x greater than the maximum input voltage. Figures 28 and 29 provide the same input RMS current information for two-phase and single-phase designs respectively. Use the same approach for selecting the bulk capacitor type and number.

L,(P-P)

) to IO.

), and the ratio

0.3 I

= 0

L(P-P)

)

= 0.25 I

L(P-P)

RMS/

0.2

0.1

INPUT-CAPACITOR CURRENT (I

00.4 1.00.2 0.6 0.8

DUTY CYCLE (V

L(P-P)

= 0.5 I = 0.75 I

IN/VO

)

FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR 3-PHASE CONVERTER

0.3

)

RMS/

0.2

0.1 I

= 0

L(P-P)

= 0.5 I

L(P-P)

INPUT-CAPACITOR CURRENT (I

00.4 1.00.2 0.6 0.8

= 0.75 I

DUTY CYCLE (V

IN/VO

)

FIGURE 28. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR 2-PHASE CONVERTER

0.6

)

RMS

0.4

Low capacitance, high-frequency ceramic cap acitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. The spikes result from the high current slew rate produced by the upper MOSFET turn on and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitics and maximize suppression.

0.2 I

= 0

L(P-P)

= 0.5 I

L(P-P)

INPUT-CAPACITOR CURRENT (I

00.4 1.00.2 0.6 0.8

L(P-P)

FIGURE 29. NORMALIZED INPUT-CAP ACITOR RMS

= 0.75 I

DUTY CYCLE (V

IN/VO

)

CURRENT FOR SINGLE-PHASE CONVERTER

FN6520.1

March 19, 2009

Page 38

ISL6333, ISL6333A, ISL6333B, ISL6333C

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. Careful component selection, layout, and placement minimizes these voltage spikes. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying channel current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes.

There are two sets of critical components in a DC/DC converter using the ISL6333 family of controllers. The power components are the most critical because they switch large amounts of energy. Next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling.

The power components should be placed first, which includes the MOSFET s, input and output capacitors, and the inductors. It is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. Symmetrical layout allows heat to be dissipated equally across all power trains. Equidistant placement of the controller to the power trains it controls through the integrated drivers helps keep the gate drive traces equally short, resulting in equal trace impedances and similar drive capability of all set s of MOSFETs.

When placing the MOSFETs, try to keep the source of the upper FETs and the drain of the lower FETs as close as thermally possible. Input bulk capacitors should be placed close to the drain of the upper FETs and the source of the lower FETs. Locate the output inductors and output capacitors between the MOSFET s and the load. The high-frequency input and output decoupling capacitors (ceramic) should be placed as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to GND next or on the capacitor solder pad.

The critical small components include the bypass capacitors for VCC and PVCC, and many of the components surrounding the controller including the feedback network and current sense components. Locate the VCC/PVCC bypass capacitors as close to the controller as possible. It is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to EMI pick-up.

A multi-layer printed circuit board is recommended. Figure 30 shows the connections of the critical components for the converter. Note that capacitors C each represent numerous physical capacitors. Dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer.

Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to output inductors short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring.

xx(IN)

and C

xx(OUT)

could

Routing UGATE, LGA TE, and PHASE Traces

Great attention should be paid to routing the UGATE, LGATE, and PHASE traces since they drive the power train MOSFETs using short, high current pulses. It is important to size them as large and as short as possible to reduce their overall impedance and inductance. They should be sized to carry at least one ampere of current (0.02” t o 0 . 0 5 ” ) . G o i n g between layers with vias should also be avoided, but if so, use two vias for interconnection when possible.

Extra care should be given to the LGATE traces in particular since keeping their impedance and inductance lo w helps to significantly reduce the possibility of shoot-through. It is also important to route each channels UGATE and PHASE traces in as close proximity as possible to reduce their inductances.

Current Sense Component Placement and Trace Routing

One of the most critical aspects of the controller regulator layout is the placement of the inductor DCR current sense components and traces. The R-C current sense components must be placed as close to their respective ISEN+ and ISEN- pins on the controller as possible.

The sense traces that connect the R-C sense components to each side of the output inductors should be routed on the bottom of the board, away from the noisy switching components located on the top of the board. These traces should be routed side by side, and they should be very thin traces. It’s important to route these traces as far away from any other noisy traces or planes as possible. These traces should pick up as little noise as possible.

Thermal Management

For maximum thermal performance in high current, high switching frequency applications, connecting the thermal GND pad of the controllers to the ground plane with multiple vias is recommended. This heat spreading allows the part to achieve its full thermal potential. It is also recommended that the controllers be placed in a direct path of airflow if possible to help thermally manage the part.

FN6520.1

March 19, 2009

Page 39

(CF1)

ISL6333, ISL6333A, ISL6333B, ISL6333C

RGND

RSET BYP1

+5V VCC

(CF1)

(CF2)

BOOT1

UGATE

SET

+12V

DVC

VDIFF

DVC VSEN

IDROOP

+5V

APA

OFS

COMP

APA

VCC

PVCC1

BOOT1

UGATE1

PHASE1

LGATE1

KEY

HEAVY TRACE ON CIRCUIT PLANE LAYER

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

LOCATE CLOSE TO IC

(MINIMIZE CONNECTION PATH)

BIN1

LOCATE NEAR SWITCHING TRANSISTORS;

(MINIMIZE CONNECTION PATH)

OFS

REF

IMON

REF

ISL6333

VID7 VID6 VID5 VID4 VID3

VID2 VID1 VID0

PSI#

VR_RDY

IMON

GND

ISEN1ISEN1+

PVCC2_3

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2ISEN2+

PUVCC

BOOT3

UGATE3

PHASE3

LGATE3

ISEN3ISEN3+

UGATE

(CF3)

BOOT2

(CF4)

BOOT3

+12V

BIN2

BIN3

HFOUT

)

BOUT

LOAD

LOCATE NEAR LOAD;

(MINIMIZE CONNECTION

PATH)

FIGURE 30. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6520.1

March 19, 2009

Page 40

ISL6333, ISL6333A, ISL6333B, ISL6333C

Package Outline Drawing

L48.7x7

48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06

7.00

PIN 1

INDEX AREA

5.5

44X

0.50 48

PIN #1 INDEX AREA

(4X) 0.15

( 6 . 80 TYP )

( 4 . 30 )

TOP VIEW

TYPICAL RECOMMENDED LAND PATTERN

7.00

0 . 90 ± 0 . 1

( 44X 0 . 5 )

( 48X 0 . 23 )

( 48X 0 . 60 )

48X 0 . 40± 0 . 1

BOTTOM VIEW

SIDE VIEW

0 . 2 REF

DETAIL "X"

0 . 00 MIN. 0 . 05 MAX.

BASE PLANE

4. 30 ± 0 . 15

M0.10 C AB

0.23 +0.07 / -0.05

SEE DETAIL "X"

0.10

SEATING PLANE

C0.08

NOTES:

Dimensions are in millimeters.1. Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Unless otherwise specified, tolerance : Decimal ± 0.05

Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

6. located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN6520.1

March 19, 2009