Datasheet isl6326 Datasheets

Page 1

ISL6326

Data Sheet May 5, 2008

4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing

The ISL6326 controls microprocessor core voltage regulation by driving up to 4 synchronous-rectified buck channels in parallel. Multiphase buck converter architecture uses interleaved timing to multiply channel ripple frequency and reduce input and output ripple currents. Lower ripple results in fewer components, lower component cost, reduced power dissipation, and smaller implementation area.

Microprocessor loads can generate load transients with extremely fast edge rates. The ISL6326 utilizes Intersil’s proprietary Active Pulse Positioning (APP) and Adaptive Phase Alignment (APA) modulation scheme to achieve the extremely fast transient response with fewer output capacitors.

Today’s microprocessors require a tightly regulated output voltage position versus load current (droop). The ISL6326 senses the output current continuously by utilizing patented techniques to measure the voltage across the dedicated current sense resistor or the DCR of the output inductor. Current sensing provides the needed signals for precision droop, channel-current balancing, and overcurrent protection. A programmable integrated temperature compensation function is implemented to effectively compensate for the temperature coefficient of the current sense element. The current limit function provides the overcurrent protection for the individual phase.

A unity gain, differential amplifier is provided for remote voltage sensing. Any potential difference between remote and local grounds can be completely eliminated using the remote-sense amplifier. Eliminating ground differences improves regulation and protection accuracy. The thresholdsensitive enable input is available to accurately coordinate the start up of the ISL6326 with any other voltage rail. Dynamic-VID™ technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting.

FN9262.1

Features

• Proprietary Active Pulse Positioning and Adaptive Phase Alignment Modulation Scheme

• Precision Multiphase Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over Life, Load, Line and

Temperature

- Adjustable Precision Reference-Voltage Offset

• Precision Resistor

or DCR Current Sensing

- Accurate Load-Line Programming

- Accurate Channel-Current Balancing

- Differential Current Sense

• Microprocessor Voltage Identification Input

- Dynamic VID™ T echnology

- 8-Bit VID Input with Selectable VR11 Code and

Extended VR10 Code at 6.25mV Per Bit

• Thermal Monitoring

• Integrated Programmable Temperature Compensation

• Overcurrent Protection and Channel Current Limit

• Overvoltage Protection

• 2-, 3- or 4-Phase Operation

• Adjustable Switching Frequency up to 1MHz Per Phase

• Package Option

- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad

Flat No Leads - Product Outline

- QFN Near Chip Scale Package Footprint; Improves

PCB Efficiency, Thinner in Profile

• Pb-Free (RoHS Compliant)

Ordering Information

PART

NUMBER

(Note)

ISL6326CRZ* ISL6326CRZ 0 to+70 40 Ld 6x6 QFN L40.6x6 ISL6326IRZ* ISL6326IRZ -40 to +85 40 Ld 6x6 QFN L40.6x6 *Add “-T” suffix for tape and reel. Please refer to TB347 for details

on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

TEMP.

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Page 2

ISL6326

Pinout

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VRSEL

OFS

DAC

ISL6326

(40 LD QFN)

TOP VIEW

VID7

11 12 13 14 15 16 17 18 19 20

REF

VR_HOT

39 38 37 36 35 34 33 32 31

COMP

VR_FAN

IDROOP

VR_RDY

GND

VDIFF

RGND SS

VSEN

EN_VTT

TCOMP

EN_PWR

VCC

PWM3

PWM1

ISEN3+

ISEN3-

ISEN2-

ISEN2+

PWM2

PWM4

ISEN4+

ISEN4-

ISEN1-

ISEN1+

FN9262.1

May 5, 2008

Page 3

ISL6326CR Block Diagram

VDIFF

RGND

VSEN

SOFT-START

OVP

FAULT LOGIC

VR_RDY

AND

ISL6326

CLOCK AND

RAMP GENERAT OR

0.875

POWER-ON

RESET (POR)

0.875

EN_VTT

EN_PWR

VRSEL

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

DAC

OFS

REF

COMP

+175mV

DYNAMIC

VID D/A

OFFSET

APP AND APA

MODULATOR

APP AND APA

MODULATOR

APP AND APA

MODULATOR

APP AND APA

MODULATOR

E/A

CHANNEL CURRENT BALANCE AND PEAK

CURRENT LIMIT

CHANNEL

DETECT

PWM1

PWM2

PWM3

PWM4

IDROOP

VR_HOT

VR_FAN

THERMAL

MONITOR

TM TCOMP

TEMPERATURE

COMPENSATION

GAIN ADJUST

OCP

I_TRIP

1 N

TEMPERATURE

COMPENSATION

GND

CHANNEL CURRENT

SENSE

ISEN1+ ISEN1ISEN2+ ISEN2ISEN3+ ISEN3ISEN4+ ISEN4-

FN9262.1

May 5, 2008

Page 4

ISL6326

Typical Application - 4-Phase Buck Converter with External Temperature Compensation

VTT

VR_RDY

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

VRSEL

VR_FAN

VR_HOT

VIN

THERMISTOR

°C

FB IDROOP VDIFF VSEN RGND EN_VTT

EN_PWR

GND

TCOMP

+5V

NTC

ISL6326

OFS FS SS

VIN

+5V

+12V

PVCC

VCC

BOOT

UGATE PHASE

ISL6612

DRIVER

VCCCOMP

DAC

REF

PWM1

ISEN1-

ISEN1+

PWM

+12V

PVCC

VCC

LGATE

GND

BOOT

UGATE PHASE

VIN

ISL6612

PWM2

ISEN2-

ISEN2+

PWM3

ISEN3-

ISEN3+

DRIVER

PWM

+12V

PVCC

VCC

LGATE

GND

BOOT

UGATE PHASE

VIN

µP

LOAD

ISL6612

DRIVER

PWM

PWM4

ISEN4-

ISEN4+

+12V

PVCC

LGATE

GND

BOOT

VIN

VCC

°C

PWM

ISL6612

DRIVER

UGATE PHASE

LGATE

GND

FN9262.1

May 5, 2008

Page 5

ISL6326

Typical Application - 4-Phase Buck Converter with Integrated Temperature Compensation

VTT

VR_RDY

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

VRSEL

VR_FAN

VR_HOT

VIN

FB IDROOP VDIFF VSEN RGND EN_VTT

VCCCOMP

ISL6326

+5V

ISEN1+

ISEN3+

ISEN2+

DAC

REF

ISEN1-

PWM1

PWM3

ISEN3-

ISEN2-

PWM2

+12V

VCC

GND

PWM1

PWM2

VCC

ISL6614

DRIVER

BOOT1

UGATE1 PHASE1

LGATE1

PVCC

BOOT2

UGATE2 PHASE2

LGATE2

PGND

BOOT1

5V TO

12V

VIN

µP

LOAD

+5V

EN_PWR

GND

TCOMP

+5V

NTC

OFS FS SS

ISL6614

PWM4

ISEN4-

ISEN4+

GND

PWM1

PWM2

ISL6614

DRIVER

UGATE1 PHASE1

LGATE1

PVCC

BOOT2

UGATE2 PHASE2

LGATE2

PGND

5V To

12V

VIN

FN9262.1

May 5, 2008

Page 6

ISL6326

Absolute Maximum Ratings

Supply Voltage,(VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V

All Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to V

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV

+ 0.3V

Thermal Information

Thermal Resistance (Notes 1, 2) θ

40 Ld QFN Package. . . . . . . . . . . . . . . 32 3.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

(°C/W) θ

(°C/W)

Operating Conditions

Supply Voltage, (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Ambient Temperature

ISL6326CRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL6326IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

Tech Brief TB379

2. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply VCC = 5VDC; EN_PWR = 5VDC; R

ISEN1 = ISEN2 = ISEN3 = ISEN4 = -70µA

Shutdown Supply VCC = 5VDC; EN_PWR = 0VDC; R

= 100kΩ,

= 100kΩ -1421mA

POWER-ON RESET AND ENABLE

POR Threshold VCC Rising 4.3 4.5 4.7 V

VCC Falling 3.7 3.9 4.2 V

EN_PWR Threshold Rising 0.850 0.875 0.910 V

Hysteresis - 130 - mV Falling 0.720 0.745 0.775 V

EN_VTT Threshold Rising 0.850 0.875 0.910 V

Hysteresis - 130 - mV Falling 0.720 0.745 0.775 V

REFERENCE VOLTAGE AND DAC

System Accuracy of ISL6326CRZ (VID = 1V to 1.6V, T

= 0°C to +70°C)

System Accuracy of ISL6326CRZ (VID = 0.5V to 1V, T

= 0°C to +70°C)

System Accuracy of ISL6326IRZ (VID = 1V to 1.6V, T

= -40°C to +85°C)

System Accuracy of ISL6326IRZ (VID = 0.5V to 1V, T

= -40°C to +85°C)

(Note 3) -0.5 - 0.5 %VID

(Note 3) -0.9 - 0.9 %VID

(Note 3) -0.6 - 0.6 %VID

(Note 3) -1 - 1 %VID

VID Pull-Up -60 -40 -20 µA VID Input Low Level --0.4V VID Input High Level 0.8 - - V VRSEL Input Low Level --0.4V

-1826mA

FN9262.1

May 5, 2008

Page 7

ISL6326

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VRSEL Input High Level 0.8 - - V DAC Source Current -47mA DAC Sink Current - - 300 µA REF Source Current 45 50 55 µA REF Sink Current 45 50 55 µA

PIN-ADJUSTABLE OFFSET

Voltage at OFS Pin Offset resistor connected to ground 380 400 420 mV

Voltage below VCC, offset resistor connected to VCC 1.55 1.600 1.65 V

OSCILLATORS

Accuracy of Switching Frequency Setting R Adjustment Range of Switching Frequency (Note 4) 0.08 - 1.0 MHz Soft-Start Ramp Rate R Adjustment Range of Soft-Start Ramp Rate (Note 4) 0.625 - 6.25 mV/µs

PWM GENERATOR

Sawtooth Amplitude -1.25- V

ERROR AMPLIFIER

Open-Loop Gain R Open-Loop Bandwidth (Note 4) - 80 - MHz Slew Rate (Note 4) - 25 - V/µs Maximum Output Voltage 3.8 4.3 4.9 V Output High Voltage @ 2mA 3.6 - - V Output Low Voltage @ 2mA --1.8V

REMOTE-SENSE AMPLIFIER

Bandwidth (Note 4) - 20 - MHz Output High Current VSEN - RGND = 2.5V -500 - 500 µA Output High Current VSEN - RGND = 0.6 -500 - 500 µA

PWM OUTPUT

PWM Output Voltage LOW Threshold I PWM Output Voltage HIGH Threshold I

CURRENT SENSE AND OVERCURRENT PROTECTION

Sensed Current Tolerance (IDROOP) ISEN1 = ISEN2 = ISEN3 = ISEN4 = 60µA 57 60 63 µA Overcurrent Trip Level for Average Current 72 85 98 µA Peak Current Limit for Individual Channel 100 120 140 µA

THERMAL MONITORING AND FAN CONTROL

TM Input Voltage for VR_FAN Trip 1.55 1.65 1.75 V TM Input Voltage for VR_FAN Reset 1.85 1.95 2.05 V TM Input Voltage for VR_HOT Trip 1.3 1.4 1.5 V TM Input Voltage for VR_HOT Reset 1.55 1.65 1.75 V Leakage Current of VR_FAN With externally pull-up resistor connected to VCC - - 30 µA

= 100kΩ 225 250 275 kHz

= 100kΩ (Notes 5, 6) - 1.563 - mV/µs

= 10kΩ to ground (Note 4) - 96 - dB

= ±500µA - - 0.5 V

LOAD

= ±500µA 4.3 - - V

LOAD

FN9262.1

May 5, 2008

Page 8

ISL6326

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VR_FAN Low Voltage I Leakage Current of VR_HOT With externally pull-up resistor connected to VCC - - 30 µA VR_HOT Low Voltage I

VR READY AND PROTECTION MONITORS

Leakage Current of VR_RDY With externally pull-up resistor connected to VCC - - 30 µA VR_RDY Low Voltage I Undervoltage Threshold VDIFF Falling 48 50 52 %VID VR_RDY Reset Voltage VDIFF Rising 58 60 62 %VID Overvoltage Protection Threshold Before valid VID 1.250 1.275 1.300 V

After valid VID, the voltage above VID 150 175 200 mV

Overvoltage Protection Reset Hysteresis - 100 - mV

NOTES:

3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.

4. Spec limits established by characterization and are not production tested.

5. During soft-start, VDAC rises from 0V to 1.1V first and then ramp to VID voltage after receiving valid VID.

6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.

= 4mA - - 0.4 V

VR_FAN

= 4mA - - 0.4 V

VR_HOT

= 4mA - - 0.4 V

VR_RDY

FN9262.1

May 5, 2008

Page 9

ISL6326

Functional Pin Description

VCC

Supplies the power necessary to operate the chip. The controller starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. Connect this pin directly to a +5V supply.

GND

Bias and reference ground for the IC. The bottom metal base of ISL6326 is the GND.

EN_PWR

This pin is a threshold-sensitive enable input for the controller. Connecting the 12V supply to EN_PWR through an appropriate resistor divider provides a means to synchronize power-up of the controller and the MOSFET driver ICs. When EN_PWR is driven above 0.875V, the ISL6326 is active depending on status of EN_VTT, the internal POR, and pending fault states. Driving EN_PWR below 0.745V will clear all fault states and prime the ISL6326 to soft-start when re-enabled.

EN_VTT

This pin is another threshold-sensitive enable input for the controller. It’s typically connected to VTT output of VTT voltage regulator in the computer mother board. When EN_VTT is driven above 0.875V, the ISL6326 is active depending on status of EN_PWR, the internal POR, and pending fault states. Driving EN_VTT below 0.745V will clear all fault states and prime the ISL6326 to soft-start when re-enabled.

Use this pin to set up the desired switching frequency. A resistor, placed from FS to ground will set the switching frequency. The relationship between the value of the resistor and the switching frequency will be described by an approximate equation.

Use this pin to set up the desired start-up oscillator frequency. A resistor, placed from SS to ground will set up the soft-start ramp rate. The relationship between the value of the resistor and the soft-start ramp up time will be described by an approximate equation.

VID7, VID6, VID5, VID4, VID3, VID2, VID1 and VID0

These are the inputs to the internal DAC that generates the reference voltage for output regulation. Connect these pins either to open-drain outputs with or without external pull-up resistors or to active pull-up outputs. All VID pins have 40µA internal pull-up current sources that diminish to zero as the voltage rises above the logic-high level. These inputs can be pulled up externally as high as VCC plus 0.3V.

VRSEL

use this pin to select internal VID code. When it is connected to GND, the extended VR10 code is selected. When it’s floated or pulled to high, VR11 code is selected. This input

can be pulled up as high as VCC plus 0.3V.

VDIFF, VSEN, and RGND

VSEN and RGND form the precision differential remotesense amplifier. This amplifier converts the differential voltage of the remote output to a single-ended voltage referenced to local ground. VDIFF is the amplifier ’s output and the input to the regulation and protection circuitry . Connect VSEN and RGND to the sense pins of the remote load.

FB and COMP

Inverting input and output of the error amplifier respectively. FB can be connected to VDIFF through a resistor. A properly chosen resistor between VDIFF and FB can set the load line (droop), when IDROOP pin is tied to FB pin. The droop scale factor is set by the ratio of the ISEN resistors and the inductor DCR or the dedicated current sense resistor. COMP is tied back to FB through an external R-C network to compensate the regulator.

DAC and REF

The DAC pin is the output of the precision internal DAC reference. The REF pin is the positive input of the Error Amp. In typical applications, a 1kΩ, 1% resistor is used between DAC and REF to generate a precision offset voltage. This voltage is proportional to the offset current determined by the offset resistor from OFS to ground or VCC. A capacitor is used between REF and ground to smooth the voltage transition during Dynamic VID™ operations.

PWM1, PWM2, PWM3, PWM4

Pulse width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3 and PWM4. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation.

ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-; ISEN4+, ISEN4-

The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers. The sensed current is used for channel current balancing, overcurrent protection, and droop regulation. Inactive channels should have their respective current sense inputs left open (for example, open ISEN4+ and ISEN4- for 3-phase operation).

For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, R The voltage across the sense capacitor is proportional to the

ISEN

FN9262.1

May 5, 2008

Page 10

ISL6326

inductor current. Therefo re, the sense current is proportional to the inductor current, and scaled by the DCR of the inductor and R

To match the time delay of the internal circuit, a capacitor is needed between each ISEN+ pin and GND, as described in “Current Sensing” on page 12.

ISEN

VR_RDY

VR_RDY indicates that soft-start has completed and the output voltage is within the regulated range around VID setting. It is an open-drain logic output. When OCP or OVP occurs, VR_RDY will be pulled to low. It will also be pulled low if the output voltage is below the undervoltage threshold.

OFS

The OFS pin can be used to program a DC offset current which will generate a DC offset voltage between the REF and DAC pins. The offset current is generated via an external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left unterminated.

TCOMP

Temperature compensation scaling input. The voltage sensed on the TM pin is utilized as the temperature input to adjust ldroop and the overcurrent protection limit to effectively compensate for the temperature coefficient of the current sense element. To implement the integrated temperature compensation, a resistor divider circuit is needed with one resistor being connected from TCOMP to VCC of the controller and another resistor being connected from TCOMP to GND. Changing the ratio of the resistor values will set the gain of the integrated thermal compensation. When integrated temperature compensation function is not used, connect TCOMP to GND.

IDROOP

IDROOP is the output pin of the sensed average channel current which is proportional to the load current. In the application which does not require loadline, this pin can be connected to GND through a resistor to generate a voltage signal, which is proportional the load current and the resistor value. In the application which requires load line, connect this pin to FB so that the sensed average current will flow through the resistor between FB and VDIFF to create a voltage drop which is proportional to load current. Tie this pin to GND if not used.

TM is an input pin for the VR temperature measurement. Connect this pin through an NTC thermistor to GND and a resistor to VCC of the controller. The voltage at this pin is reverse proportional to the VR temperature. ISL6326 monitors the VR temperature based on the voltage at the TM pin and outputs VR_HOT and VR_FAN signals.

VR_HOT

VR_HOT is used as an indication of high VR temperature. It is an open-drain logic output. It will be pulled low if the measured VR temperature is less than a certain level, and open when the measured VR temperature reaches a certain level. A external pull-up resistor is needed.

VR_FAN

VR_FAN is an output pin with open-drain logic output. It will be pulled low if the measured VR temperature is less than a certain level, and open when the measured VR temperature reaches a certain level. An external pull-up resistor is needed.

Operation

Multiphase Power Conversion

Microprocessor load current profiles have changed to the point that the advantages of multiphase power conversion are impossible to ignore. The technical challenges associated with producing a single-phase converter which is both cost-effective and thermally viable have forced a change to the cost-saving approach of multiphase. The ISL6326 controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. The block diagrams on page 3, 4, and 5 provide top level views of multiphase power conversion using the ISL6326 controller.

Interleaving

The switching of each channel in a multiphase converter is timed to be symmetrically out-of-phase with each of the other channels. In a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a result, the 3-phase converter has a combined ripple frequency 3x greater than the ripple frequency of any one phase. In addition, the peak-to-peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (Equations 1 and 2). Increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification.

Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (IL1, IL2, and IL3) combine to form the AC ripple current and the DC load current. The ripple component has 3x the ripple frequency of each individual channel current. Each PWM pulse is terminated 1/3 of a cycle after the PWM pulse of the previous phase. The DC components of the inductor currents combine to feed the load.

FN9262.1

May 5, 2008

Page 11

IL1 + IL2 + IL3, 7A/DIV

IL1, 7A/DIV

PWM1, 5V/DIV

IL2, 7A/DIV

PWM2, 5V/DIV

IL3, 7A/DIV

PWM3, 5V/DIV

1µs/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

T o understand the reduction of ripple current amplitude in the multiphase circuit, examine the equation representing an individual channel’s peak-to-peak inductor current.

VINV

–()V

OUT

------------------------------------------------------=

LfSV

In Equation 1, V

and V

OUT

are the input and output

OUT

(EQ. 1)

voltages respectively, L is the single-channel inductor value, and f

is the switching frequency.

INPUT-CAPACITOR CURRENT, 10A/DIV

CHANNEL 1 INPUT CURRENT 10A/DIV

CHANNEL 2 INPUT CURRENT 10A/DIV

CHANNEL 3 INPUT CURRENT 10A/DIV

1µs/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-

CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER

The output capacitors conduct the ripple component of the inductor current. In the case of multiphase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Compare Equation 1 to the expression for the peak-to-peak current after the summation of N symmetrically phase-shifted inductor currents in Equation 2. Peak-to-peak ripple current decreases by an amount proportional to the number of channels. Output voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple

ISL6326

current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors.

VINNV

–()V

OUT

(EQ. 2)

CP-P()

------------------------------------------------------------= LfSV

Another benefit of interleaving is to reduce input ripple current. Input capacitance is determined in part by the maximum input ripple current. Multiphase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. The example in Figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current.

The converter depicted in Figure 2 delivers 36A to a 1.5V load from a 12V input. The RMS input capacitor current is 5.9A. Compare this to a single-phase conve rter also step ping down 12V to 1.5V at 36A. The single-phase converter has

11.9A

input capacitor current. The single-phase converter

RMS

must use an input capacitor bank with twice the RMS current capacity as the equivalent three-phase converter .

Figures 18, 19 and 20 in the section entitled “Input Capacitor Selection” on page 28 can be used to determine the input-capacitor RMS current based on load current, duty cycle, and the number of channels. They are provided as aids in determining the optimal input capacitor solution. Figure 21 shows the single phase input-capacitor RMS current for comparison.

PWM Modulation Scheme

The ISL6326 adopts Intersil's proprietary Active Pulse Positioning (APP) modulation scheme to improve transient performance. APP control is a unique dual-edge PWM modulation scheme with both PWM leading and trailing edges being independently moved to give the best response to transient loads. The PWM frequency, however , is constant and set by the external resistor between the FS pin and GND. To further improve the transient response, the ISL6326 also implements Intersil's proprietary Adaptive Phase Alignment (APA) technique. APA, with sufficiently large load step currents, can turn on all phases together. With both APP and APA control, ISL6326 can achieve excellent transient performance and reduce the demand on the output capacitors.

Under steady state conditions the operation of the ISL6326 PWM modulator appears to be that of a conventional trailing edge modulator. Conventional analysis and design methods can therefore be used for steady state and small signal operation.

PWM Operation

The timing of each channel is set by the number of active channels. The default channel setting for the ISL6326 is four. The switching cycle is defined as the time between PWM pulse termination signals of each channel. The cycle time of the pulse signal is the inverse of the switching frequency set

FN9262.1

May 5, 2008

Page 12

ISL6326

by the resistor between the FS pin and ground. The PWM signals command the MOSFET driver to turn on/off the channel MOSFETs.

For 4-channel operation, the channel firing order is 4-3-2-1: PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2 output follows another 1/4 of a cycle after PWM3, and PWM1 delays another 1/4 of a cycle after PWM2. For 3-channel operation, the channel firing order is 3-2-1.

Connecting PWM4 to VCC selects three channel operation and the pulse times are spaced in 1/3 cycle increments. If PWM3 is connected to VCC, two channel operation is selected and the PWM2 pulse happens 1/2 of a cycle after PWM pulse.

Switching Frequency

Switching frequency is determined by the selection of the frequency-setting resistor, R

, which is connected from FS

pin to GND (see the figures labeled Typical Applications on page 4 and page 5). Equation 3 is provided to assist in selecting the correct resistor value.

2.5X10

------------------------- -=

where F

is the switching frequency of each phase.

(EQ. 3)

Current Sensing

ISL6326 senses the current continuously for fast response. ISL6326 supports inductor DCR sensing, or resistive sensing techniques. The associated channel current sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current, I I

, is proportional to the inductor current. The sensed

SEN

current is used for current balance, load-line regulation, and overcurrent protection.

The internal circuitry, shown in Figures 3 and 4, represents one channel of an N-channel converter. This circuitry is repeated for each channel in the converter, but may not be active depending on the status of the PWM3 and PWM4 pins, as described in the “PWM Operation” on page 11.

INDUCTOR DCR SENSING

An inductor’s winding is characteristic of a distributed resistance as measured by the DCR (Direct Current Resistance) parameter. Consider the inductor DCR as a separate lumped quantity, as shown in Figure 3. The channel current I

, flowing through the inductor, will also

pass through the DCR. Equation 4 shows the s-domain equivalent voltage across the inductor V

LIL

sL DCR+⋅()⋅=

. The sense current,

(EQ. 4)

A simple RC network across the inductor extracts the DCR voltage, as shown in Figure 3.

The voltage on the capacitor V proportional to the channel current I

⎛⎞

-------------

⋅ 1+

⎝⎠

DCR

---------------------------------------------------------------------

DCR I

sRC 1+⋅()

, can be shown to be

, see Equation 5.

⋅()⋅

(EQ. 5)

If the RC network components are selected such that the RC time constant (= R*C) matches the inductor time constant (= L/DCR), the voltage across the capacitor V

is equal to

the voltage drop across the DCR, i.e., proportional to the channel current.

ISL6605

PWM(n)

ISL6326 INTERNAL CIRCUIT

CURRENT

SENSE

SEN

FIGURE 3. DCR SENSING CONFIGURATION

DCR

-------------------=

ISEN

INDUCTOR

ISEN-(n)

ISEN+(n)

ILs()

VC(s)

DCR

(PTC)

ISEN(n)

OUT

With the internal low-offset current amplifier, the capacitor voltage V Therefore, the current out of ISEN+ pin (I

is replicated across the sense resistor R

SEN

), is

ISEN

proportional to the inductor current. Because of the internal filter at ISEN- pin, one capacitor, C

is needed to match the time delay between the ISEN- and ISEN+ signals. Select the proper C constant of R

ISEN

and CT (R

to keep the time

x CT) close to 27ns.

ISEN

Equation 6 shows that the ratio of the channel current to the sensed current (I

) is driven by the value of the sense

SEN

resistor and the DCR of the inductor.

DCR

SENIL

----------------- -

⋅=

ISEN

(EQ. 6)

FN9262.1

May 5, 2008

Page 13

ISL6326

RESISTIVE SENSING

For accurate current sense, a dedicated current-sense resistor R

in series with each output inductor can

SENSE

serve as the current sense element (see Figure 4). This technique is more accurate, but reduces overall converter efficiency due to the additional power loss on the current sense element R

The same capacitor C between ISEN- and ISEN+ signals. Select the proper C keep the time constant of R

SENSE

is needed to match the time delay

and CT (R

ISEN

x CT) close

ISEN

to 27ns. Equation 7 shows the ratio of the channel current to the

sensed current I

SENIL

FIGURE 4. SENSE RESISTOR IN SERIES WITH INDUCTORS

-----------------------

⋅=

ISL6326 INTERNAL CIRCUIT

CURRENT

SENSE

SEN

SENSE

ISEN

SENSE

--------------------------= R

ISEN

(EQ. 7)

ISEN-(n)

ISEN+(n)

SENSE

ISEN(n)

OUT

The inductor DCR value will increase as the temperature increases. Therefore the sensed current will increase as the temperature of the current sense element increases. In order to compensate the temperature effect on the sensed current signal, a Positive T emperature Coefficient (PTC) resistor can be selected for the sense resistor R

, or the integrated

ISEN

temperature compensation function of ISL6326 should be utilized. The integrated temperature compensation function is described in “Temperature Compensation” on page 22.

Channel-Current Balance

The sensed current In from each active channel is summed together and divided by the number of active channels. The resulting average current (I total load current. Channel current balance is achieved by comparing the sensed current of each channel to the average current to make an appropriate adjustment to the PWM duty cycle of each channel with Intersil’s patented current-balance method.

Channel current balance is essential in achieving the thermal advantage of multiphase operation. With good

) provides a measure of the

AVG

current balance, the power loss is equally dissipated over multiple devices and a greater area.

Voltage Regulation

The compensation network shown in Figure 5 assures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6326 to include the combined tolerances of each of these elements.

The output of the error amplifier (V sawtooth waveforms to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry, which control voltage regulation are illustrated in Figure 5.

EXTERNAL CIRCUIT ISL6326 INTERNAL CIRCUIT

COMP

DAC

REF

AVG

DROOP

IDROOP

VDIFF

VSEN

RGND

OUT

FIGURE 5. OUTPUT VOLT AGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

The ISL6326 incorporates an internal differential remote-sense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point resulting in a more accurate means of sensing output voltage. Connect the microprocessor sense pins to the non-inverting input (VSEN) and inverting input (RGND) of the remote-sense amplifier. The remote-sense output (V

) is connected to the inverting input of the error

DIFF

amplifier through an external resistor. A digital-to-analog converter (DAC) generates a reference

voltage based on the state of logic signals at pins VID7 through VID0. The DAC decodes the eight 6-bit logic signal (VID) into one of the discrete voltages shown in Table 1. Each VID input offers a 45µA pull-up to an internal 2.5V source for use with open-drain outputs. The pull-up current

) is compared to

COMP

ERROR AMPLIFIER

DIFFERENTIAL REMOTE-SENSE AMPLIFIER

COMP

FN9262.1

May 5, 2008

Page 14

ISL6326

diminishes to zero above the logic threshold to protect voltage-sensitive output devices. External pull-up resistors can augment the pull-up current sources if case leakage into the driving device is greater than 45µA.

TABLE 1. VR10 VID T ABLE (WITH 6.25mV EXTENSION)

VID6

VID4

VID3

VID2

VID1

VID0

VID5

400mV

200mV

100mV

50mV

25mV

12.5mV

010101 010101 0 1.59375 010110 010110 010111 1 1.57500 010111 011000 011000 0 1.55625 011001 011001 011010 1 1.53750 011010 011011 011011 011100 1 1.51250 011100 011101 011101 0 1.49375 011110 011110 011111 1 1.47500 011111 100000 100000 100001 100001 100010 100010 100011 100011 100100 100100 100101 100101 100110 100110

6.25mV

VOLTAGE

(V)

1 1.60000

1 1.58750 0 1.58125

0 1.56875 1 1.56250

1 1.55000 0 1.54375

0 1.53125 1 1.52500 0 1.51875

0 1.50625 1 1.50000

1 1.4875 0 1.48125

0 1.46875 1 1.46250 0 1.45625 1 1.45000 0 1.44375 1 1.43750 0 1.43125 1 1.42500 0 1.41875 1 1.41250 0 1.40625 1 1.40000 0 1.39375 1 1.38750 0 1.38125

TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)

VID6

VID4

VID3

VID2

VID1

VID0

VID5

400mV

200mV

100mV

50mV

25mV

12.5mV

100111 1 1.37500 100111 101000 101000 101001 1 1.35000 101001 101010 101010 0 1.33125 101011 101011 101100 1 1.31250 101100 101101 101101 0 1.29375 101110 101110 101111 101111 0 1.26875 110000 110000 110001 1 1.25000 110001 110010 110010 0 1.23125 110011 110011 110100 110100 110101 110101 110110 110110 110111 110111 111000 111000 111001 111001 111010

6.25mV

VOLTAGE

0 1.36875 1 1.36250 0 1.35625

0 1.34375 1 1.33750

1 1.32500 0 1.31875

0 1.30625 1 1.30000

1 1.28750 0 1.28125 1 1.27500

1 1.26250 0 1.25625

0 1.24375 1 1.23750

1 1.22500 0 1.21875 1 1.21250 0 1.20625 1 1.20000 0 1.19375 1 1.18750 0 1.18125 1 1.17500 0 1.16875 1 1.16250 0 1.15625 1 1.15000 0 1.14375 1 1.13750

(V)

FN9262.1

May 5, 2008

Page 15

ISL6326

TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)

VID6

VID4

VID3

VID2

VID1

VID0

VID5

400mV

200mV

100mV

50mV

25mV

12.5mV

111010 0 1.13125 111011 111011 111100 111100 0 1.10625 111101 111101 111110 1OFF 111110 111111 111111 0OFF 000000 000000 000001 1 1.07500 000001 000010 000010 000011 1 1.05000 000011 000100 000100 0 1.03125 000101 000101 000110 1 1.01250 000110 000111 000111 001000 001000 001001 001001 001010 001010 001011 001011 001100 001100 001101 001101

6.25mV

VOLTAGE

(V)

1 1.12500 0 1.11875 1 1.11250

1 1.10000 0 1.09375

0OFF 1OFF

1 1.08750 0 1.08125

0 1.06875 1 1.06250 0 1.05625

0 1.04375 1 1.03750

1 1.02500 0 1.01875

0 1.00625 1 1.00000 0 0.99375 1 0.9875 0 0.98125 1 0.97500 0 0.96875 1 0.9625 0 0.95625 1 0.95000 0 0.94375 1 0.93750 0 0.93125 1 0.92500 0 0.91875

TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)

VID4

VID3

VID2

VID1

VID0

VID5

400mV

200mV

100mV

50mV

25mV

12.5mV

001110 1 0.91250 001110 001111 001111 010000 1 0.88750 010000 010001 010001 0 0.86875 010010 010010 010011 1 0.85000 010011 010100 010100 0 0.83125

TABLE 2. VR11 VID 8-BIT

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

00000000 OFF 00000001 OFF

000000101.60000

000000111.59375

000001001.58750

000001011.58125

000001101.57500

000001111.56875

000010001.56250

000010011.55625

000010101.55000

000010111.54375

000011001.53750

000011011.53125

000011101.52500

000011111.51875

000100001.51250

000100011.50625

000100101.50000

000100111.49375

000101001.48750

000101011.48125

000101101.47500

VID6

VOLTAGE

6.25mV

0 0.90625 1 0.90000 0 0.89375

0 0.88125 1 0.87500

1 0.86250 0 0.85625

0 0.84375 1 0.83750

(V)

FN9262.1

May 5, 2008

Page 16

ISL6326

TABLE 2. VR11 VID 8-BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

0 0 0 1 0 1 1 1 1.46875 0 0 0 1 1 0 0 0 1.46250 0 0 0 1 1 0 0 1 1.45625 0 0 0 1 1 0 1 0 1.45000 0 0 0 1 1 0 1 1 1.44375 0 0 0 1 1 1 0 0 1.43750 0 0 0 1 1 1 0 1 1.43125 0 0 0 1 1 1 1 0 1.42500 0 0 0 1 1 1 1 1 1.41875 0 0 1 0 0 0 0 0 1.41250 0 0 1 0 0 0 0 1 1.40625 0 0 1 0 0 0 1 0 1.40000 0 0 1 0 0 0 1 1 1.39375 0 0 1 0 0 1 0 0 1.38750 0 0 1 0 0 1 0 1 1.38125 0 0 1 0 0 1 1 0 1.37500 0 0 1 0 0 1 1 1 1.36875 0 0 1 0 1 0 0 0 1.36250 0 0 1 0 1 0 0 1 1.35625 0 0 1 0 1 0 1 0 1.35000 0 0 1 0 1 0 1 1 1.34375 0 0 1 0 1 1 0 0 1.33750 0 0 1 0 1 1 0 1 1.33125 0 0 1 0 1 1 1 0 1.32500 0 0 1 0 1 1 1 1 1.31875 0 0 1 1 0 0 0 0 1.31250 0 0 1 1 0 0 0 1 1.30625 0 0 1 1 0 0 1 0 1.30000 0 0 1 1 0 0 1 1 1.29375 0 0 1 1 0 1 0 0 1.28750 0 0 1 1 0 1 0 1 1.28125 0 0 1 1 0 1 1 0 1.27500 0 0 1 1 0 1 1 1 1.26875 0 0 1 1 1 0 0 0 1.26250 0 0 1 1 1 0 0 1 1.25625 0 0 1 1 1 0 1 0 1.25000 0 0 1 1 1 0 1 1 1.24375 0 0 1 1 1 1 0 0 1.23750 0 0 1 1 1 1 0 1 1.23125 0 0 1 1 1 1 1 0 1.22500

TABLE 2. VR11 VID 8-BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

001111111.21875

010000001.21250

010000011.20625

010000101.20000

010000111.19375

010001001.18750

010001011.18125

010001101.17500

010001111.16875

010010001.16250

010010011.15625

010010101.15000

010010111.14375

010011001.13750

010011011.13125

010011101.12500

010011111.11875

010100001.11250

010100011.10625

010100101.10000

010100111.09375

010101001.08750

010101011.08125

010101101.07500

010101111.06875

010110001.06250

010110011.05625

010110101.05000

010110111.04375

010111001.03750

010111011.03125

010111101.02500

010111111.01875

011000001.01250

011000011.00625

011000101.00000

011000110.99375

011001000.98750

011001010.98125

011001100.97500

FN9262.1

May 5, 2008

Page 17

ISL6326

TABLE 2. VR11 VID 8-BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

0 1 1 0 0 1 1 1 0.96875 0 1 1 0 1 0 0 0 0.96250 0 1 1 0 1 0 0 1 0.95625 0 1 1 0 1 0 1 0 0.95000 0 1 1 0 1 0 1 1 0.94375 0 1 1 0 1 1 0 0 0.93750 0 1 1 0 1 1 0 1 0.93125 0 1 1 0 1 1 1 0 0.92500 0 1 1 0 1 1 1 1 0.91875 0 1 1 1 0 0 0 0 0.91250 0 1 1 1 0 0 0 1 0.90625 0 1 1 1 0 0 1 0 0.90000 0 1 1 1 0 0 1 1 0.89375 0 1 1 1 0 1 0 0 0.88750 0 1 1 1 0 1 0 1 0.88125 0 1 1 1 0 1 1 0 0.87500 0 1 1 1 0 1 1 1 0.86875 0 1 1 1 1 0 0 0 0.86250 0 1 1 1 1 0 0 1 0.85625 0 1 1 1 1 0 1 0 0.85000 0 1 1 1 1 0 1 1 0.84375 0 1 1 1 1 1 0 0 0.83750 0 1 1 1 1 1 0 1 0.83125 0 1 1 1 1 1 1 0 0.82500 0 1 1 1 1 1 1 1 0.81875 1 0 0 0 0 0 0 0 0.81250 1 0 0 0 0 0 0 1 0.80625 1 0 0 0 0 0 1 0 0.80000 1 0 0 0 0 0 1 1 0.79375 1 0 0 0 0 1 0 0 0.78750 1 0 0 0 0 1 0 1 0.78125 1 0 0 0 0 1 1 0 0.77500 1 0 0 0 0 1 1 1 0.76875 1 0 0 0 1 0 0 0 0.76250 1 0 0 0 1 0 0 1 0.75625 1 0 0 0 1 0 1 0 0.75000 1 0 0 0 1 0 1 1 0.74375 1 0 0 0 1 1 0 0 0.73750 1 0 0 0 1 1 0 1 0.73125 1 0 0 0 1 1 1 0 0.72500

TABLE 2. VR11 VID 8-BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

100011110.71875

100100000.71250

100100010.70625

100100100.70000

100100110.69375

100101000.68750

100101010.68125

100101100.67500

100101110.66875

100110000.66250

100110010.65625

100110100.65000

100110110.64375

100111000.63750

100111010.63125

100111100.62500

100111110.61875

101000000.61250

101000010.60625

101000100.60000

101000110.59375

101001000.58750

101001010.58125

101001100.57500

101001110.56875

101010000.56250

101010010.55625

101010100.55000

101010110.54375

101011000.53750

101011010.53125

101011100.52500

101011110.51875

101100000.51250

101100010.50625

101100100.50000 11111110 OFF 11111111 OFF

FN9262.1

May 5, 2008

Page 18

ISL6326

Load-Line Regulation

Some microprocessor manufacturers require a precisely-controlled output resistance. This dependence of output voltage on load current is often termed “droop” or “load line” regulation. By adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers.

In other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output voltage spike that results from fast load-current demand changes.

The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit.

As shown in Figure 5, a current proportional to the average current of all active channels (I load-line regulation resistor R across R

is proportional to the output current, effectively

creating an output voltage droop with a steady-state value defined as Equation 8:

DROOPIAVGRFB

The regulated output voltage is reduced by the droop voltage V

. The output voltage as a function of load current is

DROOP

derived by combining Equation 8 with the appropriate sample current expression defined by the current sense method employed in Equation 9.

⎛⎞

OUT

OUTVREFVOFS

Where V

–

is the reference voltage, V

REF

-------------

–=

⎜⎟

⎝⎠

programmed offset voltage, I of the converter, R the ISEN+ pin, and R

is the sense resistor connected to

ISEN

is the feedback resistor, N is the

active channel number, and R depending on the sensing method.

Therefore the equivalent loadline impedance, i.e. Droop impedance, is equal to Equation 10:

------------

----------------- -=

ISEN

) flows from FB through a

AVG

. The resulting voltage drop

----------------- -R R

OUT

ISEN

is the

OFS

is the total output current

is the DCR, or R

SENSE

(EQ. 8)

(EQ. 9)

(EQ. 10)

Output Voltage Offset Programming

The ISL6326 allows the designer to accurately adjust the offset voltage. When a resistor, R OFS to VCC, the voltage across it is regulated to 1.6V. This causes a proportional current (I R

is connected to ground, the voltage across it is

OFS

regulated to 0.4V, and I between DAC and REF, R product (I

OFS

x R

OFS

flows out of OFS. A resistor

OFS

REF

) is equal to the desired offset voltage.

These functions are shown in Figure 6. Once the desired output offset voltage has been determined,

use Equations 11 and 12 to set R For Positive Offset (connect R

1.6 R

REF

OFS

------------------------------

OFFSET

For Negative Offset (connect R

0.4 R

REF

------------------------------

OFS

OFFSET

E/A

1.6V +

0.4V

VCC

FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING

GND

, is connected between

OFS

) to flow into OFS. If

OFS

, is selected so that the

OFS

to VCC):

OFS

to GND):

OFS

DYNAMIC

VID D/A

ISL6326B

(EQ. 11)

(EQ. 12)

DAC

REF

VCC OR

GND

OFS

REF

OFS

FN9262.1

May 5, 2008

Page 19

ISL6326

Dynamic VID

Modern microprocessors need to make changes to their core voltage as part of normal operation. They direct the core voltage regulator to do this by making changes to the VID inputs during regulator operation. The power management solution is required to monitor the DAC inputs and respond to on-the-fly VID changes in a controlled manner. Supervising the safe output voltage transition within the DAC range of the processor without discontinuity or disruption is a necessary function of the core voltage regulator.

In order to ensure the smooth transition of output voltage during VID change, a VID step change smoothing network, composed of R used. The selection of R voltage as detailed above in “Output Voltage Offset Programming” on page 18. The selection of C on the time duration for 1-bit VID change and the allowable delay time.

Assuming the microprocessor controls the VID change at 1-bit every t of R

REF

REFRREFTVID

VID

and C

REF

and C

, as shown in Figure 6, can be

REF

is based on the desired offset

REF

is based

, the relationship between the time constant

REF

network and t

is given by Equation 13:

VID

(EQ. 13)

family of Intersil MOSFET drivers, which require 12V bias.

3. The voltage on EN_VTT must be higher than 0.875V to enable the controller. This pin is typically connected to the output of VTT VR.

ISL6326 INTERNAL CIRCUIT

POR

CIRCUIT

SOFT-START

AND

FAULT LOGIC

ENABLE

COMPARATOR

0.875V

EXTERNAL CIRCUIT

VCC

EN_PWR

EN_VTT

+12V

10kΩ

910Ω

Operation Initialization

Prior to converter initialization, proper conditions must exist on the enable inputs and VCC. When the conditions are met, the controller begins soft-start. Once the output voltage is within the proper window of operation, VR_RDY asserts logic high.

Enable and Disable

While in shutdown mode, the PWM outputs are held in a high-impedance state to assure the drivers remain off. The following input conditions must be met before the ISL6326 is released from shutdown mode.

1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the ISL6326 is guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6326 will not inadvertently turn off unless the bias voltage drops substantially (see “Electrical Specifications” on page 6).

2. The ISL6326 features an enable input (EN_PWR) for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6326 in shutdown until the voltage at EN_PWR rises above 0.875V. The enable comparator has about 130mV of hysteresis to prevent bounce. It is important that the driver ICs reach their POR level before the ISL6326 becomes enabled. The schematic in Figure 7 demonstrates sequencing the ISL6326 with the ISL66xx

FIGURE 7. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (EN) FUNCTION

When all conditions are satisfied, ISL6326 begins the soft-start and ramps the output voltage to 1.1V first. After remaining at 1.1V for some time, ISL6326 reads the VID code at VID input pins. If the VID code is valid, ISL6326 will regulate the output to the final VID setting. If the VID code is OFF code, ISL6326 will shutdown, and cycling VCC, EN_PWR or EN_VTT is needed to restart.

Soft-Start

ISL6326 based VR has 4 periods during soft-start as shown in Figure 8. After VCC, EN_VTT and EN_PWR reach their POR/enable thresholds, The controller will have fixed delay period t soft-start ramp until the output voltage reaches 1.1V V voltage. Then, the controller will regulate the VR voltage at

1.1V for another fixed period t ISL6326 reads the VID signals. If the VID code is valid, ISL6326 will initiate the second soft-start ramp until the voltage reaches the VID voltage minus offset voltage.

The soft-start time is the sum of the 4 periods, as shown in Equation 14:

SStd1td2td3td4

. After this delay period, the VR will begin first

. At the end of td3 period,

+++=

BOOT

(EQ. 14)

FN9262.1

May 5, 2008

Page 20

ISL6326

td1 is a fixed delay with the typical value as 1.36ms. td3 is determined by the fixed 85µs plus the time to obtain valid VID voltage. If the VID is valid before the output reaches the

1.1V, the minimum time to validate the VID input is 500ns. Therefore the minimum t

is about 86µs.

During td2 and td4, ISL6326 digitally controls the DAC voltage change at 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor R second soft-start ramp time t

from SS pin to GND. The

and td4 can be calculated

based on Equations 15 and 16:

1.1xR

----------------------- -

6.25x25 V

------------------------------------------------

VID

6.25x25

μs()=

1.1–()xR

(EQ. 15)

μs()=

(EQ. 16)

For example, when VID is set to 1.5V and the RSS is set at 100kΩ, the first soft-st art ramp time t second soft-start ramp time t

will be 256µs.

will be 704µs and the

After the DAC voltage reaches the final VID setting, VR_RDY will be set to high with the fixed delay t typical value for t

is 85µs.

, 500mV/DIV

OUT

EN_VTT

VR_RDY

FIGURE 8. SOFT-START WAVEFORMS

500µs/DIV

td3td4t

. The

when an undervoltage or overvoltage condition is detected, or the controller is disabled by a reset from EN_PWR, EN_VTT, POR, or VID OFF-code.

Undervoltage Detection

The undervoltage threshold is set at 50% of the VID code. When the output voltage at VSEN is below the undervoltage threshold, VR_RDY is pulled low.

Overvoltage Protection

Regardless of the VR being enabled or not, the ISL6326 overvoltage protection (OVP) circuit will be active after its POR. The OVP thresholds are different under different operation conditions. When VR is not enabled and during the soft-start intervals t

1.275V . Once the controller detects valid VID input, the OVP trip point will be changed to DAC + 175mV.

Two actions are taken by the ISL6326 to protect the microprocessor load when an overvoltage condition occurs.

At the inception of an overvoltage event, all PWM outputs are commanded low instantly (>20ns). This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level to avoid damaging the load. When the VDIFF voltage falls below the DAC + 75mV, PWM signals enter a high-impedance state. The Intersil drivers respond to the high-impedance input by turning off both upper and lower MOSFETs. If the overvoltage condition reoccurs, the ISL6326 will again command the lower MOSFETs to turn on. The ISL6326 will continue to protect the load in this fashion as long as the overvoltage condition occurs.

Once an overvoltage condition is detected, normal PWM operation ceases until the ISL6326 is reset. Cycling the voltage on EN_PWR, EN_VTT or VCC below the POR-falling threshold will reset the controller. Cycling the VID codes will not reset the controller..

, td2 and td3, the OVP threshold is

VR_RDY

Fault Monitoring and Protection

The ISL6326 actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common power good indicator is provided for linking to external system monitors. The schematic in Figure 9 outlin es the interaction between the fault monitors and the VR_RDY signal.

VR_RDY Signal

The VR_RDY pin is an open-drain logic output to indicate that the soft-start period has completed and the output voltage is within the regulated range. VR_RDY is pulled low during shutdown and releases high after a successful soft-start and a fixed delay t

. VR_RDY will be pulled low

50%

DAC

VDIFF

SOFT-START, FAULT

AND CONTROL LOGIC

VID + 0.175V

FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY

May 5, 2008

85µA

AVG

FN9262.1

Page 21

ISL6326

Overcurrent Protection

ISL6326 has two levels of overcurrent protection. Each phase is protected from a sustained overcurrent condition by limiting its peak current, while the combined phase currents are protected on an instantaneous basis.

In instantaneous protection mode, the ISL6326 utilizes the sensed average current I condition. See the “Channel-Current Balance” on page 13 for more detail on how the average current is measured. The average current is continually compared with a constant 85µA reference current, as shown in Figure 9. Once the average current exceeds the reference current, a comparator triggers the converter to shutdown.

At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state within 20ns, commanding the Intersil MOSFET driver ICs to turn off both upper and lower MOSFET s. The system remains in this state a period of 4096 switching cycles. If the controller is still enabled at the end of this wait period, it will attempt a soft-start. If the fault remains, the trip-retry cycles will continue indefinitely (as shown in Figure 10) until either controller is disabled or the fault is cleared. Note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard during this kind of operation.

OUTPUT CURRENT

OUTPUT VOLT AGE

to detect an overcurrent

AVG

Thermal Monitoring (VR_HOT/VR_F AN)

There are two thermal signals to indicate the temperature status of the voltage regulator: VR_HOT and VR_FAN. Both VR_FAN and VR_HOT pins are open-drain outputs, and external pull-up resistors are required. Those signals are valid only after the controller is enabled.

The VR_FAN signal indicates that the temperature of the voltage regulator is high and more cooling airflow is needed. The VR_HOT signal can be used to inform the system that the temperature of the voltage regulator is too high and the CPU should reduce its power consumption. The VR_HOT signal may be tied to the CPU’s PROC_HOT signal.

The diagram of thermal monitoring function block is shown in Figure 11. One NTC resistor should be placed close to the power stage of the voltage regulator to sense the operational temperature, and one pull-up resistor is needed to form the voltage divider for the TM pin. As the temperature of the power stage increases, the resistance of the NTC will reduce, resulting in the reduced voltage at the TM pin. Figure 12 shows the TM voltage over the temperature for a typical design with a recommended 6.8kΩ NTC (P/N: NTHS0805N02N6801 from Vishay) and 1kΩ resistor R We recommend using those resistors for the accurate temperature compensation.

There are two comparators with hysteresis to compare the TM pin voltage to the fixed thresholds for VR_FAN and VR_HOT signals respectively. The VR_FAN signal is set to high when the TM voltage is lower than 33% of VCC voltage, and is pulled to GND when the TM voltage increases to above 39% of VCC voltage. The VR_FAN signal is set to high when the TM voltage goes below 28% of VCC voltage, and is pulled to GND when the TM voltage goes back to above 33% of VCC voltage. Figure 13 shows the operation of those signals.

TM1

FIGURE 10. OVERCURRENT BEHAVIOR IN HICCUP MODE.

= 500kHz

2ms/DIV

For the individual channel overcurrent protection, the ISL6326 continuously compares the sensed current signal of each channel with the 120µA reference current. If one channel current exceeds the reference current, ISL6326 will pull PWM signal of this channel to low for the rest of the switching cycle. This PWM signal can be turned on next cycle if the sensed channel current is less than the 120µA reference current. The peak current limit of individual channel will not trigger the converter to shutdown.

VCC

VR_FAN

TM1

°C

NTC

FIGURE 11. BLOCK DIAGRAM OF THERMAL MONITORING

FUNCTION

0.33V

0.28V

VR_HOT

FN9262.1

May 5, 2008

Page 22

VTM/VCC vs TEMPERATURE

100

80 70

(%)

40 30

0 20 40 60 80 100 120 140

TEMPERATURE (°C)

FIGURE 12. THE RATIO OF TM VOLTAGE TO NTC

TEMPERATURE WITH RECOMMENDED PARTS

0.39*V

0.33*V

0.28*V

ISL6326

temperature coefficient, which is about +0.38%/°C. Since the voltage across inductor is sensed for the output current information, the sensed current has the same po si tive temperature coefficient as the inductor DCR.

In order to obtain the correct current information, there should be a way to correct the temperature impact on the current sense component. ISL6326 provides two methods:

1. Integrated temperature compensation

2. External temperature compensation

Integrated Temperature Compensation

When the TCOMP voltage is equal or greater than VCC/15, ISL6326 will utilize the voltage at TM and TCOMP pins to compensate the temperature impact on the sensed current. The block diagram of this function is shown in Figure 14.

TM1

NON-LINEAR

°C

NTC

A/D

CHANNEL CURRENT

SENSE

SEN4

SEN3

SEN2

SEN1

VR_FAN

VR_HOT

T1 T2 T3

TEMPERATURE

FIGURE 13. VR_HOT AND VR_FAN SIGNAL vs TM VOLTAGE

Based on the NTC temperature characteristics and the desired threshold of the VR_HOT signal, the pull-up resistor R

of TM pin is given by Equation 17:

TM1

NTC(T3)

2.75xR

NTC T3()

(EQ. 17)

is the NTC resistance at the VR_HOT threshold

temperature T3. The NTC resistance at the set point T2 and release point T1

of VR_FAN signal can be calculated in Equations 18 and 19:

1.267xR

NTC T2()

NTC T1()

1.644xR

NTC T3()

(EQ. 18)

(EQ. 19)

With the NTC resistance value obtained from Equations 17 and 18, the temperature value T2 and T1 can be found from the NTC datasheet.

Temperature Compensation

ISL6326 supports inductor DCR sensing, or resistive sensing techniques. The inductor DCR has a positive

TC1

TCOMP

TC2

D/A

4-BIT

A/D

DROOP AND

OVERCURRENT PROTECTION

FIGURE 14. BLOCK DIAGRAM OF INTEGRATED

TEMPERATURE COMPENSATION

When the TM NTC is placed close to the current sense component (inductor), the temperature of the NTC will track the temperature of the current sense component. Therefore the TM voltage can be utilized to obtain the temperature of the current sense component.

Based on VCC voltage, ISL6326 converts the TM pin voltage to a 6-bit TM digital signal for temperature compensation. With the non-linear A/D converter of ISL6326, the TM digital signal is linearly proportional to the NTC temperature. For accurate temperature compensation, the ratio of the TM voltage to the NTC temperature of the practical design should be similar to that in Figure 12.

Depending on the location of the NTC and the airflow, the NTC may be cooler or hotter than the current sense component. The TCOMP pin voltage can be utilized to correct the temperature difference between NTC and the current sense component. When a different NTC type or different voltage divider is used for the TM function, the

FN9262.1

May 5, 2008

Page 23

ISL6326

TCOMP voltage can also be used to compensate for the difference between the recommended TM voltage curve in Figure 13 and that of the actual design. According to the VCC voltage, ISL6326 converts the TCOMP pin voltage to a 4-bit TCOMP digital signal as TCOMP factor N.

The TCOMP factor N is an integer between 0 and 15. The integrated temperature compensation function is disabled for N = 0. For N = 4, the NTC temperature is equal to the temperature of the current sense component. For N < 4, the NTC is hotter than the current sense component. The NTC is cooler than the current sense component for N > 4. When N > 4, the larger TCOMP factor N, the larger the difference between the NTC temperature and the temperature of the current sense component.

ISL6326 multiplexes the TCOMP factor N with the TM digital signal to obtain the adjustment gain to compensate the temperature impact on the sensed channel current. The compensated channel current signal is used for droop and overcurrent protection functions.

Design Procedure

1. Properly choose the voltage divider for the TM pin to match the TM voltage vs temperature curve with the recommended curve in Figure 12.

2. Run the actual board under the full load and the desired cooling condition.

3. After the board reaches the thermal steady state, record the temperature (T (inductor or MOSFET) and the voltage at TM and VCC pins.

4. Use Equation 20 to calculate the resistance of the TM NTC, and find out the corresponding NTC temperature

from the NTC datasheet.

NTC

NTC T

()

NTC

VTMxR

------------------------------- -=

5. Use Equation 21 to calculate the TCOMP factor N:

209x T

()

CSC

--------------------------------------------------------

3xT

NTC

6. Choose an integral number close to the above result for the TCOMP factor. If this factor is higher than 15, use N = 15. If it is less than 1, use N = 1.

7. Choose the pull-up resistor R

8. If N = 15, do not need the pull-down resistor R otherwise obtain R

NxR

TC1

-----------------------

TC2

15 N–

9. Run the actual board under full load again with the proper resistors connected to the TCOMP pin.

10. Record the output voltage as V1 immediately after the output voltage is stable with the full load. Record the output voltage as V2 after the VR reaches the thermal steady state.

) of the current sense component

CSC

TM1

VCCV–

T–

NTC

400+

4+=

(typical 10kΩ).

TC1

by using Equation 22:

TC2

(EQ. 20)

(EQ. 21)

TC2

(EQ. 22)

11. If the output voltage increases over 2mV as the temperature increases, i.e. V2 - V1 > 2mV , reduce N and redesign R

; if the output voltage decreases over 2mV

TC2

as the temperature increases, i.e. V1 - V2 > 2mV, increase N and redesign R

TC2

External Temperature Compensation

By pulling the TCOMP pin to GND, the integrated temperature compensation function is disabled. And one external temperature compensation network (shown in Figure 15) can be used to cancel the temperature impact on the droop (i.e. load line).

ISL6326

INTERNAL CIRCUIT

COMP

IDROOP

°C

VDIFF

FIGURE 15. EXTERNAL TEMPERATURE COMPENSATION

The sensed current will flow out of the IDROOP pin and develop a droop voltage across the resistor equivalent (R between the FB and VDIFF pins. If R

resistance reduces

as the temperature increases, the temperature impact on the droop can be compensated. An NTC resistor can be placed close to the power stage and used to form R

. Due to the

non-linear temperature characteristics of the NTC, a resistor network is needed to make the equivalent resistance between the FB and VDIFF pins reverse proportional to the temperature.

The external temperature compensation network can only compensate the temperature impact on the droop, while it has no impact to the sensed current inside ISL6326. Therefore, this network cannot compensate for the temperature impact on the overcurrent protection function.

Current Sense Output

The current from the IDROOP pin is the sensed average current inside the ISL6326. In typical application, the IDROOP pin is connected to the FB pin for the application where load line is required.

When load line function is not needed, the IDROOP pin can be used to obtain the load current information: with one resistor from the IDROOP pin to GND, the voltage at the IDROOP pin will be proportional to the load current in Equation 23:

IDROOP

----------------------------

----------------- -I R

ISEN

LOAD

(EQ. 23)

)

FN9262.1

May 5, 2008

Page 24

ISL6326

where V

IDROOP

is the resistor between the IDROOP pin and GND, I the total output current of the converter, R

is the voltage at the IDROOP pin, R

is the sense

ISEN

IDROOP

LOAD

resistor connected to the ISEN+ pin, N is the active channel number, and R element, either the DCR of the inductor or R

is the resistance of the current sense

SENSE

depending on the sensing method. The resistor from the IDROOP pin to GND should be chosen

to ensure that the voltage at the IDROOP pin is less than 2V under the maximum load current.

If the IDROOP pin is not used, tie it to GND.

General Design Guide

This design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. It i s assume d that the reader is familiar with many of the basic skills and techniques referenced in the following sections. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications.

Power Stages

The first step in designing a multiphase converter is to determine the number of phases. This determination depends heavily on the cost analysis, which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power-supply circuitry. Generally speaking, the most economical solutions are those in which each phase handles between 15A and 20A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heat-dissipating surfaces.

MOSFETs

The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of the MOSFETs to dissipate heat; and the availability and nature of heat sinking and air flow.

LOWER MOSFET POWER CALCULATION

The calculation for heat dissipated in the lower MOSFET is simple, since virtually all of the heat loss in the lower MOSFET is due to current conducted through the channel resistance (r continuous output current; I

). In Equation 24, IM is the maximum

DS(ON)

is the peak-to-peak inductor

P-P

current (see Equation 1); d is the duty cycle (V

OUT/VIN

); and

L is the per-channel inductance.

1d–()

(EQ. 24)

LOW 1,

DS ON()

⎛⎞

⎜⎟

----- N

⎝⎠

1d–()

L(P-P)

---------------------------------- -+= 12

An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at I f

and the length of dead times, td1 and td2, at the beginning

, V

the switching frequency,

D(ON)

and the end of the lower-MOSFET conduction interval respectively as shown in Equation 25:

LOW 2,

DON()fS

⎛⎞

P-P

----- -

----------+

⎝⎠

⎛⎞

⎜⎟

–

----- -

⎝⎠

P-P

---------2

(EQ. 25)

Thus the total maximum power dissipated in each lower MOSFET is approximated by the summation of P P

LOW,2

LOW,1

and

UPPER MOSFET POWER CALCULATION

In addition to r

losses, a large portion of the

DS(ON)

upper-MOSFET losses are due to currents conducted across the input voltage (V

) during switching. Since a

substantially higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times the lower-MOSFET body-diode reverse-recovery charge (Q r

DS(ON)

conduction loss.

) and the upper MOSFET

When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 26, the required time for this commutation is t approximated associated power loss is P

⎛⎞

≈

UP 1,VIN

⎛⎞

----- -

⎝⎠

----------+

P-P

----

⎜⎟

⎝⎠

and the

UP,1

(EQ. 26)

At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t approximate power loss is P

≈

UP 2,VIN

⎛⎞

⎜⎟

----- N

⎝⎠

⎛⎞

P-P

----------

----

⎜⎟

–

⎝⎠

. In Equation 27, the

UP,2

(EQ. 27)

A third component involves the lower MOSFET’s reverse-recovery charge (Q

). Since the inductor current

has fully commutated to the upper MOSFET before the lower-MOSFET’s body diode can draw all of Q

, it is

FN9262.1

May 5, 2008

Page 25

ISL6326

conducted through the upper MOSFET across VIN. The power dissipated as a result is P

UP 3,

VINQrrf

and is approximately

UP,3

(EQ. 28)

Finally, the resistive part of the upper MOSFET’s is given in Equation 29 as P

UP,4

The total power dissipated by the upper MOSFET at full load can now be approximated as the summa ti on of the resu l ts from Equations 26, 27, and 28. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies.

UP 4,rDS ON()

⎛⎞

⎜⎟

----- N

⎝⎠

d+≈

---------12

(EQ. 29)

Current Sensing Resistor

The resistors connected to the ISEN+ pins determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. Select values for these resistors by using Equation 30:

OCP

ISEN

where R

----------------------85 10

ISEN

------------- -=

–

is the sense resistor connected to the ISEN+ pin, N is the active channel number, R resistance of the current sense element, either the DCR of the inductor or R and I

is the desired overcurrent trip point. Typically , I

OCP

depending on the sensing method,

SENSE

can be chosen to be 1.3x the maximum load current of the specific application.

With integrated temperature compensation, the sensed current signal is independent on the operational temperature of the power stage, i.e. the temperature effect on the current sense element R temperature compensation function. R

is cancelled by the integrated

in Equation 30

should be the resistance of the current sense element at the room temperature.

When the integrated temperature compensation function is disabled by pulling the TCOMP pin to GND, the sensed current will be dependent on the operational temperature of the power stage, since the DC resistance of the current sense element may be changed according to the operational temperature. R

in Equation 30 should be the maximum DC

resistance of the current sense element at the all-operational temperature.

In certain circumstances, it may be necessary to adjust the value of one or more ISEN resistors. When the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, smaller values of RISEN for the affected phases (see the section entitled “Channel-Curr e nt

is the

(EQ. 30)

OCP

Balance” o n page 13). Choose R

in proportion to the

ISEN,2

desired decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase in Equation 31:

ISEN 2,

ISEN

Make sure that ΔT

----------= ΔT

is the desired temperature rise above the

(EQ. 31)

ΔT

ambient temperature, and ΔT1 is the measured temperature rise above the ambient temperature. While a single adjustment according to Equation 31 is usually sufficient, it may occasionally be necessary to adjust R

two or more

ISEN

times to achieve optimal thermal balance between all channels.

Load-Line Regulation Resistor

The load-line regulation resistor is labelled RFB in Figure 5. Its value depends on the desired loadline requirement of the application.

The desired loadline can be calculated by using Equation 32:

DROOP

------------------------ -= I

is the full load current of the specific application,

is the desired voltage droop under the full

DROOP

(EQ. 32)

where I and VR load condition.

Based on the desired loadline R

, the loadline regulation

resistor can be calculated by using Equation 33:

--------------------------------- -=

where N is the active channel number, R

ISEN

(EQ. 33)

is the sense resistor connected to the ISEN+ pin, and RX is the resistance of the current sense element, either the DCR of the inductor or R

depending on the sensing method.

SENSE

If one or more of the current sense resistors are adjusted for thermal balance, as in Equation 31, the load-line regulation resistor should be selected based on the average value of the current sensing resistors, as given in Equation 34:

---------- R

where R

∑

ISEN(n)

ISEN n()

is the current sensing resistor connected to

(EQ. 34)

the nth ISEN+ pin.

Compensation

The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in “Load-Line Regulation” on page 18, there are two distinct methods for achieving these goals.

FN9262.1

May 5, 2008

Page 26

ISL6326

COMPENSATING LOAD-LINE REGULATED CONVERTER

The load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, R

and CC.

Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately, there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator by compensating the L-C poles and the ESR zero of the voltage-mode approximation yields a solution that is always stable with very close to ideal transient performance.

C2 (OPTIONAL)

DROOP

FIGURE 16. COMPENSATION CONFIGURATION FOR

The feedback resistor, R

LOAD-LINE REGULATED ISL6326 CIRCUIT

COMP

IDROOP

ISL6326

VDIFF

, has already been chosen as outlined in “Load-Line Regulation Resistor” on page 25. Select a target bandwidth for the compensated system, f

The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. The values of the compensation components depend on the relationships of f to the L-C pole frequency and the ESR zero frequency. For each of the three cases which follow, there is a separate set of equations for the compensation components.

------------------- f

Case 1:

Case 2:

Case 3:

------------------2π LC

2π LC

CRFB

0.75V

------------------------------------=

2π VPPRFBf

CRFB

-------------------------------------------------------------=

2π()2f

------------------------------>

2π C ESR()

CRFB

0.75VINESR()C

-------------------------------------------------=

2π V

2π f0VppLC

----------------------------------- -=

0.75V

------------------------------<≤

2π C ESR()

VPP2π()2f

--------------------------------------------=

0.75 V

0.75V

VPPRFBLC

2π f0VppL

------------------------------------------=

0.75 V

PPRFBf0

ESR()

(EQ. 35)

In Equation 35, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and V

is the sawtooth

P-P

amplitude described in Electrical Specifications on page 7. The optional capacitor C

, is sometimes needed to bypass

noise away from the PWM comparator (see Figure 16). Keep a position available for C

, and be prepared to install a

high-frequency capacitor of between 22pF and 150pF in case any leading-edge jitter problem is noted.

Once selected, the compensation values in Equation 35 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to R value of R

while observing the transient performance on an

. Slowly increase the

oscilloscope until no further improvement is noted. Normally, C

will not need adjustment. Keep the value of CC from

Equation 35 unless some performance issue is noted.

COMPENSATION WITHOUT LOAD-LINE REGULATION

The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type-III controller, as shown in Figure 17, provides the necessary compensation.

FN9262.1

May 5, 2008

Page 27

ISL6326

FIGURE 17. COMPENSATION CIRCUIT FOR ISL6326 BASED

CONVERTER WITHOUT LOAD-LINE REGULATION

COMP

IDROOP

VDIFF

ISL6326

The first step is to choose the desired bandwidth, f0, of the compensated system. Choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. The type-III compensator has an extra high-frequency pole, f

. This pole can be used for

added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. A good general rule is to choose f higher if desired. Choosing f

= 10f0, but it can be

to be lower than 10f0 can

cause problems with too much phase shift below the system bandwidth.

In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in Equation 36, R

is selected arbitrarily. The remaining

compensation components are then selected.

-----------------------------------------= LC C ESR()–

C ESR()

R1R

Output Filter Design

The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. The output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand.

In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ΔI; the load-current slew rate, di/dt; and the maximum allowable output voltage deviation under transient loading, ΔV their capacitance, ESR, and ESL (equivalent series inductance).

At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount in Equation 37:

ΔV ESL()

. Capacitors are characterized according to

MAX

-----ESR()ΔI+≈ dt

(EQ. 37)

LC C E SR()–

-----------------------------------------=

0.75V

--------------------------------------------------------------------= 2π()2f0fHFLCRFBV

⎛⎞

VPP2π

⎝⎠

---------------------------------------------------------------------=

0.75V

--------------------------------------------------------------------=

f0fHFLCRFBV

2π()

f0fHFLCR

⎛⎞

2π fHFLC 1–

⎝⎠

⎛⎞

2π fHFLC 1–

⎝⎠

(EQ. 36)

P-P

In Equation 36, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and V

is the sawtooth

P-P

signal amplitude as described in “Electrical Specifications” on page 7.

The filter capacitor must have sufficiently low ESL and ESR so that ΔV < ΔV

MAX

Most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation.

The ESR of the bulk capacitors also creates the majority of the output voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current (see “Interleaving” on page 10 and Equation 2), a voltage develops across the bulk-capacitor ESR equal to I

(ESR). Thus, once the

C(P-P)

output capacitors are selected, the maximum allowable ripple voltage, V

P-P(MAX)

, determines the lower limit on the

inductance.

FN9262.1

May 5, 2008

Page 28

ISL6326

⎛⎞

L ESR()

⎝⎠

------------------------------------------------------------≥

–

INNVOUT

fSVINV

OUT

P-P MAX()

(EQ. 38)

Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ΔV

. This places an upper limit on inductance.

MAX

Equation 39 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output voltage deviation than the leading edge. Equation 40 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels.

2NCV

--------------------- ΔV

()

ΔI

()

1.25

------------------------- - ΔV

≤

()

ΔI

MAX

ΔI ESR()–≤

ΔIESR()– VINVO–

⎛⎞ ⎝⎠

(EQ. 39)

(EQ. 40)

0.3

)

RMS

0.2

0.1 I

= 0

L(P-P)

= 0.5 I

L(P-P)

INPUT-CAPACITOR CURRENT (I

L(P-P)

00.4 1.00.2 0.6 0.8

= 0.75 I

DUTY CYCLE (V

O/VIN

)

FIGURE 18. NORMALIZED INPUT- CAP ACITOR RMS CURRENT

vs DUTY CYCLE FOR 2-PHASE CONVERTER

0.3

= 0

L(P-P)

)

RMS/

0.2

L(P-P)

= 0.25 I

L(P-P)

= 0.5 I = 0.75 I

Switching Frequency Selection

There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper-MOSFET loss calculation. These effects are outlined in “MOSFETs” on page 24 and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small output voltage ripple as outlined in “Output Filter Design” on page 27. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements.

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases.

0.1

INPUT-CAPACITOR CURRENT (I

00.4 1.00.2 0.6 0.8 DUTY CYCLE (VO/VIN)

FIGURE 19. NORMALIZED INPUT- CAP ACITOR RMS CURRENT

vs DUTY CYCLE FOR 3-PHASE CONVERTER

For a two-phase design, use Figure 18 to determine the input-capacitor RMS current requirement given the duty cycle, maximum sustained output current (I of the per-phase peak-to-peak inductor current (I I

. Select a bulk capacitor with a ripple current rating which

), and the ratio

L(P-P)

) to

will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25x greater than the maximum input voltage.

FN9262.1

May 5, 2008

Page 29

ISL6326

0.3 I

= 0

L(P-P)

)

RMS/

0.2

0.1

INPUT-CAPACITOR CURRENT (I

= 0.25 I

L(P-P)

00.4 1.00.2 0.6 0.8

L(P-P)

DUTY CYCLE (V

= 0.5 I = 0.75 I

O/VIN

)

FIGURE 20. NORMALIZED INPUT -CAP ACITOR RMS CURRENT

vs DUTY CYCLE FOR 4-PHASE CONVERTER

Figures 19 and 20 provide the same input RMS current information for three and four phase designs respectively. Use the same approach to selecting the bulk capacitor type and number as described previously.

Low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. The result from the high current slew rates produced by the upper MOSFETs turn on and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitic impedances and maximize suppression.

MULTIPHASE RMS IMPROVEMENT

Figure 21 is provided as a reference to demonstrate the dramatic reductions in input-capacitor RMS current upon the implementation of the multiphase topology. For example, compare the input RMS current requirements of a two-phase converter vs that of a single phase. Assume both converters have a duty cycle of 0.25, maximum sustained output current of 40A, and a ratio of I converter would require 17.3A two-phase converter would only require 10.9A

to IO of 0.5. The single phase

L(P-P)

current capacity while the

RMS

. The advantages become even more pronounced when output current is increased and additional phases are added to keep the component cost down relative to the single phase approach.

0.6

)

RMS/

0.4

0.2 I

= 0

L(P-P)

= 0.5 I

L(P-P)

INPUT-CAPACITOR CURRENT (I

00.4 1.00.2 0.6 0.8

L(P-P)

= 0.75 I

DUTY CYCLE (V

O/VIN

)

FIGURE 21. NORMALIZED INPUT-CAP ACITOR RMS

CURRENT vs DUTY CYCLE FOR SINGLE-PHASE CONVERTER

Layout Considerations

The following layout strategies are intended to minimize the impact of board parasitic impedances on converter performance and to optimize the heat-dissipating capabilities of the printed-circuit board. These sections highlight some important practices which should not be overlooked during the layout process.

Component Placement

Within the allotted implementation area, orient the switching components first. The switching components are the most critical because they carry large amounts of energy and tend to generate high levels of noise. Switching component placement should take into account power dissipation. Align the output inductors and MOSFETs such that space between the components is minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals. If possible, duplicate the same placement of these components for each phase.

Next, place the input and output capacitors. Position one highfrequency ceramic input capacitor next to each upper MOSFET drain. Place the bulk input capacitors as close to th e upper MOSFET drains as dictated by the component size and dimensions. Long distances between input capacito rs and MOSFET drains result in too much trace inductance and a reduction in capacitor performance. Locate the output capacitors between the inductors and the load, while keeping them in close proximity to the microprocessor socket.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9262.1

May 5, 2008

Page 30

Package Outline Drawing

L40.6x6

40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06

6.00

PIN 1

INDEX AREA

ISL6326

6.00

4.5

0.50

36X

PIN #1 INDEX AREA

4 . 10 ± 0 . 15

(4X)

( 5 . 8 TYP )

( 4 . 10 )

0.15

TOP VIEW

TYPICAL RECOMMENDED LAND PATTERN

0 . 90 ± 0 . 1

( 36X 0 . 5 )

( 40X 0 . 23 )

( 40X 0 . 6 )

40X 0 . 4 ± 0 . 1

BOTTOM VIEW

SIDE VIEW

0 . 2 REF

0 . 00 MIN.

0 . 05 MAX.

DETAIL "X"

0 . 23 +0 . 07 / -0 . 05

SEE DETAIL "X"

0.10

BASE PLANE

SEATING PLANE

B0.1011MAC

0.08

NOTES:

Dimensions are in millimeters.1. Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Unless otherwise specified, tolerance : Decimal ± 0.05

Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

6. located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN9262.1

May 5, 2008