Datasheet isl6314 Datasheets

Page 1

ISL6314

Data Sheet

Single-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

The ISL6314 single-phase PWM control IC provides a precision voltage regulation system for advanced microprocessors. This controller IC maintains the same features as the multi-phase product family, but reduces the output to a single-phase, for lower current systems. By reducing the number of external parts, this integration is optimized for a cost and space saving power management solution.

One outstanding feature of this controller IC is its multi-processor compatibility, allowing it to work with both Intel and AMD microprocessors. Included are programmable VID codes for Intel VR1 1 as well as AMD 5-bit and 6-bit DAC tables. A circuit is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. The output voltage can also be positively or negatively offset through the use of a single external resistor.

Another unique feature of the ISL6314 is the addition of a circuit that allows optimizing compensation to be added for flatter load transient response and well controlled dynamic VID response.

The ISL6314 also includes advanced control loop features for optimal transient response to load apply and removal. One of these features is highly accurate, fully differential, continuous DCR current sensing for load line programming. Active Pulse Positioning (APP) and Adaptive Phase Alignment (APA) are two other unique features, allowing for quicker initial response to high di/dt load transients; the number of output bulk capacitors can be reduced, helping to reduce cost.

Protection features of this controller IC include a set of sophisticated overvoltage, undervoltage, and overcurrent protection. Furthermore, the ISL6314 includes protection against an open circuit on the remote sensing inputs. Combined, these features provide advanced protection for the microprocessor and power system.

October 8, 2009 FN6455.2

Features

• Integrated-driver Single-Phase Power Conversion

• Precision Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over-Temperature

- Adjustable Reference-Voltage Offset

• Optimal Transient Response

- Adaptive Phase Alignment (APA)

- Active Pulse Positioning (APP) Modulation

• Fully Differential, Continuous DCR Current Sensing

- Accurate Load Line Programming

• Variable Gate Drive Bias: 5V to 12V

• Multi-Processor Compatible

- Intel VR11 Mode of Operation

- AMD Mode of Operation

• Microprocessor Voltage Identification Inputs

- 8-Bit DAC

- Selectable Between Intel VR11, AMD 5-bit, and AMD 6-bit DAC Tables

- Dynamic VID Technology

• Overcurrent Protection

• Multi-tiered Overvoltage Protection

• Digital Soft-Start

• Selectable Operation Frequency up to 1.0MHz

• Pb-Free (RoHS compliant)

Ordering Information

PART

NUMBER

(Note)

ISL6314CRZ* ISL6314 CRZ 0 to +70 32 Ld 5x5 QFN L32.5x5B ISL6314IRZ* ISL6314 IRZ -40 to +85 32 Ld 5x5 QFN L32.5x5B *Add “-T” suffix for tape and reel. Please refer to TB347 for details on

reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

TEMP.

RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG . #

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Page 2

Pinout

ISL6314ISL6314

ISL6314

(32 LD QFN)

TOP VIEW

VID0

VID7

32 31 30 29 28 27 26 25

PGOOD

REF

OFS

APA

COMP

DVC

9 10111213141516

VDIFF

ISL6314 Integrated Driver Block Diagram

VID1

RGND

VID2

GND

VSEN

VID3

OCSET

VID4

ISENO

VID5

ISEN-

VID6

ISEN+

PHASE

UGATE

BOOT

LGATE

PVCC

VCC

PWM

SOFT-START

AND

FAULT LOGIC

GATE

CONTROL

LOGIC

SHOOT-

THROUGH

PROTECTION

PVCC

BOOT

UGATE

20kΩ

PHASE

10kΩ

LGATE

FN6455.2

October 8, 2009

Page 3

Block Diagram

ISL6314ISL6314

ISEN-

ISEN+

RGND

VSEN

VDIFF

ISEN AMP

FSD

OPEN SENSE LINE DETECT

UNDERVOLTAGE

DETECTION

LOGIC

OVERVOLTAGE

DETECTION

LOGIC

FS/DROOP

SELECT

FSD

OCSET PGOODISENO

100µA

SOFT-START

AND

FAULT LOGIC

POWER-ON

RESET

0.85V

VCC

PVCC

BOOT

VID7 VID6

VID5 VID4 VID3 VID2 VID1 VID0

DVC

REF

COMP

APA

OFS

MODE/DAC

SELECT

DYNAMIC

VID

D/A

OFFSET

2kΩ

E/A

100µA

CLOCK AND MODULATOR WAVEFORM GENERAT OR

ADAPTIVE PHASE

ALLIGNMENT

CIRCUITRY

PWM

MOSFET

DRIVER

UGATE

PHASE

LGATE

GND

FN6455.2

October 8, 2009

Page 4

Typical Application - ISL6314

ISL6314ISL6314

+5V

COMP

APA

VCC

OFS FS REF

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

VSEN RGND

VDIFFDVC

ISL6314

PVCC

BOOT

UGATE

PHASE

LGATE

Typical Applications

1. PVCC = 12V; VIN =12V;

2. PVCC = 5V; VIN = 19V;

other combinations are also possible

PVCC

VIN

LOAD

PGOOD

OCSET ISEN-ISENOISEN+

OCSET

COMP

GND

FN6455.2

October 8, 2009

Page 5

Typical Application - ISL6314 with NTC Thermal Compensation

ISL6314ISL6314

+5V

COMP

APA

VCC

OFS FS REF

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

VDIFFDVC

ISL6314

VSEN RGND

PVCC

BOOT

UGATE

PHASE

LGATE

+12V

PLACE IN CLOSE

PROXIMITY

NTC

LOAD

PGOOD

OCSET ISEN-ISENOISEN+

OCSET

COMP

GND

FN6455.2

October 8, 2009

Page 6

ISL6314ISL6314

Absolute Maximum Ratings

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V

Absolute Boot Voltage, V Phase Voltage, V

GND - 8V (<400ns, 20µJ) to 30V (<200ns, V

PHASE

Upper Gate Voltage, V

- 3.5V (<100ns Pulse Width, 2µJ) to V

Lower Gate Voltage, V

PHASE

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V

Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V

. . . . . . . .GND - 0.3V to GND + 36V

BOOT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . .V

UGATE

LGATE

PHASE

. . . . . . . . GND - 0.3V to PVCC + 0.3V

BOOT-PHASE

- 0.3V to V

BOOT BOOT

+ 0.3V + 0.3V

= 5V)

Thermal Information

Thermal Resistance θJA (°C/W) θJC (°C/W)

QFN Package (Notes 1, 2). . . . . . . . . . 32 3.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .+5V to 12V ±5%

Ambient Temperature

ISL6314CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL6314IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

Tech Brief TB379.

2. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

BIAS SUPPLIES

Input Bias Supply Current I

Gate Drive Bias Current - PVCC Pin I

POR (Power-On Reset) Threshold VCC rising 4.25 4.38 4.50 V

PVCC POR (Power-On Reset) Threshold PVCC rising 4.25 4.38 4.50 V

PWM MODULATOR

Oscillator Frequency Accuracy, f (ISL6314CRZ)

Oscillator Frequency Accuracy, f (ISL6314IRZ)

Adjustment Range of Switching Frequency (Note 3) 0.08 - 1.0 MHz Oscillator Ramp Amplitude, V

P-P

CONTROL THRESHOLDS

EN Rising Threshold 0.84 0.86 0.88 V EN Hysteresis -110-mV

REFERENCE AND DAC

System Accuracy (1.000V to 1.600V) -0.5 - 0.5 % System Accuracy (0.600V to 1.000V) -1.0 - 1.0 % System Accuracy (0.375V to 0.600V) -2.0 - 2.0 % VIDx Input Low Voltage (INTEL) Pins VID0 to VID7 - - 0.4 V

; VCC = 5V; EN = high,

VCC

not switching;

; PVCC = 12V; EN = high,

PVCC

high, not switching

falling 3.75 3.88 4.00 V

911.416mA

124mA

PVCC falling 3.75 3.88 4.00 V

= 100kΩ (± 0.1%) 225 250 275 kHz

= 100kΩ (± 0.1%) 215 250 280 kHz

(Note 3) - 1.50 - V

FN6455.2

October 8, 2009

Page 7

ISL6314ISL6314

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VIDx Input High Voltage (INTEL) Pins VID0 to VID7 0.8 - - V VIDx Input Low Voltage (AMD) Pins VID0 to VID7 - - 0.8 V VIDx Input High Voltage (AMD) Pins VID0 to VID7 1.4 - - V VIDx Pull-Up Current (INTEL) Pins VID0 to VID7; VIDx = 0V - -40 - µA VIDx Pull-Down Current (AMD) Pins VID0 to VID7; VIDx = 0.5V - 20 - µA

PIN-ADJUSTABLE OFFSET

OFS Sink Current Accuracy (Negative Offset) R

OFS Source Current Accuracy (Positive Offset)

ERROR AMPLIFIER

DC Gain R Gain-Bandwidth Product CL = 100pF, RL = 10k to

Slew Rate C

Maximum Output Voltage Load = 1mA 3.90 4.20 - V Minimum Output Voltage Load = -1mA - 1.20 1.4 V

SOFT-START RAMP

Soft-Start Ramp Rate VR11, R

Adjustment Range of Soft-Start Ramp Rate (Note 3)

OVERCURRENT PROTECTION

OCSET Trip Current (ISL6314CRZ) 94 100 106 µA OCSET Trip Current (ISL6314IRZ) 93 100 107 µA OCSET Accuracy OCSET and ISUM Difference -5 0 5 mV ISENO Offset -1.7 0 1.7 mV

PROTECTION

Undervoltage Threshold VSEN falling VDAC - 325 VDAC - 350mV VDAC - 375 V Undervoltage Hysteresis VSEN rising - 100 - mV Overvoltage Threshold During Soft-Start VR11 and AMD 1.24 1.27 1.30 V Overvoltage Threshold (Default) VR11, VSEN rising VDAC + 150mV VDAC + 175mV VDAC + 200mV V

Overvoltage Hysteresis VSEN falling - 100 - mV PGOOD Output Sink Current PGOOD = 0.4V - 7.5 - mA

OVER-TEMPERATURE SHUTDOWN (Note 3)

Thermal Shutdown Setpoint - 160 - °C Thermal Recovery Setpoint - 100 - °C

= 32.4kΩ from OFS to

OFS

VCC

= 6.04kΩ from OFS to

OFS

GND

= 10k to ground, (Note 3) - 96 - dB

47.0 49.4 53.0 µA

47.0 49.7 53.0 µA

-40-MHz

ground, (Note 3)

= 100pF, load = ±400µA,

-20-V/µs

(Note 3)

= 100kΩ - 1.25 - mV/µs

AMD, R

= 100kΩ - 1.25 - mV/µs

0.156 - 6.25 mV/µs

AMD, VSEN rising VDAC + 200mV VDAC + 225mV VDAC + 250mV V

FN6455.2

October 8, 2009

Page 8

ISL6314ISL6314

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SWITCHING TIME (Note 3)

UGATE Rise Time t

RUGATE; VPVCC

load, 10% to 90%

LGATE Rise Time t

UGATE Fall Time t

LGATE Fall Time t

RLGATE; VPVCC

load, 10% to 90%

FUGATE; VPVCC

load, 90% to 10%

FLGATE; VPVCC

load, 90% to 10%

UGATE Turn-On Non-Overlap t

LGATE Turn-On Non-Overlap t

PDHUGATE

load, adaptive

PDHLGATE

load, adaptive

GATE DRIVE RESISTANCE (Note 3)

Upper Drive Source Resistance V

Upper Drive Sink Resistance V

Lower Drive Source Resistance V

Lower Drive Sink Resistance V

= 12V, 15mA source

PVCC

current

= 12V, 15mA sink

PVCC

current

= 12V, 15mA source

PVCC

current

= 12V, 15mA sink

PVCC

current

NOTE:

3. Limits should be considered typical and are not production tested.

; V

PVCC

= 12V, 3nF

= 12V , 3nF

-26-ns

-18-ns

-12-ns

-10-ns

1.25 2.0 3.0 Ω

0.9 1.65 3.0 Ω

0.85 1.25 2.2 Ω

0.60 0.80 1.35 Ω

Timing Diagram

UGATE

LGATE

PDHUGATE

FLGATE

RUGATE

PDHLGATE

FUGATE

RLGATE

FN6455.2

October 8, 2009

Page 9

ISL6314ISL6314

Functional Pin Description

VCC (Pin 18)

VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1µF ceramic capacitor.

PVCC (Pin 19)

This pin is the power supply pin for the channel MOSFET drivers, and can be connected to any voltage from +5V to +12V depending on the desired MOSFET gate-drive level. Decouple this pin with a quality 1.0µF ceramic capacitor.

GND (Pin 33 = Metal Pad)

GND is the bias and reference ground for the IC, connected to the metal pad under the IC.

EN (Pin 17)

This pin is a threshold-sensitive (approxima tely 0.85V) enable input for the controller. Held low, this pin disables controller operation. Pulled high, the pin enables the controller for operation.

FS (Pin 3)

A resistor, RT, tied to this pin sets the channel switching frequency of the controller. Refer to Equation 42 for proper resistor calculation.

The FS pin also controls whether the droop voltage (as described under pins ISENO, ISEN-, ISEN+) is added to the differential remote-sense amplifier’s output (VDIFF). T ying the R

resistor to ground connects droop voltage, allowing the

converter to incorporate output voltage droop proportional to the output current. Tying the R the droop voltage.

VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7 (Pins 31, 30, 29, 28, 27, 26, 25, 32)

These are the inputs for the internal DAC that provide the reference voltage for output regulation. These pins respond to TTL logic thresholds. These pins are internally pulled high, to approximately 1.2V, by 40µA internal current sources for Intel modes of operation, and pulled low by 20µA internal current sources for AMD modes of operation. The internal pull-up current decreases to 0 as the VID voltage approaches the internal pull-up voltage. All VID pins are compat ible with external pull-up voltages not exceeding the IC’s bias voltage (VCC).

VSEN (Pin 12)

This pin senses the microprocessor’s CORE voltage. Connect this pin to the CORE voltage sense pin or point of the microprocessor.

RGND (Pin 11)

This pin senses the local ground voltage of the microprocessor. Conne ct this pin to the Ground sen se pin or point of the microprocessor.

resistor to VCC disconnects

FB and COMP (Pins 9, 7)

These pins are the internal error amplifier inverting input and output respectively. The FB pin, COMP pin, and the VDIFF pins are tied together through external R-C networks to compensate the regulator.

DVC (Pin 8)

A series resistor and capacitor can be connected from the DVC pin to the FB pin to compensate and smooth dynamic VID transitions.

OCSET (Pin 13)

This is the overcurrent set pin. Placing a resistor from OCSET pin to ISENO allows a 100µA current to flow out of this pin, producing a voltage reference. Internal circuitry compares the voltage at OCSET to the voltage at ISEN-, and if ISEN- ever exceeds OCSET, the overcurrent protection activates.

APA (Pin 6)

This is the Adaptive Phase Alignment set pin. A 100µA current flows out the APA pin and by tying a resistor from this pin to COMP the trip level for the Adaptive Phase Alignment circuitry can be set.

REF (Pin 4)

The REF input pin is the positive input of the error amplifier. It is internally connected to the DAC output through a 2kΩ resistor. A cap acitor is used between the REF pin and gro und to smooth the voltage transition during soft-start and Dynamic VID transitions. This pin can also be returned to RGND if desired.

NC (Pin 20)

This pin is presently NC (No Connect), but is reserved for a future function.

OFS (Pin 5)

The OFS pin provides a means to program a DC current for generating an offset voltage across the re sistor betwe en FB and VDIFF. The offset current is generated via an external resistor and precision internal voltage references. The polarity is selected by connecting the resistor to GND (for positive offset) or to VCC (for negative offset). For no offset, the OFS pin should be left unconnected.

UGA TE (Pin 23)

Connect this pin to the corresponding upper MOSFET gate. This pin is used to control the upper MOSFET and is monitored for shoot-through prevention purposes.

BOOT (Pin 22)

This pin provides the bias voltage for the upper MOSFET drive. Connect this pin to appropriately-chosen external bootstrap capacitors. Internal bootstrap diodes connected to the PVCC pin provides the necessary bootstrap charge.

FN6455.2

October 8, 2009

Page 10

ISL6314ISL6314

PHASE (Pin 24)

Connect this pin to the source of the upper MOSFET. This pin is the return path for the upper MOSFET drive.

LGATE (Pin 21)

This pin is used to control the lower MOSFET. Connect this pin to the lower MOSFET gate.

SS (Pin 2)

A resistor, RSS, placed from SS to VCC or GND will set the soft-start ramp slope. Refer to Equations 16 and 17 for proper resistor calculation.

The state of the SS pin also selects which of the available DAC tables will be used to decode the VID inputs and puts the controller into the corresponding mode of operation. For Intel VR1 1 mode of operation the R GND. AMD compliance is selected if the R

resistor should be tied to

resistor is tied to

VCC (once in AMD mode, the VID7 bit selects 5-bit DAC if set to a logic high, or 6-bit DAC if set to a logic low).

PGOOD (Pin 1)

For Intel mode of operation, PGOOD indicates whether VSEN is within specified overvoltage and undervolt age limit s after a fixed delay from the end of soft-start. If VSEN exceeds these limits, or if an overcurrent event occurs, or if the part is disabled, PGOOD is pulled low. PGOOD is always low prior to the end of soft-start.

For AMD modes of operation, PGOOD will always be high as long as VSEN is within the specified undervoltage/overvolta ge window and soft-start has ended. PGOOD only goes low if VSEN is outside this window .

ISENO, ISEN-, and ISEN+ (Pins 14, 15, 16)

ISEN-, ISEN+, and ISENO are the DCR current sense amplifier’s negative input, positive input, and output respectively . For accu rate D CR current sensing , connect a resistor from the phase node to ISEN- and connect ISEN+ to the output inductor, roughl y VOUT. A parallel R-C feedback circuit connected between ISEN- and ISENO will then create a voltage from ISEN+ to ISENO proportional to the voltage drop across the inductor DCR. This voltage is referred to as the droop voltage and is added to the differential remote-sense amplifier’s output.

An optional 0.001µF to 0.01µF ceramic capacitor can be placed from the ISEN+ pin to the ISEN- pin to help reduce common mode noise that might be introduced by the layout.

VDIFF (Pin 10)

VDIFF is the output of the differential remote-sense amplifier. The voltage on this pin is equal to the difference between VSEN and RGND (VOUT) added to the difference between ISEN+ and ISENO (droop). VDIFF therefore represents the VOUT voltage plus the droop voltage. The state of the FS pin determines whether the droop voltage is added or not.

Operation

Power Conversion

The ISL6314 controller helps simplify implementation by integrating vital functions and requiring minimal external components. The “Block Diagram” on page 3 provides a top level view of the single-phase power conversion using the ISL6314 controller.

IL, 7A/DIV

PWM, 5V/DIV

1µs/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WA VEFORMS

FOR 1-PHASE CONVERTER

Output Ripple

Figure 1 illustrates the output ripple. The PWM current forms the AC ripple current and the DC load current. The peak-to-peak current about 7A, and the DC components of the inductor current feeds the load.

To und erstand the rippl e current amplitude, examine Equation 1 representing a single channel peak-to-peak inductor current.

VINV

----------------------------------------------------------=

–()V

P-P

In Equation 1, V voltages respectively, L is the single-channel inductor value, and f

is the switching frequency.

The output capacitors conduct the ripple component of the inductor current. Output voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. Equation 2 shows the approximation for the output voltage ripple.

P-PIP-P

OUT

ESR⋅=

V⋅IN⋅

and V

⋅

OUT

are the input and output

OUT

(EQ. 1)

(EQ. 2)

Adaptive Phase Alignment (APA)

To improve the transient response, the ISL6314 implements Intersil’s proprietary Adaptive Phase Alignment (APA) technique, which turns on the channel during large current step transient events.

FN6455.2

October 8, 2009

Page 11

EXTERNAL CIRCUIT

APA

APA,TRIP

COMP

ISL6314 INTERNAL CIRCUIT

100µA

LOW

PASS

FILTER

ERROR

AMPLIFIER

APA

CIRCUITRY

TO APA

ISL6314ISL6314

The PWM output state is driven by the position of the error amplifier output signal, V the beginning of each PWM time interval, this V

, as illustrated in Figure 3. At

COMP

signal is compared to the internal modulator waveform. As long as the V

voltage is lower then the modulator waveform

COMP

voltage, the PWM signal is commanded low. The internal MOSFET driver detects the low state of the PWM signal and turns off the upper MOSFET and turns on the lower synchronous MOSFET. When the V

voltage crosses

COMP

the modulator ramp, the PWM output transitions high, turning off the synchronous MOSFET and turning on the upper MOSFET. The PWM signal will remain high until the V

voltage crosses the modulator ramp again. When

COMP

this occurs, the PWM signal will transition low again.

FIGURE 2. ADAPTIVE PHASE ALIGNMENT DETECTION

As Figure 2 shows, the APA circuitry works by monitoring the voltage on the APA pin and comparing it to a filtered copy of the voltage on the COMP pin. The voltage on the APA pin is a copy of the COMP pin voltage that has been negatively offset. If the APA pin exceeds the filtered COMP pin voltage an APA event occurs and the channel is forced on.

The APA trip level is the amount of DC offset between the COMP pin and the APA pin. This is the voltage excursion that the APA and COMP pin must have during a transient event to activate the Adaptive Phase Alig nment circuitry. This APA trip level is set through a resistor, R

APA

, that connects from the APA pin to the COMP pin. A 100µA current flows across R

into the APA pin to set the APA

APA

trip level as described in Equation 3. An APA trip level of 500mV is recommended for most applications. A 1000pF capacitor , C

, should also be placed across the R

APA

resistor to help with noise immunity.

APA TRIP,

APA

100 106–×⋅=

(EQ. 3)

Active Pulse Positioning (APP) Modulated PWM Operation

The ISL6314 uses a proprietary Active Pulse Positioning (APP) modulation scheme to control the internal PWM signals that command each channel’s driver to turn their upper and lower MOSFETs on and off. The time interval in which a PWM signal can occur is generated by an internal clock, whose cycle time is the inverse of the switching frequency set by the resistor connected to the FS pin. The advantage of Intersil’s proprietary Active Pulse Positioning (APP) modulator is that the PWM signal has the ability to turn on at any point during this PWM time interval, and turn off immediately after the PWM signal has transitioned high. This is important because is allows the controller to quickly respond to output voltage drops associated with current load spikes, while avoiding the ring back affects associated with other modulation schemes.

During each PWM time interval, the PWM signal can only transition high once. Once PWM transitions high, it can not transition high again until the beginning of the next PWM time interval. This prevents the occurrence of double PWM pulses occurring during a single period.

COMP

MODULATOR

RAMP

WAVEFORM

FIGURE 3. CHANNEL PWM FUNCTION

PWM

TO GATE

CONTROL

LOGIC

Output Voltage Setting

The ISL6314 uses a digital to analog converter (DAC) to generate a reference voltage based on the logic signals at the VID pins. The DAC decodes the logic signals into one of the discrete voltages shown in Tables 2, 3 or 4. In the Intel VR11 mode of operation, each VID pin is pulled up to an internal 1.2V voltage by a weak current source (40µA), which decreases to 0A as the voltage at the VID pin varies from 0 to the internal 1.2V pull-up voltage. In AMD modes of operation, the VID pins are pulled low by a weak 20µA current source. External pull-up resistors or active-high output stages can augment the pull-up current sources, up to a voltage of 5V.

The ISL6314 accommodates three different DAC ranges: Intel VR11, AMD K8/K9 5-bit, and AMD 6-bit. The state of the SS and VID7 pins decide which DAC version is active. Refer to T able 1 for a description of how to select the desired DAC version.

FN6455.2

October 8, 2009

Page 12

ISL6314ISL6314

TABLE 1. ISL6314 DAC SELECT AND FUNCTION TABLE

DAC VERSION SS PIN VID7 PIN

INTEL VR11 R

resistor tied to

GND

AMD 5-BIT R

AMD 6-BIT R

TIE RESISTOR to

VCC

: AMD Tables - RSS: Intel Table

: Negative No Offset R

OFS

: No Droop - RT: Droop

resistor tied to

VCC

resistor tied to

VCC

OPEN TIE RESISTOR to

GND

OFS

high

low

: Positive

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

00000000OFF 00000001OFF

000000101.60000

000000111.59375

000001001.58750

000001011.58125

000001101.57500

000001111.56875

000010001.56250

000010011.55625

000010101.55000

000010111.54375

000011001.53750

000011011.53125

000011101.52500

000011111.51875

000100001.51250

000100011.50625

000100101.50000

000100111.49375

000101001.48750

000101011.48125

000101101.47500

000101111.46875

000110001.46250

000110011.45625

000110101.45000

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

000110111.44375

000111001.43750

000111011.43125

000111101.42500

000111111.41875

001000001.41250

001000011.40625

001000101.40000

001000111.39375

001001001.38750

001001011.38125

001001101.37500

001001111.36875

001010001.36250

001010011.35625

001010101.35000

001010111.34375

001011001.33750

001011011.33125

001011101.32500

001011111.31875

001100001.31250

001100011.30625

001100101.30000

001100111.29375

001101001.28750

001101011.28125

001101101.27500

001101111.26875

001110001.26250

001110011.25625

001110101.25000

001110111.24375

001111001.23750

001111011.23125

001111101.22500

001111111.21875

010000001.21250

010000011.20625

010000101.20000

FN6455.2

October 8, 2009

Page 13

ISL6314

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

010000111.19375

010001001.18750

010001011.18125

010001101.17500

010001111.16875

010010001.16250

010010011.15625

010010101.15000

010010111.14375

010011001.13750

010011011.13125

010011101.12500

010011111.11875

010100001.11250

010100011.10625

010100101.10000

010100111.09375

010101001.08750

010101011.08125

010101101.07500

010101111.06875

010110001.06250

010110011.05625

010110101.05000

010110111.04375

010111001.03750

010111011.03125

010111101.02500

010111111.01875

011000001.01250

011000011.00625

011000101.00000

011000110.99375

011001000.98750

011001010.98125

011001100.97500

011001110.96875

011010000.96250

011010010.95625

011010100.95000

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

011010110.94375

011011000.93750

011011010.93125

011011100.92500

011011110.91875

011100000.91250

011100010.90625

011100100.90000

011100110.89375

011101000.88750

011101010.88125

011101100.87500

011101110.86875

011110000.86250

011110010.85625

011110100.85000

011110110.84375

011111000.83750

011111010.83125

011111100.82500

011111110.81875

100000000.81250

100000010.80625

100000100.80000

100000110.79375

100001000.78750

100001010.78125

100001100.77500

100001110.76875

100010000.76250

100010010.75625

100010100.75000

100010110.74375

100011000.73750

100011010.73125

100011100.72500

100011110.71875

100100000.71250

100100010.70625

100100100.70000

FN6455.2

October 8, 2009

Page 14

ISL6314

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

100100110.69375

100101000.68750

100101010.68125

100101100.67500

100101110.66875

100110000.66250

100110010.65625

100110100.65000

100110110.64375

100111000.63750

100111010.63125

100111100.62500

100111110.61875

101000000.61250

101000010.60625

101000100.60000

101000110.59375

101001000.58750

101001010.58125

101001100.57500

101001110.56875

101010000.56250

101010010.55625

101010100.55000

101010110.54375

101011000.53750

101011010.53125

101011100.52500

101011110.51875

101100000.51250

101100010.50625

101100100.50000 11111110OFF 11111111OFF

TABLE 3. AMD 5-BIT VOLTAGE IDENTIFICATION

CODES

VID4 VID3 VID2 VID1 VID0 VDAC

11111Off

111100.800

111010.825

TABLE 3. AMD 5-BIT VOLTAGE IDENTIFICATION

CODES (Continued)

VID4 VID3 VID2 VID1 VID0 VDAC

111000.850

110110.875

110100.900

110010.925

110000.950

101110.975

101101.000

101011.025

101001.050

100111.075

100101.100

100011.125

100001.150

011111.175

011101.200

011011.225

011001.250

010111.275

010101.300

010011.325

010001.350

001111.375

001101.400

001011.425

001001.450

000111.475

000101.500

000011.525

000001.550

TABLE 4. AMD 6-BIT VOLTAGE IDENTIFICATION

CODES

VID5 VID4 VID3 VID2 VID1 VID0 VDAC

0 0 0 0 0 0 1.5500 0 0 0 0 0 1 1.5250 0 0 0 0 1 0 1.5000 0 0 0 0 1 1 1.4750 0 0 0 1 0 0 1.4500 0 0 0 1 0 1 1.4250 0 0 0 1 1 0 1.4000

FN6455.2

October 8, 2009

Page 15

ISL6314

TABLE 4. AMD 6-BIT VOLTAGE IDENTIFICATION

CODES (Continued)

VID5 VID4 VID3 VID2 VID1 VID0 VDAC

0 0 0 1 1 1 1.3750 0 0 1 0 0 0 1.3500 0 0 1 0 0 1 1.3250 0 0 1 0 1 0 1.3000 0 0 1 0 1 1 1.2750 0 0 1 1 0 0 1.2500 0 0 1 1 0 1 1.2250 0 0 1 1 1 0 1.2000 0 0 1 1 1 1 1.1750 0 1 0 0 0 0 1.1500 0 1 0 0 0 1 1.1250 0 1 0 0 1 0 1.1000 0 1 0 0 1 1 1.0750 0 1 0 1 0 0 1.0500 0 1 0 1 0 1 1.0250 0 1 0 1 1 0 1.0000 0 1 0 1 1 1 0.9750 0 1 1 0 0 0 0.9500 0 1 1 0 0 1 0.9250 0 1 1 0 1 0 0.9000 0 1 1 0 1 1 0.8750 0 1 1 1 0 0 0.8500 0 1 1 1 0 1 0.8250 0 1 1 1 1 0 0.8000 0 1 1 1 1 1 0.7750 1 0 0 0 0 0 0.7625 1 0 0 0 0 1 0.7500 1 0 0 0 1 0 0.7375 1 0 0 0 1 1 0.7250 1 0 0 1 0 0 0.7125 1 0 0 1 0 1 0.7000 1 0 0 1 1 0 0.6875 1 0 0 1 1 1 0.6750 1 0 1 0 0 0 0.6625 1 0 1 0 0 1 0.6500 1 0 1 0 1 0 0.6375 1 0 1 0 1 1 0.6250 1 0 1 1 0 0 0.6125 1 0 1 1 0 1 0.6000

TABLE 4. AMD 6-BIT VOLTAGE IDENTIFICATION

VID5 VID4 VID3 VID2 VID1 VID0 VDAC

1 0 1 1 1 0 0.5875 1 0 1 1 1 1 0.5750 1 1 0 0 0 0 0.5625 1 1 0 0 0 1 0.5500 1 1 0 0 1 0 0.5375 1 1 0 0 1 1 0.5250 1 1 0 1 0 0 0.5125 1 1 0 1 0 1 0.5000 1 1 0 1 1 0 0.4875 1 1 0 1 1 1 0.4750 1 1 1 0 0 0 0.4625 1 1 1 0 0 1 0.4500 1 1 1 0 1 0 0.4375 1 1 1 0 1 1 0.4250 1 1 1 1 0 0 0.4125 1 1 1 1 0 1 0.4000 1 1 1 1 1 0 0.3875 1 1 1 1 1 1 0.3750

CODES (Continued)

Voltage Regulation

In order to regulate the output voltage to a specified level, the ISL6314 uses the integrating compensation network shown in Figure 4. This compensation network insures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6314 to include the combined tolerances of each of these elements.

The ISL6314 incorporates an internal differential remote-sense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point, resulting in a more accurate means of sensing output voltage. Connect the microprocessor sense pins to the non-inverting input, VSEN, and inverting input, RGND, of the remote-sense amplifier. The droop voltage, V feeds into the remote-sense amplifier. The remote-sense output, V voltage, V

, is therefore equal to the sum of the output

DIFF

, and the droop voltage. V

OUT

is connected to

DIFF

the inverting input of the error amplifier through an external resistor.

OUTVREFVOFS

– V

–=

DROOP

, also

(EQ. 4)

FN6455.2

October 8, 2009

Page 16

ISL6314

The output of the error amplifier, V

, is compared to the

COMP

sawtooth waveform to generate the PWM signal. The PWM signal controls the timing of the Internal MOSFET drivers and regulates the converter output so that the voltage at FB is equal to the voltage at REF. This will regulate the output voltage to be equal to Equation 4. The internal and external circuitry that controls voltage regulation is illustrated in Figure 4.

EXTERNAL CIRCUIT ISL6314 INTERNAL CIRCUIT

COMP

VID DAC

REF

OFS

OUT

DROOP

VDIFF

VSEN

RGND

ISEN+

ISENO

ERROR AMPLIFIER

OFS

+ +

DIFFERENTIAL REMOTE-SENSE AMPLIFIER

COMP

FIGURE 4. OUTPUT VOLTAGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

Load-Line (Droop) Regulation

Some microprocessor manufacturers require a precisely-controlled output resistance. This dependence of output voltage on load current is often termed “droop” or “load line” regulation. By adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers.

In other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results from fast load-current demand changes.

The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit.

PHASE

ISEN-

ISENO

COMP

INDUCTOR I

COMP

VL(s)

DCR

OUT

DROOP

ISL6314

ISEN+

(OPTIONAL)

FIGURE 5. DCR SENSING CONFIGURATION

As shown in Figure 5, a voltage, V current in the channel, I

, feeds into the differential

OUT

, proportional to the

DROOP

remote-sense amplifier. The resulting voltage at the output of the remote-sense amplifier is the sum of the output voltage and the droop voltage. Equation 5 shows that feeding this voltage into the compensation network causes the regulator to adjust the output voltage so that it’s equal to the reference voltage minus the droop voltage.

The droop voltage, V

, is created by sensing the

DROOP

current through the output inductors. This is accomplished by using a continuous DCR current sensing method.

Inductor windings have a characteristic distributed resistance or DCR (Direct Current Resistance). For simplicity, the inductor DCR is considered as a separate lumped quantity, as shown in Figure 5. The channel current, I

, flowing through the inductor, passes through the DCR.

Equation 5 shows the S-domain equivalent voltage, V

across the inductor.

s() ILsL DCR+⋅()⋅=

(EQ. 5)

The inductor DCR is important because the voltage dropped across it is proportional to the channel current. By using a simple R-C network and a current sense amplifier, as shown in Figure 5, the voltage drop across the inductor’s DCR can be extracted. The output of the current sense amplifier, V current I

, can be shown to be proportional to the channel

DROOP

, shown in Equation 6.

sL⋅

⎛⎞

-------------

⎝⎠

DCR

--------------------------------- ---------------------------------------- -

s()

⋅⋅ 1+()

COMPCCOMP

COMP

-----------------------

IL()DCR⋅⋅⋅=

(EQ. 6)

If the R-C network components are selected such that the R-C time constant matches the inductor L/DCR time constant, then V

is equal to the voltage drop across

DROOP

the DCR, multiplied by a gain. As Equation 7 shows, V I

OUT

is therefore proportional to the total output current,

DROOP

FN6455.2

October 8, 2009

Page 17

ISL6314

DROOP

COMP

---------------------

OUT

DCR⋅⋅=

(EQ. 7)

By simply adjusting the value of RS, the load line can be set to any level, giving the converter the right amount of droop at all load currents. It may also be necessary to compensate for any changes in DCR due to temperature. These changes cause the load line to be skewed, and cause the R-C time constant to not match the L/DCR time constant. If this becomes a problem a simple negative temperature coefficient resistor network can be used in the place of R

to compensate for the rise in DCR due to

COMP

temperature. Note: An optional 10nF ceramic capacitor from the ISEN+

pin to the ISEN- pin is recommended to help reduce any noise affects on the current sense amplifier due to layout

Output-Voltage Offset Programming

The ISL6314 allows the designer to accurately adjust the offset voltage by connecting a resistor, R pin to VCC or GND. When R

is connected between OFS

OFS

and VCC, the voltage across it is regulated to 1.6V. This causes a proportional current (I

) to flow into the OFS pin

OFS

and out of the FB pin, providing a negative offset. If R connected to ground, the voltage across it is regulated to

0.3V, and I

flows into the FB pin and out of the OFS pin,

OFS

providing a positive offset. The offset current flowing through the resistor between VDIFF and FB will generate the desired offset voltage which is equal to the product (I These functions are shown in Figures 6 and 7.

Once the desired output offset voltage has been determined, use the following formulas in Equations 8 and 9 to set R

For Negative Offset (connect R

1.6 RFB⋅

OFS

--------------------------

OFFSET

For Positive Offset (connect R

0.3 RFB⋅

--------------------------

OFS

OFFSET

OFS

to VCC):

to GND):

, from the OFS

OFS

x RFB).

OFS

(EQ. 8)

(EQ. 9)R

VDIFF

OFS

GND

ISL6314

VREF

E/A

GND

1.6V

0.3V

VCC

FIGURE 6. POSITIVE OFFSET OUTPUT VOLT AGE

PROGRAMMING

VDIFF

OFS

VREF

E/A

VCC

1.6V

OFS

GND

0.3V

OFS

ISL6314

FIGURE 7. NEGATIVE OFFSET OUTPUT VOL T AG E

PROGRAMMING

FN6455.2

October 8, 2009

Page 18

ISL6314

Dynamic VID

Modern microprocessors need to make changes to their core voltage as part of normal operation. They direct the ISL6314 to do this by making changes to the VID inputs. The ISL6314 is required to monitor the DAC inputs and respond to on-the-fly VID changes in a controlled manner, supervising a safe output voltage transition without discontinuity or disruption. The DAC mode, ISL6314 is operating in, determines how the controller responds to a dynamic VID change.

INTEL DYNAMIC VID TRANSITIONS

When in Intel VR11 mode the ISL6314 checks the VID inputs on the positive edge of an internal 5.5MHz clock. If a new code is established and it remains stable for three consecutive readings (0.36µs to 0.54µs), the ISL6314 recognizes the new code and changes the internal DAC reference directly to the new level. The Intel processor controls the VID transitions and is responsible for incrementing or decrementing one VID step at a time. In VR1 1 mode, the ISL6314 will immediately change the internal DAC reference to the new requested value as soon as the request is validated, which means the fastest recommended rate at which a bit change can occur is once every 1µs. If the VID code is changed by more then one step at a time, the DAC will try to track it at a 5.5MHz step rate. This will likely cause an overcurrent or overvoltage fault.

AMD DYNAMIC VID TRANSITIONS

When running in AMD 5-bit or 6-bit modes of operation, the ISL6314 responds differently to a dynamic VID change. In the AMD modes the ISL6314 still checks the VID inputs on the positive edge of an internal 5.5MHz clock. In these mo de s t he VID code can be changed by more than a 1-bit step at a time. If a new code is established and it remains stable for three consecutive readings (0.36µs to 0.54µs), the ISL6314 recognizes the change and begin s s l e w i n g t h e DAC in

6.25mV steps at a stepping frequency of 345kHz until the VID and DAC are equal. Thus, the total time required for a VID change, t (ΔV

VID

The time required for a ISL6314-based converter in AMD 5-bit DAC configuration to make a 1.1V to 1.5V reference voltage change is about 186µs, as calculated using Equation 10.

DVID

VID “OFF” DAC CODES

Both the Intel VR1 1 and the AMD 5-bit VID t ables include “Of f” DAC codes, which indicate to the controller to disable all regulation. Recognition of these codes is slightly different in that they mus t b e st a ble for four consecutive readings of a 5.5MHz clock (0.54µs to 0.72µs) to be recognized. Once an “Of f” code is recognized the ISL6314 latches off, and must be reset by dropping the EN pin.

, is dependent only on the size of the VID change

DVID

------------------------- -

345 10

VID

⎛⎞

---------------------

⋅=

⎝⎠

0.00625

(EQ. 10)

Compensating Dynamic VID Transitions

During a VID transition, the resulting change in voltage on the FB pin and the COMP pin causes an AC current to flow through the error amplifier compensation components from the FB to the COMP pin. This current then flows through the feedback resistor, R overshoot or undershoot at the end of the VID transition. In order to ensure the smooth transition of the output voltage during a VID change, a VID-on-the-fly compensation network is required. This network is composed of a resistor and capacitor in series, R and the FB pin, as shown in Figure 8.

VDIFF

DVC

REF

VDAC+RGND

FIGURE 8. VID-ON-THE-FLY COMPENSATION NETWORK

This VID-on-the-fly compensation network works by sourcing AC current into the FB node to offset the effects of the AC current flowing from the FB to the COMP pin during a VID transition. To create this compensation current the ISL6314 sets the voltage on the DVC pin to be 2x the voltage on the REF pin. Since the error amplifier forces the voltage on the FB pin and the REF pin to be equal, the resulting voltage across the series RC between DVC and FB is equal to the REF pin voltage. The RC compensation components, R

and C

DVC

amount of compensation current. The amount of compensation current required is dependant

on the modulator gain of the system, K1, and the error amplifier R-C components, R between the FB and COMP pins. Use Equations 11, 12, and 13 to calculate the RC component values, R for the VID-on-the-fly compensation network. For these equations: V

is the input voltage for the power train; V

is the oscillator ramp amplitude (1.5V); and R the error amplifier R-C components between the FB and COMP pins.

-----------

, and can cause the output voltage to

DVC

and C

DVC

ISL6314 INTERNAL CIRCUIT

, between the DVC

DVC

= I

ERROR

AMPLIFIER

COMP

, can then be selected to create the desired

and CC, that are in series

and C

DVC

and CC are

---------------- -

K1 1–

DVC

P-P

(EQ. 11)

FN6455.2

October 8, 2009

Page 19

ISL6314

DVC

------- -

×=

(EQ. 12)

(EQ. 13)

Advanced Adaptive Zero Shoot-Through Deadtime Control (Patent Pending)

The integrated drivers incorporate a unique adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower MOSFET body-diode conduction, and to prevent the upper and lower MOSFETs from conducting simultaneously. This is accomplished by ensuring either rising gate turns on its MOSFET with minimum and sufficient delay after the other has turned off.

During turn-off of the lower MOSFET, the PHASE voltage is monitored until it reaches a -0.3V/+0.8V (forward/reverse inductor current). At this time the UGA TE is released to rise. An auto-zero comparator is used to correct the r phase voltage preventing false detection of the -0.3V phase level during r

DS(ON)

conduction period. In the case of zero current, the UGA TE is released after 35ns delay of the LGATE dropping below 0.5V. When LGATE first begins to transition low, this quick transition can disturb the PHASE node and cause a false trip, so there is 20ns of blanking time once LGA TE falls until PHASE is monitored.

DS(ON)

drop in the

1.6

1.4

1.2

1.0

(µF)

0.8

0.6

BOOT_CAP

0.4

0.2 20nC

0.0

FIGURE 9. BOOTSTRAP CAPACIT ANCE vs BOOT RIPPLE

50nC

VOLTAGE

= 100nC

GATE

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0 ΔV

BOOT_CAP

(V)

The bootstrap capacitor must have a maximum voltage rating above PVCC + 4V and its capacitance value can be chosen from Equation 14: where Q charge per upper MOSFET at V N

is the number of control MOSFETs. The ΔV

is the amount of gate

gate-source voltage and

GS1

BOOT_CAP

term is defined as the allowable droop in the rail of the upper gate drive. Typical curves are shown in Figure 9.

GATE

BOOT_CAP

--------------------------------------

≥

ΔV

BOOT_CAP

(EQ. 14)

Once the PHASE is high, the advanced adaptive shoot-through circuitry monitors the PHASE and UGATE voltages during a PWM falling edge and the subsequent UGATE turn-off. If either the UGATE falls to less than 1.75V above the PHASE or the PHASE falls to less than +0.8V , the LGATE is released to turn-on.

Internal Bootstrap Device

The integrated driver features an internal bootstrap schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the PHASE node. This reduces voltage stress on the boot to phase pins.

GATE

----------------------------------

GS1

⋅=

QG1PVCC⋅

Gate Drive Voltage Versatility

The ISL6314 provides the user flexibility in choosing the gate drive voltage for efficiency optimization. The controller ties the upper and lower drive rails together. Simply applying a voltage from 5V up to 12V on PVCC sets both gate drive rail voltages simultaneously.

Initialization

Prior to initialization, proper conditions must exist on the EN, VCC, PVCC and the VID pins. When the conditions are met, the controller begins soft-start. Once the output voltag e is within the proper window of operation, the controller asserts PGOOD.

FN6455.2

October 8, 2009

Page 20

ISL6314

ISL6314 INTERNAL CIRCUIT

POR

CIRCUIT

SOFT-START

AND

FAULT LOGIC

FIGURE 10. POWER SEQUENCING USING

THRESHOLD-SENSITIVE ENABLE (EN) FUNCTION

ENABLE COMPARATOR

0.85V

EXTERNAL CIRCUIT

VCC

PVCC

+12V

10.7kΩ

1.40kΩ

Enable and Disable

While in shutdown mode, the LGATE and UGATE signals are held low to assure the MOSFETs remain off. The following input conditions must be met, for both Intel and AMD modes of operation, before the ISL6314 is released from shutdown mode to begin the soft-start start-up sequence:

4. The VID code must not be 11 1 11 in AMD 5-bit mode. This code signals the controller that no load is present. The controller will not allow soft-start to begin if this VID code is present on the VID pins.

Once all of these conditions are met the controller will begin the soft-start sequence and will ramp the output voltage up to the user designated level.

Intel Soft-Start

The soft-start function allows the converter to bring up the output voltage in a controlled fashion, resulting in a linear ramp-up. The soft-start sequence for the Intel modes of operation is slightly different than the AMD soft-start sequence.

, 500mV/DIV

OUT

PGOOD

FIGURE 11. INTEL SOFT-START WAVEFORMS

500µs/DIV

td3t

1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the ISL6314 is guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6314 will not inadvertently turn off unless the bias voltage drops substantially (see “Electrical Specifications” on page 6).

2. The voltage on EN must be above 0.85V. The EN input allows for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6314 in shutdown until the voltage at EN rises above 0.85V . The enable comparator has 110mV of hysteresis to prevent bounce.

3. The driver bias voltage applied at the PVCC pin must reach the internal power-on reset (POR) rising threshold. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6314 will not inadvertently turn off unless the PVCC bias voltage drops substantially (see “Electrical Specifications” on page 6).

For Intel VR11 and AMD 6-bit modes of operation these are the only conditions that must be met for the controller to immediately begin the soft-start sequence, as shown in Figure 10. If running in AMD 5-bit mode of operation there is one more condition that must be met:

For the Intel VR11 mode of operation, the soft-start sequence is composed of four periods, as shown in Figure 1 1. Once the ISL6314 is released from shutdown and soft-start begins (as described in “Enable and Disable” on page 20), the controller will have fixed delay period t

, typically 1.1ms. After this delay period, the VR will begin first soft-start ramp until the output voltage reaches 1.1V VBOOT voltage. Then, the controller will regulate the VR voltage at

1.1V for another fixed period t t

period, ISL6314 will read the VID signals. It is

typically 93µs. At the end of

d3,

recommended that the VID codes be set no later then 50µs into period t

. If the VID code is valid, ISL6314 will initiate

the second soft-start ramp until the output voltage reaches the VID voltage plus/minus any offset or droop voltage.

The soft-start time is the sum of the 4 periods as shown in Equation 15.

SStd1td2td3td4

During t

+++=

and td4, ISL6314 digitally controls the DAC

(EQ. 15)

voltage change at 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor R second soft-start ramp time t

from SS pin to GND. The

and td4 can be calculated

based on Equations 16 and 17:

FN6455.2

October 8, 2009

Page 21

1.1 R⋅

d4VVID

8103–μs()⋅⋅=

1.1– RSS8103–μs()⋅⋅⋅=

(EQ. 16)

(EQ. 17)

For example, when VID is set to 1.5V and the RSS is set at 100kΩ, the first soft-st art ramp time t second soft-start ramp time t

will be 320µs.

will be 880µs and the

After the DAC voltage reaches the final VID setting, PGOOD will be set to high with the fixed delay t for t

is 93µs.

. The typical value

AMD Soft-Start

, 500mV/DIV

OUT

ISL6314

TABLE 5. ISL6314 SOFT_START TIMING SUMMARY

MODE TIME SLOT TIME

VR11 t VR11 t VR11 t VR11 t VR11 t

AMD t AMD t

d1 d2 d3 d4 d5 dA dB

Pre-Biased Soft-Start

OUTPUT PRECHARGED

ABOVE DAC LEVEL

OUTPUT PRECHARGED

BELOW DAC LEVEL

1.1ms

Equation 16

93µs

Equation 17

93µs

1.1ms

Equation 18

PGOOD

FIGURE 12. AMD SOFT-START WAVEFORMS

500µs/DIV

For the AMD 5-bit and 6-bit modes of operation, the soft-start sequence is composed of two periods, as shown in Figure 12. At the beginning of soft-start, the VID code is immediately obtained from the VID pins, followed by a fixed delay period t

of typically 1.1ms. After this delay period the

ISL6314 will begin ramping the output voltage to the desired DAC level at a fixed rate of 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor R

on the SS pin.

The amount of time required to ramp the output voltage to the final DAC voltage is referred to as t

, and can be

calculated as shown in Equation 18.

R⋅

dBVVID

8103–μs()⋅⋅=

(EQ. 18)

At the end of soft-start, PGOOD will immediately go high if the VSEN voltage is within the undervoltage and overvoltage limits.

Table 5 is a summary table of the typical soft-start timing for both modes. The times listed are fixed delays; the variable ones (defined by the equations) depend on the slope of the ramp (1.25 mV/µs for a nominal 100kΩ R

resistor), and

the amount of voltage excursion.

GND>

T2 T3

FIGURE 13. SOFT-ST ART W A VEFORMS FOR ISL6314-BASED

CONVERTER

(0.5V/DIV)

OUT

EN (5V/DIV)

The ISL6314 also has the ability to start up into a pre-charged output, without causing any unnecessary disturbance. The FB pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both MOSFETs off. Once the internal ramping reference exceeds the FB pin potential, the output drives are enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the DAC setting. Should the output be pre-charged to a level exceeding the DAC setting, the output drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage down to the DAC-set level. See Figure 13.

Fault Monitoring and Protection

The ISL6314 actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common power good indicator is provided for linking to external system monitors. The schematic in Figure 14 outlines the interaction between the fault monitors and the power-good signal.

FN6455.2

October 8, 2009

Page 22

ISL6314

ISENO

ISEN+

OCSET

ISEN-

VDIFF

+1V

VID + OFFSET mV

OVP

ISEN

DROOP

SOFT-START, FAULT

AND CONTROL LOGIC

100µA

VSEN

RGND

PGOOD

VID - OFFSET mV

FIGURE 14. POWER-GOOD AND PROTECTION CIRCUITRY

ISL6314 INTERNAL CIRCUITRY

Power-Good Signal

The power-good pin (PGOOD) is an open-drain logic output that signals whether or not the ISL6314 is regulating the output voltage within the proper levels, and whether any fault conditions exist. This pin should be tied through a resistor to a voltage source that’s equal to or less than VCC.

For Intel mode of operation, PGOOD indicates whether VSEN is within specified overvoltage and undervolt age limit s after a fixed delay from the end of soft-start. PGOOD transitions low when an undervoltage, overvoltage, or overcurrent condition is detected or when the controller is disabled by a reset from EN, POR, or one of the no-CPU VID codes. In the event of an overvoltage or overcurrent condition, or a no-CPU VID code, the controller latches off and PGOOD will not return high until EN is toggled and a successful soft-start is completed. In the case of an undervoltage event, PGOOD will return high when the output voltage rises above the undervoltage hysteresis level. PGOOD is always low prior to the end of soft-start.

For AMD modes of operation, PGOOD will always be high as long as VSEN is within the specified undervoltage/overvoltage window and soft-start has ended. PGOOD only goes low if

VSEN is outside this window. Even if the controller is shut down the PGOOD signal will still stay high until VSEN falls below the undervoltage threshold.

Overvoltage Protection

The ISL6314 constantly monitors the dif ference between the VSEN and RGND voltages to detect if an overvoltage event occurs. During soft-start, while the DAC is ramping up, the overvoltage trip level is the higher of a fixed voltage 1.27V or DAC + 175mV for Intel modes of operation and DAC + 225mV for AMD modes of operation. Upon successful soft-start, the overvoltage trip level is only DAC + 175mV or DAC + 225mV depending on whether the controller is running in Intel or AMD mode. When the o ut p ut vo l t ag e ri se s ab ov e t h e O V P t ri p le ve l actions are taken by the ISL6314 to protect the microprocessor load.

At the inception of an overvoltage event, LGATE is commanded high and the PGOOD signal is driven low. This turns on the lower MOSFETs and pulls the output voltage below a level that might cause damage to the load. The LGATE output remains high until VSEN falls 100mV below the OVP threshold that tripped the overvoltage protection circuitry. The ISL6314 will continue to protect the load in this fashion as long as the overvoltage condition recurs. Once an overvoltage condition ends, the ISL6314 latches off, and must be reset by toggling EN, or through POR, before a soft-start can be reinitiated.

There is an OVP condition that exists that will not latch off the ISL6314. During a soft-start sequence, if the VSEN voltage is above the OVP threshold an overvoltage event will occur, but will be released once VSEN falls 100mV below the OVP threshold. If VSEN then rises above the OVP trip threshold a second time, the ISL6314 will be latched off and cannot be restarted until the controller is reset.

Pre-POR Overvoltage Protection

Prior to PVCC and VCC exceeding their POR levels, the ISL6314 is designed to protect the load from any overvoltage events that may occur. This is accomplished by means of an internal 10kΩ resistor tied from PHASE to LGATE, which turns on the lower MOSFET to control the output voltage until the overvoltage event ceases or the input power supply cuts off. For complete protection, the low side MOSFET should have a gate threshold well below the maximum voltage rating of the load/microprocessor. In the event that during normal operation the PVCC or VCC voltage falls back below the POR threshold, the pre-POR overvoltage protection circuitry reactivates to protect from any more pre-POR overvoltage events.

Undervoltage Detection

The undervoltage threshold is set at DAC - 350mV of the VID code. When the output voltage (V the undervoltage threshold, PGOOD gets pulled low. No other action is taken by the controller. PGOOD will return high if the output voltage rises above DAC - 250mV.

SEN

- R

GND

) is below

FN6455.2

October 8, 2009

Page 23

Open Sense Line Protection

In the case that either of the remote sense lines (VSEN or RGND) become open, the ISL6314 is designed to prevent the controller from regulating. This is accomplished by means of a small 5µA pull-up current on VSEN, and a pull-down current on RGND. If the sense lines are opened at any time, the voltage difference between V

SEN

and R

GND

will increase until an overvoltage event occurs, at which point overvoltage protection activates and the controller stops regulating. The ISL6314 will be latched off and cannot be restarted until the controller is reset.

Overcurrent Protection

The ISL6314 detects overcurrent events by comparing the droop voltage, V shown in Figure 14. The droop voltage, set by the external current sensing circuitry, is proportional to the output current as shown in Equation 19. A constant 100µA flows through R

, creating the OCSET voltage. When the droop

OCSET

voltage exceeds the OCSET voltage, the overcurrent protection circuitry activates. Since the droop voltage is proportional to the output current, the overcurrent trip level, I

, can be set by selecting the proper value for R

MAX

as shown in Equation 20.

COMP

DROOP

OCSET

---------------------

MAXRCOMP

----------------------------------------------------------

Once the output current exceeds the overcurrent trip level, V

DROOP

will exceed V

the converter to begin overcurrent protection procedures. At the beginning of an overcurrent shutdown, the controller

turns off both upper and lower MOSFETs and lowers PGOOD. The controller will then immediately attempt to soft-start (which includes the 1.1ms delay of either t t

). If the overcurrent fault remains, the trip-retry cycles will

continue until either the controller is disabled or the fault is cleared. But if five overcurrent events occur without successfully completing soft-start, the controller will latch off after the fifth try and must be reset by toggling EN before a soft-start can be reinitiated. Note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. Figure 15 shows an example.

, to the OCSET voltage, V

DROOP

DCR⋅⋅=

OUT

DCR⋅⋅

100μ AR

⋅

, and a comparator will trigger

OCSET

(EQ. 19)

(EQ. 20)

, as

ISL6314

OUTPUT CURRENT, 25A/DIV

OUTPUT VOLTAGE, 500mV/DIV

FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE

1ms/DIV

General Design Guide

This design guide is intended to provide a high-level explanation of the steps necessary to create a power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications.

Power Stage

The first step in designing a power converter using the ISL6314 is to determine if one phase is sufficient (if not, Intersil offers other parts, such as the ISL6313, which has two phases with similar features). This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. Generally speaking, the most economical solutions are those in which the output handles between 25A and 30A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A, but these designs require heat sinks and forced air to cool the MOSFETs, inducto rs and heat-dissipating surfaces.

MOSFETS

The choice of MOSFETs depends on the current each MOSFET will be required to conduct, the switching frequency , the capability of the MOSFETs to dissipate heat, and the availability and nature of heat sinking and air flow .

FN6455.2

October 8, 2009

Page 24

ISL6314

LOWER MOSFET POWER CALCULATION

The calculation for power loss in the lower MOSFET is simple, since virtually all of the loss in the lower MOSFET is due to current conducted through the channel resistance (r output current, I Equation 1), and d is the duty cycle (V

). In Equation 21, IM is the maximum continuous

DS(ON)

LOW 1()rDS ON()

is the peak-to-peak inductor current (see

OUT/VIN

⎛⎞

⎜⎟

----- N

⎝⎠

LP-P()

----------------------------------------+⋅=

1d–()⋅

(EQ. 21)

An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at I f

, and the length of dead times, td1 and td2, at the beginning

, V

, the switching frequency,

D(ON)

and the end of the lower-MOSFET conduction interval respectively . Note that the dead times t

and td2 in

Equation 22 are NOT related to the soft-start timing delays.

LOW 2()VDON()fS

⎛⎞

⋅⋅=

⎜⎟

------

-----------+

⎝⎠

P-P

⎛⎞

⎜⎟

td1⋅

------

–

⎜⎟

⎝⎠

P-P

----------2

td2⋅+

(EQ. 22)

The total maximum power dissipated in each lower MOSFET is approximated by the summation of P

LOW(1)

and P

LOW(2)

UPPER MOSFET POWER CALCULATION

In addition to r

losses, a large portion of the

DS(ON)

upper-MOSFET losses are due to currents conducted across the input voltage (V

) during switching. Since a substantially

higher portion of the upper-MOSFET losses are dependent on switching frequency , the po wer ca lculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times, the lower-MOSFET body-diode reverse-recovery charge, Q and the upper MOSFET r

conduction loss.

DS(ON)

When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 23, the required time for this commutation is t approximated associated power loss is P

⎛⎞

UP 1()VIN

⎛⎞

⋅⋅⋅≈

----- -

----------+

⎝⎠

P-P

----

⎜⎟

⎝⎠

and the

UP(1).

(EQ. 23)

A third component involves the lower MOSFET reverse-recovery charge, Q

. Since the inductor current has

fully commutated to the upper MOSFET before the lower-MOSFET body diode can recover all of Q

, it is

conducted through the upper MOSFET across VIN. The power dissipated as a result is P

UP 3()VINQrrfS

⋅⋅=

, as shown in Equation

UP(3)

(EQ. 25)

25. Finally, the resistive part of the upper MOSFET is given in

Equation 26 as P

UP 4()rDS ON()

UP(4).

⎛⎞

⎜⎟

----- N

⎝⎠

P-P

+⋅⋅≈

---------12

(EQ. 26)

The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 23, 24, 25 and 26. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies.

Package Power Dissipation

When choosing MOSFETs it is important to consider the

amount of power being dissipated in the integrated drivers located in the controller. Since there is one set of drivers in the controller package, the total power dissipated by it must be less than the maximum allowable power dissipation for the QFN package.

Calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125°C. The maximum allowable IC power dissipation for the 5x5 QFN package is approximately 3W at room temperature. See “Layout Considerations” on page 29 for thermal transfer improvement suggestions.

When designing the ISL6314 into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses, P

, due to the gate charge of MOSFETs and the

Qg_TOT

integrated driver’s internal circuitry and their corresponding average driver current can be estimated with Equations 27 and 28, respectively.

At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t approximate power loss is P

⎛⎞

P-P

UP 2()VIN

⋅⋅⋅≈

----------

⎜⎟

–

----- 2

⎝⎠

. In Equation 24, the

UP(2).

⎛⎞

----

⎜⎟

⎝⎠

(EQ. 24)

FN6455.2

October 8, 2009

Page 25

ISL6314

Qg_TOTPQg_Q1PQg_Q2IQ

Qg_Q1

Qg_Q2QG2

-- -

⎛⎞

-- -

⋅ QG2NQ2⋅+

⎝⎠

In Equations 27 and 28, P power loss and P

Qg_Q2

loss; the gate charge (Q

PVCC FSWN

⋅⋅ ⋅⋅=

PVCC FSWN

⋅⋅⋅=

N⋅

Qg_Q1

is the total lower gate drive power

and QG2) is defined at the

VCC⋅++=

+⋅=

SWIQ

(EQ. 27)

(EQ. 28)

is the total upper gate drive

particular gate to source drive voltage PVC C in the corresponding MOSFET data sheet; I quiescent current with no load at both drive outputs; N N

are the number of upper and lower MOSFETs

respectively . The I

VCC product is the quiescent power of

is the driver total

and

the controller without capacitive load and is typically 75 mW at 300kHz.

PVCC

FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

BOOT

PHASE

HI1

LO1

UGATE

GI1R

the MOSFETs. Figures 16 and 17 show the typical upper and lower gate drives turn-on transition path. The total power dissipation in the controller itself, P

, can be roughly

estimated as shown in Equation 29:

DRPDR_UPPDR_LOW PBOOTIQ

Qg_Q1

BOOT

DR_UP

DR_LOW

EXT1RG1

---------------------

⎛⎞

HI1

--------------------------------------

⎜⎟

⎝⎠

HI1REXT1

⎛⎞

HI2

--------------------------------------

⎜⎟

⎝⎠

HI2REXT2

GI1

-------------

LO1

----------------------------------------

LO1REXT1

LO2

----------------------------------------

LO2REXT2

EXT2RG2

VCC⋅()+++=

Qg_Q1

---------------------

⋅=

Qg_Q2

---------------------

⋅=

GI2

-------------

(EQ. 29)

Inductor DCR Current Sensing Component Selection

For accurate load line regulation, the ISL6314 senses the total output current by detecting the voltage across the output inductor DCR (as described in “Load-Line (Droop) Regulation” on page 16). As Figure 18 illustrates, an R-C network is required to accurately sense the inductor DCR voltage and convert this information into a “droop” voltage, which is proportional to the total output current.

PHASE

INDUCTOR I

VL(s)

DCR

OUT

PVCC

HI2

LO2

LGATE

GI2

FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path resistance, P P

, and in the boot strap diode, P

DR_UP

power will be dissipated by the external gate resistors (R and R

) and the internal gate resistors (R

, the lower drive path resistance,

DR_UP

BOOT

. The rest of the

and R

GI1

GI2

) of

ISEN-

COMP

DROOP

ISL6314

ISENO

(OPTIONAL)

ISEN+

FIGURE 18. DCR SENSING CONFIGURATION

Choosing the components for this current sense network is a two step process. First, R chosen so that the time constant of this R

COMP

and C

COMP

must be

- C

COMP

network matches the time constant of the inductor L/DCR. Then the resistor R

must be chosen to set the current

sense network gain, obtaining the desired full load droop voltage. Follow the steps outlined in the following to choose the component values for this R-C network.

FN6455.2

October 8, 2009

Page 26

ISL6314

1. Choose an arbitrary value for C

. The recommended

COMP

value is 0.01µF.

2. Plug the inductor L and DCR component values, and the values for C calculate the value for R

COMP

DCR C

---------------------------------------

3. Use the new value for R

chosen in Step 1, into Equation 30 to

COMP

⋅

COMP

obtained from

COMP

(EQ. 30)

Equation 30, as well as the desired full load current, IFL, full load droop voltage, V

, and inductor DCR in

DROOP

Equation 31 to calculate the value for RS.

------------------------ -

DROOP

COMP

DCR⋅⋅=

(EQ. 31)

Due to errors in the inductance or DCR it may be necessary to adjust the value of R

to match the time constants

correctly. The ef fects of time constant mismatch can be seen in the form of droop overshoot or undershoot during the initial load transient spike, as shown in Figure 19. Follow the steps outlined in the following to ensure the R-C and inductor L/DCR time constants are matched accurately.

1. Capture a transient event with the oscilloscope set to about L/DCR/2 (sec/div). For example, with L = 1µH and DCR = 1mΩ, set the oscilloscope to 500µs/div.

2. Record ΔV1 and ΔV2 as shown in Figure 19.

3. Select new values, R based on the original value, R

V1Δ

1NEW,

4. Replace R

----------

⋅=

1OLD,

with the new value and check to see that the

, for the time constant resistor

1,NEW

, using Equation 32.

1,OLD

(EQ. 32)

error is corrected. Repeat the procedure if necessary.

ΔV

FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR

OUT

TRAN

ΔI

Loadline Regulation Resistor

If loadline regulation is desired, the resistor on the FS pin, R

, should be connected to Ground (the value of RT

separately selects the switching frequency, as per Equation 42). The desired loadline, R by Equation 33 where V at the full load current I

DROOP

------------------------ -= I

is the desired droop voltage

DROOP

, can be calculated

(EQ. 33)

Based on values for Equation 31, the desired loadline can also be calculated from Equation 34.

---------------------------------------=

COMP

DCR⋅

(EQ. 34)

If no loadline regulation is required, the resistor on the FS pin, R

, should be connected to the VCC pin (the value of

separately selects the switching frequency, as per

Equation 42).

APA Pin Component Selection

A 100µA current flows out of the APA pin and across R to set the APA trip level. A 1000pF capacitor, C also be placed across the R

resistor to help with noise

APA

immunity. An APA trip level of 500mV is recommended for most applications. Use Equation 35 to set R

APA

desired APA trip level.

APA

APA TRIP,

-------------------------------

100 106–×

500mV

---------------------------- -

100 106–×

5kΩ===

APA

, should

to get the

(EQ. 35)

Compensation

The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals.

COMPENSATION WITH LOAD-LINE REGULATION

The load-line regulated converter behaves in a similar manner to a peak current mode controller because the two poles at the output filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, R Figure 20.

and CC, as shown in

FN6455.2

October 8, 2009

Page 27

ISL6314

C2 (OPTIONAL)

Case 1:

COMP

ISL6314

------------------------------- -f 2 π LC⋅⋅⋅

CRFB

2 π f0V

----------------------------------------------------------

⋅=

------------------------------------------------------= 2 π V

⋅⋅ ⋅ ⋅

P-PRFBf0

LC⋅⋅⋅ ⋅ ⋅

P-P

VDIFF

FIGURE 20. COMPENSATION CONFIGURA TION FOR

LOAD-LINE REGULATED ISL6314 CIRCUIT

Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately, there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator, by compensating the L-C poles and the ESR zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance.

Select a target bandwidth for the compensated system, f

The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the switching frequency. The values of the compensation components depend on the relationships of f

to the L-C

pole frequency and the ESR zero frequency. For each of the following three, there is a separate set of equations for the compensation components.

In Equation 36, L is the filter inductance; C is the sum total of all output capacitors; ESR is the equivalent series resistance of the bulk output filter capacitance; and V

P-P

is the peak-to-peak sawtooth signal amplitude, as described in the “Electrical Specifications” on page 6.

Once selected, the compensation values in Equation 36 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to R value of R

while observing the transient performance on an

. Slowly increase the

oscilloscope until no further improvement is noted. Normally, C

will not need adjustment. Keep the value of CC from

Equation 36 unless some performance issue is noted.

Case 2:

Case 3:

------------------------------- 2 π LC⋅⋅⋅

CRFB

-------------------------------------------------------------------------------------- -=

2 π⋅()2f

------------------------------------->

2 π C ESR⋅⋅ ⋅

----------------------------------------------------------------- -= 2 π V

The optional capacitor C

P-P

----------------------------------------------------------------- -

⋅=

VINESR C⋅⋅

, is sometimes needed to bypass

-------------------------------------<≤ 2 π C ESR⋅⋅ ⋅

2 π⋅()⋅

P-PRFB

2 π f0V

----------------------------------------------

P-PRFBf0

P-P

ESR⋅

LC⋅⋅⋅

LC⋅⋅⋅ ⋅ ⋅

L⋅⋅ ⋅ ⋅

L⋅⋅ ⋅ ⋅ ⋅

(EQ. 36)

noise away from the PWM comparator (see Figure 20). Keep a position available for C

, and be prepared to install a

high-frequency capacitor of between 22pF and 150pF in case any leading edge jitter problem is noted. For the solutions in Equation 36, R

is selected arbitrarily, typically

in the 1kΩ to 5kΩ range.

COMPENSATION WITHOUT LOAD-LINE REGULATION

The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type III controller, as shown in Figure 21, provides the necessary compensation.

The first step is to choose the desired bandwidth, f

, of the

compensated system. Choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. The type-III compensator has an extra high-frequency pole, f

. This pole can be used for

added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. A good general rule is to choose f higher if desired. Choosing f

=10f0, but it can be

to be lower than 10f0 can

cause problems with too much phase shift below the system bandwidth.

FN6455.2

October 8, 2009

Page 28

ISL6314

FIGURE 21. COMPENSATION CIRCUIT WITHOUT LOAD-LINE

--------------------------------------------

R1R

⋅=

LC⋅ C ESR⋅–

--------------------------------------------= R

-----------------------------------------------------------------------------------------------------=

2 π⋅()2f0f

⎛⎞

VPP2π

⋅

⎝⎠

---------------------------------------------------------------------------------------- -= V

VIN2 π f

-----------------------------------------------------------------------------------------------------=

2 π⋅()

REGULATION

CESR⋅

LC⋅ C ESR⋅–

⋅⋅ ⋅ ⋅ ⋅

2 π f

f0f

⋅⋅ ⋅ ⋅ ⋅

LC⋅()RFBV

f0fHFLCR

⋅⋅ ⋅⋅⋅

LC⋅()RFBV

COMP

ISL6314

VDIFF

P-P

(EQ. 37)

LC⋅ 1–⋅⋅ ⋅()⋅

P-P

In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in Equation 37, R

is selected arbitrarily, typically in the 1kΩ

to 5kΩ range. The remaining compensation components are then selected according to Equation 37.

In Equation 37, L is the filter inductance; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and V

P-P

is the peak-to-peak sawtooth signal amplitude as described in the “Electrical Specifications” on page 6.

Output Filter Design

The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase node. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. The output capacitors must supply or sink load current while the current in the output inductor increases or decreases to meet the demand.

In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) p art of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ΔI, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, ΔV

MAX

. Capacitors are characterized according to their capacitance , ESR, and ESL (equivalent series inductance).

At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output-voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, Equation 38 shows the output voltage initially deviates by an amount as expressed in Equation 38:

ΔVESL

-----

⋅ ESR ΔI⋅+≈

(EQ. 38)

The filter capacitor must have sufficiently low ESL and ESR so that ΔV < ΔV

MAX

Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation.

The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current (see “Output Ripple” on page 10 and Equation 39), a voltage develops across the bulk capacitor ESR equal to I

(ESR). Thus, once the

C(P-P)

output capacitors are selected, the maximum allowable ripple voltage, V

P-P(MAX)

, determines the lower limit on the

inductance.

⎛⎞

–

INVOUT

⎝⎠

----------------------------------------------------------

⋅≥

ESR

⋅⋅

SVINVP-P MAX()

⋅

OUT

(EQ. 39)

Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductor must be capable of assuming the entire load current before the output voltage decreases more than ΔV

. This places an upper limit on inductance.

MAX

Equation 40 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. Equation 41

FN6455.2

October 8, 2009

Page 29

ISL6314

addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the inductance, and C is the total output capacitance.

2CV

⋅⋅

------------------------ -

()

ΔI

C⋅

1.25

--------------------

()

ΔI

ΔV

⋅⋅≤

MAX

ΔIESR⋅()–⋅≤

MAX

ΔI ESR⋅()– VINVO–

⎛⎞ ⎝⎠

(EQ. 40)

(EQ. 41)

Switching Frequency

There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper MOSFET loss calculation. These effects are outlined in “MOSFETs” on page 23, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small output-voltage ripple. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements.

Switching frequency is determined by the selection of the frequency-setting resistor, R are provided to assist in selecting the correct value for R

[]

RT10

10.61 1.035 fS()log⋅()–

500

100

(kΩ)

50 100 1k 2k

SWITCHING FREQUENCY (kHz)

FIGURE 22. R

. Figure 22 and Equation 42

vs SWITCHING FREQUENCY

(EQ. 42)

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the ac component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases.

Use Figure 23 to determine the input-capacitor RMS current requirement set by the duty cycle, maximum sustained output current (I current (I

L(P-P)

), and the ratio of the peak-to-peak inductor

) to IO. Select a bulk capacitor with a ripple

current rating which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least

1.25x greater than the maximum input voltage.

0.6

)

RMS

0.4

0.2

= 0

L(P-P)

= 0.5 I

L(P-P)

INPUT-CAPACITOR CURRENT (I

FIGURE 23. NORMALIZED INPUT-CAP ACITOR RMS

L(P-P)

00.4 1.00.2 0.6 0.8

CURRENT FOR SINGLE-PHASE CONVERTER

= 0.75 I

DUTY CYCLE (V

O/VIN

)

Low capacitance, high-frequency ceramic cap acitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spike s. The spikes result from the high current slew rate produced by the upper MOSFET turn on and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitics and maximize suppression.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. Careful component selection, layout, and placement minimizes these voltage spikes. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turn-off, the upper MOSFET was carrying channel current. During the turn-off, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes.

There are two sets of critical components in a DC/DC converter using a ISL6314 controller. The power components are the most critical because they switch large amounts of energy. Next, are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling.

FN6455.2

October 8, 2009

Page 30

ISL6314

The power components should be placed first, which include the MOSFET s, input and output capacitors, and the inductor . Keep the gate drive traces short, resulting in low trace impedances.

When placing the MOSFETs try to keep the source of the upper FETs and the drain of the lower FETs as close as thermally possible. Input Bulk capacitors should be placed close to the drain of the upper FETs and the source of the lower FETs. Locate the output inductor and output capacitors between the MOSFET s and the load. The high-frequency input and output decoupling capacitors (ceramic) should be placed as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to GND next to, or on the capacitor solder pad.

The critical small components include the bypass capacitors for VCC and PVCC, and many of the components surrounding the controller including the feedback network and current sense components. Locate the VCC and PVCC bypass capacitors as close to the ISL6314 as possible. It is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to EMI pick-up.

A multi-layer printed circuit board is recommended. Figure 24 shows the connections of the critical components for the converter. Note that capacitors C

xxIN

and C

xxOUT

could each represent numerous physical capacitors. Dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer.

Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to output inductor short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase node. Use the remaining printed circuit layers for small signal wiring.

Routing UGATE, LGATE, and PHASE Traces

Great attention should be paid to routing the UGATE, LGATE, and PHASE traces since they drive the power train MOSFETs using short, high current pulses. It is important to size them as large and as short as possible to reduce their overall impedance and inductance. They should be sized to carry at least one ampere of current (0.02” t o 0 . 0 5 ” ) . G o i n g between layers with vias should also be avoided, but if so, use two vias for interconnection when possible.

Extra care should be given to the LGATE traces in particular since keeping their impedance and inductance lo w helps to significantly reduce the possibility of shoot-through. It is also important to route each channels UGATE and PHASE traces in as close proximity as possible to reduce their inductances.

Current Sense Component Placement and Trace Routing

One of the most critical aspects of the ISL6314 regulator layout is the placement of the inductor DCR current sense components and traces. The R-C current sense components must be placed as close to their respective ISEN+ and ISEN- pins on the ISL6314 as possible.

The sense traces that connect the R-C sense components to each side of the output inductors should be routed on the bottom of the board, away from the noisy switching components located on the top of the board. These traces should be routed side by side, and they should be very thin traces. It’s important to route these traces as far away from any other noisy traces or planes as possible. These traces should pick up as little noise as possible.

Thermal Management

For maximum thermal performance in high current, high switching frequency applications, connecting the thermal GND pad of the ISL6314 to the ground plane with multiple vias is recommended. This heat spreading allows the part to achieve its full thermal potential. It is also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6455.2

October 8, 2009

Page 31

(CF1)

ISL6314

DVC

APA

+5V

COMP

APA

VCC

OFS

OFS FS REF

REF

VID7 VID6

VID5

VID4 VID3 VID2 VID1 VID0

DVC

VDIFFDVC

ISL6314

LOCATE CLOSE TO IC

(MINIMIZE CONNECTION PATH)

VSEN RGND

KEY

HEAVY TRACE ON CIRCUIT PLANE LAYER

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

LOCATE NEAR SWITCHING TRANSISTORS;

PVCC

BOOT

UGATE

PHASE

LGATE

(CF2)

BOOT

(MINIMIZE CONNECTION PATH)

+12V

BIN (CHFIN)

HFOUT

)

LOAD

BOUT

LOCATE NEAR LOAD;

(MINIMIZE CONNECTION

PATH)

PGOOD

ISEN+

OCSET ISEN-ISENO

OCSET

COMP

GND

FIGURE 24. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

FN6455.2

October 8, 2009

Page 32

Package Outline Drawing

L32.5x5B

32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 11/07

5.00

PIN 1

INDEX AREA

ISL6314

3.5

0.50

28X

PIN #1 INDEX AREA

(4X) 0.15

( 4. 80 TYP )

TOP VIEW

( 3. 30 )

TYPICAL RECOMMENDED LAND PATTERN

5.00

( 28X 0 . 5 )

(32X 0 . 23 )

( 32X 0 . 60)

0 . 90 ± 0.1

32X 0.40 ± 0.10 4

BOTTOM VIEW

SIDE VIEW

0 . 00 MIN. 0 . 05 MAX.

0 . 2 REF

DETAIL "X"

3 .30 ± 0 . 15

M0.10 C B

32X 0.23

SEE DETAIL "X"

0.10

BASE PLANE

+ 0.07

- 0.05

SEATING PLANE

0.08 C

NOTES:

Dimensions are in millimeters.1. Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Unless otherwise specified, tolerance : Decimal ± 0.05

Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

6. located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN6455.2

October 8, 2009