Datasheet isl6313 Datasheets

Page 1

ISL6313

Data Sheet

Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

The ISL6313 two-phase PWM control IC provides a precision voltage regulation system for advanced microprocessors. The integration of power MOSFET drivers into the controller IC marks a departure from the separate PWM controller and driver configuration of previous multi-phase product families. By reducing the number of external parts, this integration is optimized for a cost and space saving power management solution.

One outstanding feature of this controller IC is its multiprocessor compatibility, allowing it to work with both Intel and AMD microprocessors. Included are programmable VID codes for Intel VR11 as well as AMD 5-bit and 6-bit DAC tables. A circuit is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. The output voltage can also be positively or negatively offset through the use of a single external resistor.

The ISL6313 also includes advanced control loop features for optimal transient response to load apply and removal. One of these features is highly accurate, fully differential, continuous DCR current sensing for load line programming and channel current balance. Active Pulse Positioning (APP) Modulation and Adaptive Phase Alignment (APA) are two other unique features, allowing for quicker initial response to high di/dt load transients. With this quicker initial response to load transients, the number of output bulk capacitors can be reduced, helping to reduce cost.

Integrated into the ISL6313 are user programmable current sense resistors, which require only a single external resistor to set their values. No external current sense resistors are required. Another unique feature of the ISL6313 is the addition of a dynamic VID compensation pin that allows optimizing compensation to be added for well controlled dynamic VID response.

Protection features of this controller IC include a set of sophisticated overvoltage, undervoltage, and overcurrent protection. Furthermore, the ISL6313 includes protection against an open circuit on the remote sensing inputs. Combined, these features provide advanced protection for the microprocessor and power system.

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Features

• Integrated Multi-Phase Power Conversion

- 2-Phase or 1-Phase Operation with Internal Drivers

• Precision Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over-Temperature

- Adjustable Reference-Voltage Offset

• Optimal Transient Response

- Active Pulse Positioning (APP) Modulation

- Adaptive Phase Alignment (APA)

• Fully Differential, Continuous DCR Current Sensing

- Integrated Programmable Current Sense Resistors

- Accurate Load Line Programming

- Precision Channel Current Balancing

• Variable Gate Drive Bias: 5V to 12V

• Multi-Processor Compatible

- Intel VR11 Mode of Operation

- AMD Mode of Operation

• Microprocessor Voltage Identification Inputs

- 8-Bit DAC

- Selectable between Intel VR11, AMD 5-Bit, and AMD 6-Bit DAC tables

- Dynamic VID Technology

• Dynamic VID Compensation

• Overcurrent Protection

• Multi-tiered Overvoltage Protection

• Digital Soft-Start

• Selectable Operation Frequency up to 1.5MHz Per Phase

• Pb-Free (RoHS Compliant)

Ordering Information

PART

NUMBER

(Note)

ISL6313CRZ* ISL6313 CRZ 0 to +70 36 Ld 6x6 TQFN L36.6x6 ISL6313IRZ* ISL6313 IRZ -40 to +85 36 Ld 6x6 TQFN L36.6x6 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on

reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

TEMP.

(°C)

PACKAGE

(Pb-Free)

PKG .

DWG. #

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Page 2

Pinout

ISL6313ISL6313

ISL6313

(36 LD TQFN)

TOP VIEW

35 34 33 32 31 30 29 28

ISEN1-

ISEN1+

ISEN2+

ISEN2-

RSET

VCC

PGOOD

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

10 11 12 13 14 15 16 17 18

REF

IOUT

DVC

ISL6313 Integrated Driver Block Diagram

APA

GND

COMP

OFS

VSEN

RGND

PHASE1

UGATE1

BOOT1

LGATE1

PVCC

LGATE2

BOOT2

UGATE2

PHASE2

PVCC

PWM

SOFT-START

AND

FAULT LOGIC

BOOT

UGATE

20kΩ

GATE

CONTROL

LOGIC

SHOOT-

THROUGH

PROTECTION

10kΩ

PHASE

LGATE

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Block Diagram

ISL6313ISL6313

PGOOD

VSEN

APA

VID7 VID6

VID5 VID4 VID3 VID2 VID1 VID0

RGND

DVC

REF

COMP

RGND

UNDERVOLTAGE

DETECTION

OVERVOLTAGE

DETECTION

MODE / DAC

SELECT

DYNAMIC

VID D/A

OPEN SENSE

LINE PREVENTION

LOGIC

∑

2kΩ

E/A

OCP

I_TRIP

SOFT-START

AND

FAULT LOGIC

ADAPTIVE PHASE

ALLIGNMENT

CIRCUITRY

CLOCK AND

MODULATOR

WAVEFORM

GENERAT OR

∑

0.85V

PWM1

PWM2

POWER-ON

RESET

CHANNEL

DETECT

MOSFET

DRIVER

MOSFET

DRIVER

VCC

PVCC

BOOT1

UGATE1

PHASE1

LGATE1

BOOT2

UGATE2

PHASE2

LGATE2

OFS

IOUT

OFFSET

OCP

I_AVG

CHANNEL CURRENT BALANCE

I_AVG

1 N

∑

CH2

CURRENT

SENSE

CH1

CURRENT

SENSE

GND

ISEN2

ISEN1

ISEN2-

ISEN2+

RSET

ISEN1+

ISEN1-

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Typical Application - ISL6313

ISL6313ISL6313

+5V

COMP

APA

VCC

OFS FS REF

SS IOUT

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

PGOOD

GND

DVC

VSEN

ISL6313

RGND

RSET

BOOT1

UGATE1

PHASE1

LGATE1

ISEN1-

ISEN1+

PVCC

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2-

ISEN2+

+5V VCC

+12V

LOAD

+12V

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ISL6313ISL6313

Typical Application - ISL6313 with NTC Thermal Compensation

+5V

COMP

APA

VCC

OFS FS REF

SS IOUT

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

PGOOD

GND

DVC

VSEN

ISL6313

RGND

RSET

BOOT1

UGATE1

PHASE1

LGATE1

ISEN1-

ISEN1+

PVCC

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2-

ISEN2+

+5V VCC

+12V

NTC

PLACE IN CLOSE

PROXIMITY

LOAD

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ISL6313ISL6313

Absolute Maximum Ratings

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V

BOOT Voltage, V BOOT to PHASE Voltage, V

PHASE Voltage, V

GND - 8V (<400ns, 20µJ) to 24V (<200ns, V

UGATE Voltage, V

PHASE

LGATE Voltage, V

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC + 0.3V

Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V

. . . . . . . . . . . . . .GND - 0.3V to GND + 36V

BOOT

BOOT-PHASE

. . . . . . . GND - 0.3V to 15V (PVCC = 12)

PHASE

. . . . . . . .V

UGATE

- 3.5V (<100ns Pulse Width, 2µJ) to V

. . . . . . . . . . . GND - 0.3V to PVCC + 0.3V

LGATE

. . . . . . -0.3V to 15V (DC)

-0.3V to 16V (<10ns, 10µJ)

BOOT - PHASE

- 0.3V to V

PHASE

BOOT BOOT

= 12V) + 0.3V + 0.3V

Thermal Information

Thermal Resistance θJA (°C/W) θJC (°C/W)

TQFN Package (Notes 1, 2). . . . . . . . . 32 2.0

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .+5V to 12V ±5%

Ambient Temperature

ISL6313CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL6313IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

Tech Brief TB379.

2. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

3. Limits established by characterization and are not production tested.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

BIAS SUPPLIES

Input Bias Supply Current I Gate Drive Bias Current - PVCC Pin I VCC POR (Power-On Reset)

Threshold

PVCC POR (Power-On Reset) Threshold

PWM MODULATOR

Oscillator Frequency Accuracy, F (ISL6313CRZ)

Oscillator Frequency Accuracy, F

(ISL6313IRZ) Adjustment Range of Switching

Frequency Oscillator Ramp Amplitude, V

P-P

CONTROL THRESHOLDS

EN Rising Threshold 0.84 0.85 0.88 V EN Hysteresis - 100 - mV

REFERENCE AND DAC

System Accuracy (1.000V to 1.600V) -0.5 - 0.5 % System Accuracy (0.600V to 1.000V) -1.0 - 1.0 % System Accuracy (0.375V to 0.600V) -2.0 - 2.0 % DAC Input Low Voltage (INTEL) - - 0.4 V

; EN = high 10 14 17 mA

VCC

; EN = high 2 4.2 6 mA

PVCC

VCC rising 4.25 4.38 4.50 V VCC falling 3.75 3.87 4.00 V PVCC rising 4.25 4.38 4.50 V PVCC falling 3.75 3.87 4.00 V

= 100kΩ (±0.1%) 225 250 275 kHz

= 100kΩ (±0.1%) 215 250 280 kHz

(Note 3) 0.08 - 1.0 MHz

(Note 3) - 1.50 - V

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ISL6313ISL6313

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DAC Input High Voltage (INTEL) 0.8 - - V DAC Input Low Voltage (AMD) - - 0.8 V DAC Input High Voltage (AMD) 1.4 - - V

PIN-ADJUSTABLE OFFSET

OFS Sink Current Accuracy (Negative Offset)

OFS Source Current Accuracy (Positive Offset)

ERROR AMPLIFIER

DC Gain R Gain-Bandwidth Product C

Slew Rate C Maximum Output Voltage Load = 1mA 3.90 4.20 - V Minimum Output Voltage Load = -1mA - 1.30 1.52 V

SOFT-START RAMP

Soft-Start Ramp Rate R Adjustment Range of Soft-Start Ramp

Rate (Note 3)

CURRENT SENSING

IOUT Current Sense Offset R IOUT Current Sense Gain

(ISL6313CRZ) IOUT Current Sense Gain

(ISL6313IRZ)

OVERCURRENT PROTECTION

Overcurrent Trip Level - Average Channel

Overcurrent Trip Level - Individual Channel

IOUT Pin Overcurrent Trip Level 1.97 2.02 2.07 V

PROTECTION

Undervoltage Threshold VSEN falling VDAC - 325mV VDAC - 350mV VDAC - 375mV V Undervoltage Hysteresis VSEN rising 85 100 125 mV Overvoltage Threshold During

Soft-Start Overvoltage Threshold VR11, VSEN rising VDAC + 150mV VDAC + 175mV VDAC + 200mV V

Overvoltage Hysteresis VSEN falling - 100 - mV

= 32.4kΩ from OFS to VCC 47.0 50.0 53.0 µA

OFS

= 6.04kΩ from OFS to GND 47.0 50.0 53.0 µA

OFS

= 10k to ground, (Note 3) - 96 - dB

= 100pF, RL = 10k to ground,

-40-MHz

(Note 3)

= 100pF, Load = ±400µA, (Note 3) - 20 - V/µs

= 100kΩ - 1.26 - mV/µs

0.156 - 6.25 mV/µs

SET

= 40.2kΩ, V = 40.2kΩ, V

= 40.2kΩ, V

ISEN1+ ISEN1

ISEN1

= V

= 0V -2.5 0 2.5 µA

ISEN2+

= 24mV768084µA

ISEN2

= 24mV738084µA

ISEN2

Normal operation (ISL6313CRZ) 88 100 112 µA Normal operation (ISL6313IRZ) 82 100 118 µA Dynamic VID change 114 140 166 µA Normal operation 114 140 166 µA Dynamic VID change 166 196 226 µA

VR11 and AMD 1.220 1.260 1.300 V

AMD, VSEN rising VDAC + 200mV VDAC + 225mV VDAC + 250mV V

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ISL6313ISL6313

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SWITCHING TIME (Note 3)

UGATE Rise Time t

RUGATE; VPVCC

90%

LGATE Rise Time t

UGATE Fall Time t

LGATE Fall Time t

RLGATE; VPVCC

90%

FUGATE; VPVCC

10%

FLGATE; VPVCC

10%

UGATE Turn-On Non-Overlap t

LGATE Turn-On Non-Overlap t

PDHUGATE

adaptive

PDHLGATE

adaptive

GATE DRIVE RESISTANCE (Note 3)

Upper Drive Source Resistance V Upper Drive Sink Resistance V Lower Drive Source Resistance V Lower Drive Sink Resistance V

= 12V, 15mA source current 1.25 2.0 3.0 Ω

PVCC

= 12V, 15mA sink current 0.9 1.65 3.0 Ω

PVCC

= 12V, 15mA source current 0.85 1.25 2.2 Ω

PVCC

= 12V, 15mA sink current 0.60 0.80 1.35 Ω

PVCC

OVER-TEMPERATURE SHUTDOWN (Note 3)

Thermal Shutdown Setpoint - 160 - °C Thermal Recovery Setpoint - 100 - °C

= 12V, 3nF load, 10% to

= 12V, 3nF load, 90% to

; V

= 12V, 3nF load,

PVCC

; V

= 12V, 3nF load,

PVCC

-26-ns

-18-ns

-12-ns

-10-ns

Timing Diagram

UGATE

LGATE

PDHUGATE

FLGATE

RUGATE

PDHLGATE

FUGATE

RLGATE

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ISL6313ISL6313

Functional Pin Description

VCC

VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1µF ceramic capacitor.

PVCC

This pin is the power supply pin for the channel MOSFET drivers, and can be connected to any voltage from +5V to +12V depending on the desired MOSFET gate-drive level. Decouple this pin with a quality 1.0µF ceramic capacitor.

GND

GND is the bias and reference ground for the IC.

This pin is a threshold-sensitive (approxima tely 0.85V) enable input for the controller. Held low, this pin disables controller operation. Pulled high, the pin enables the controller for operation.

A resistor, RS, tied to this pin sets the channel switching frequency of the controller. Refer to Equation 47 for proper resistor calculation.

The FS pin also controls whether the internal I connected to the FB pin or not. Tying the R ground connects the I allowing the converter to incorporate output voltage droop proportional to the output current. Tying the R VCC, disconnects the I pin.

current internally to the FB pin,

AVG

current internally from the FB

AVG

VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7

These are the inputs for the internal DAC that provides the reference voltage for output regulation. These pins respond to TTL logic thresholds. These pins are internally pulled high, to approximately 1.2V, by 40µA internal current sources for Intel modes of operation, and pulled low by 20µA internal current sources for AMD modes of operation. The internal pull-up current decreases to 0 as the VID voltage approaches the internal pull-up voltage. All VID pins are compat ible with external pull-up voltages not exceeding the IC’s bias voltage (VCC).

VSEN

This pin senses the microprocessor’s CORE voltage. Connect this pin to the CORE voltage sense pin or point of the microprocessor.

RGND

This pin senses the local ground voltage of the microprocessor and offsets the internal DAC by this sensed voltage. Connect this pin to the Ground sense pin or point of the microprocessor.

current is

AVG

resistor to

FB and COMP

These pins are the internal error amplifier inverting input and output respectively. The FB pin, COMP pin, and the VSEN pins are tied together through external R-C networks to compensate the regulator.

DVC

A series resistor and capacitor can be connected from the DVC pin to the FB pin to compensate and smooth dynamic VID transitions.

IOUT

The IOUT pin is the average channel-current sense output. This pin is used as a load current indicator to monitor what the output load current is.

This pin can also be used to set the overcurrent protection trip level if it desired that a lower level be used then the internal trip point. Connecting this pin through a resistor to ground allows the controller to set the alternate overcurrent protection trip level.

APA

This is the Adaptive Phase Alignment set pin. A 100µA current flows into the APA pin and by tying a resistor from this pin to COMP the trip level for the Adaptive Phase Alignment circuitry can be set.

REF

The REF input pin is the positive input of the error amplifier. It is internally connected to the DAC output through a 2kΩ resistor. A cap acitor is used between the REF pin and gro und to smooth the voltage transition during soft-start and Dynamic VID transitions. This pin can also be bypassed to RGND if desired.

RSET

Connect this pin to VCC through a resistor to set the effective value of the internal R recommended a 0.1µF ceramic capacitor be placed in parallel with this resistor for noise immunization.

current sense resistors. It is

ISEN

OFS

The OFS pin provides a means to program a dc current for generating an offset voltage across the re sistor betwe en FB and VSEN. The offset current is generated via an external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left unconnected.

ISEN1-, ISEN1+, ISEN2-, and ISEN2+

These pins are used for differentially sensing the corresponding channel output currents. The sensed currents are used for channel balancing, protection, and load line regulation.

Connect ISEN1- and ISEN2- to the node between the RC sense elements surrounding the inductor of their respective

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ISL6313ISL6313

channel. Tie the ISEN+ pins to the VCORE side of their corresponding channel’s sense capacitor.

Tying ISEN2- to VCC programs the part for single phase operation.

UGATE1 and UGATE2

Connect these pins to the corresponding upper MOSFET gates. These pins are used to control the upper MOSFETs and are monitored for shoot-through prevention purposes.

BOOT1 and BOOT2

These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect these pins to appropriately chosen external bootstrap capacitors. Internal bootstrap diodes connected to the PVCC pin provides the necessary bootstrap charge.

PHASE1 and PHASE2

Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return path for the upper MOSFET drives.

LGATE1 and LGATE2

These pins are used to control the lower MOSFET s. Connect these pins to the corresponding lower MOSFETs’ gates.

A resistor, RSS, placed from SS to ground or VCC, will set the soft-start ramp slope. Refer to Equations 20 and 21 for proper resistor calculation.

The state of the SS pin also selects which of the available DAC tables will be used to decode the VID inputs and puts the controller into the corresponding mode of operation. For Intel VR1 1 mode of operation the R ground. AMD compliance is selected if the R

resistor should be tied to

resistor is tied

to VCC.

PGOOD

For Intel mode of operation, PGOOD indicates whether VSEN is within specified overvoltage and undervolt age limit s after a fixed delay from the end of soft-start. If VSEN exceeds these limits, an overcurrent event occurs, or if the part is disabled, PGOOD is pulled low. PGOOD is always low prior to the end of soft-start.

Operation

Multiphase Power Conversion

Microprocessor load current profiles have changed to the point that using single-phase regulators is no longer a viable solution. Designing a regulator that is cost-effective, thermally sound, and efficient has become a challenge that

only multi-phase converters can accomplish. The ISL6313 controller helps simplify implementation by integrating vital functions and requiring minimal external components. The “Block Diagram” on page 3 provides a top level view of multi-phase power conversion using the ISL6313 controller.

IL1 + IL2 + IL3, 7A/DIV

IL3, 7A/DIV

PWM3, 5V/DIV

IL2, 7A/DIV

PWM2, 5V/DIV

IL1, 7A/DIV

PWM1, 5V/DIV

1µs/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

Interleaving

The switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels. In a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. In addition, the peak-to-peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (Equations 1 and 2). Increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification.

Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (I combine to form the AC ripple current and the DC load current. The ripple component has 3x the ripple frequency of each individual channel current. Each PWM pulse is terminated 1/3 of a cycle after the PWM pulse of the previous phase. The peak-to-peak current for each phase is about 7A, and the DC components of the inductor currents combine to feed the load.

T o understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel peak-to-peak inductor current.

VINV

----------------------------------------------------------=

–()V

In Equation 1, V

OUT

V⋅IN⋅

and V

⋅

OUT

are the input and output

OUT

voltages respectively, L is the single-channel inductor value, and f

is the switching frequency.

, IL2, and IL3)

(EQ. 1)

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ISL6313ISL6313

The output capacitors conduct the ripple component of the inductor current. In the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Compare Equation 1 to the expression for the peak-to-peak current after the summation of N symmetrically phase-shifted inductor currents in Equation 2. Peak-to-peak ripple current decreases by an amount proportional to the number of channels. Output voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors.

CP-P()

------------------------------------------------------------------- -=

⋅–()V

OUT

⋅

OUT

V⋅IN⋅

(EQ. 2)

VINNV

Another benefit of interleaving is to reduce input ripple current. Input capacitance is determined in part by the maximum input ripple current. Multiphase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. The example in Figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current.

The converter depicted in Figure 2 delivers 1.5V to a 36A load from a 12V input. The RMS input capacitor current is 5.9A. Compare this to a single-phase converter also stepping down 12V to 1.5V at 36A. The single-phase converter has

11.9A

input capacitor current. The single-phase converter

RMS

must use an input capacitor bank with twice the RMS current capacity as the equivalent three-phase converter.

INPUT-CAPACITOR CURRENT, 10A/DIV

which a PWM signal can occur is generated by an internal clock, whose cycle time is the inverse of the switching frequency set by the resistor connected to the FS pin. The advantage of Intersil’s proprietary Active Pulse Positioning (APP) modulator is that the PWM signal has the ability to turn on at any point during this PWM time interval, and turn off immediately after the PWM signal has transitioned high. This is important because it allows the controller to quickly respond to output voltage drops associated with current load spikes, while avoiding the ring back affects associated with other modulation schemes.

The PWM output state is driven by the position of the error amplifier output signal, V

minus the current correction

COMP

signal relative to the proprietary modulator ramp waveform as illustrated in Figure 4. At the beginning of each PWM time interval, this modified V

signal is compared to the

COMP

internal modulator waveform. As long as the modified V

voltage is lower then the modulator waveform

COMP

voltage, the PWM signal is commanded low. The internal MOSFET driver detects the low state of the PWM signal and turns off the upper MOSFET and turns on the lower synchronous MOSFET. When the modified V

COMP

voltage crosses the modulator ramp, the PWM output transitions high, turning off the synchronous MOSFET and turning on the upper MOSFET. The PWM signal will remain high until the modified V

voltage crosses the modulator ramp

COMP

again. When this occurs the PWM signal will transition low again.

During each PWM time interval the PWM signal can only transition high once. Once PWM transitions high it can not transition high again until the beginning of the next PWM time interval. This prevents the occurrence of double PWM pulses occurring during a single period.

CHANNEL 3 INPUT CURRENT

CHANNEL 2 INPUT CURRENT

CHANNEL 1 INPUT CURRENT

1µs/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND

INPUT-CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER

Active Pulse Positioning (APP) Modulated PWM Operation

The ISL6313 uses a proprietary Active Pulse Positioning (APP) modulation scheme to control the internal PWM signals that command each channel’s driver to turn their upper and lower MOSFETs on and off. The time interval in

EXTERNAL CIRCUIT

APA

FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION

APA

APA,TRIP

COMP

ISL6313 INTERNAL CIRCUIT

100µA

LOW

PASS

FILTER

ERROR

AMPLIFIER

APA

CIRCUITRY

TO APA

Adaptive Phase Alignment (APA)

To further improve the transient response, the ISL6313 also implements Intersil’s proprietary Adaptive Phase Alignment (APA) technique, which turns on all of the channels together at the same time during large current step transient events.

FN6448.2

September 2, 2008

Page 12

As Figure 3 shows, the APA circuitry works by monitoring the voltage on the APA pin and comparing it to a filtered copy of the voltage on the COMP pin. The voltage on the APA pin is a copy of the COMP pin voltage that has been negatively offset. If the APA pin exceeds the filtered COMP pin voltage an APA event occurs and all of the channels are forced on.

The APA trip level is the amount of DC offset between the COMP pin and the APA pin. This is the voltage excursion that the APA and COMP pin must have during a transient event to activate the Adaptive Phase Alig nment circuitry. This APA trip level is set through a resistor, R

APA

, that connects from the APA pin to the COMP pin. A 100µA current flows across R

into the APA pin to set the APA

APA

trip level as described in Equation 3. An APA trip level of 500mV is recommended for most applications. A 1000pF capacitor , C

, should also be placed across the R

APA

resistor to help with noise immunity.

ISL6313ISL6313

COMP

FIGURE 4. CHANNEL-1 PWM FUNCTION AND

∑

FILTER

f(s)

∑

CURRENT-BALANCE ADJUSTMENT

AVG

MODULATOR

RAMP

WAVEFORM

÷ 2

PWM1

∑

The filtered error signal modifies the pulse width commanded by V I

toward zero. The same method for error signal

to correct any unbalance and force

COMP

correction is applied to each active channel.

TO GATE

CONTROL

LOGIC

APA TRIP()RAPA

100 106–×⋅=

(EQ. 3)

Number of Active Channels

The default number of active channels on the ISL6313 is two for 2-phase operation. If single phase operation is desired the ISEN2- pin should be tied to the VCC pin. This will disable Channel 2, so only Channel 1 will fire. In single phase operation all of the Channel 2 pins should be left unconnected including the PHASE2, LGATE2, UGATE2, BOOT2, and ISEN2+ pins.

Channel-Current Balance

One important benefit of multi-phase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. By doing this the designer avoids the complexity of driving parallel MOSFETs and the expense of using expensive heat sinks and exotic magnetic materials.

In order to realize the thermal advantage, it is important that each channel in a multi-phase converter be controlled to carry equal amounts of current at any load level. To achieve this, the currents through each channel must be sensed continuously every switching cycle. The sensed currents, I from each active channel are summed together and divided by the number of active channels. The resulting cycle average current, I

, provides a measure of the total

AVG

load-current demand on the converter during each switching cycle. Channel-current balance is achieved by comparing the sensed current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current-balance method is illustrated in Figure 4, with error correction for Channel 1 represented. In the figure, the cycle average current, I sensed current, I

, is compared with the Channel 1

AVG

, to create an error signal IER.

PWM

SWITCHING PERIOD

SEN

TIME

FIGURE 5. CONTINUOUS CURRENT SAMPLING

Continuous Current Sensing

In order to realize proper current-balance, the currents in each channel are sensed continuously every switching cycle. During this time the current-sense amplifier uses the

ISEN inputs to reproduce a signal proportional to the inductor current, I

. This sensed current, I

, is simply a

SEN

scaled version of the inductor current. The ISL6313 supports inductor DCR current sensing to

continuously sense each channel’s current for channel-current balance. The internal circuitry, shown in Figure 6 represents channel n of an N-Channel converter. This circuitry is repeated for each channel in the converter, but may not be active depending on how many channels are operating.

FN6448.2

September 2, 2008

Page 13

ISL6313

UGATE

MOSFET

DRIVER

SENSE

FIGURE 6. INDUCTOR DCR CURRENT SENSING

LGATE

ISL6313 INTERNAL

CIRCUIT

SEN

CONFIGURATION

VC(s)

ISEN

INDUCTOR

VL(s)

ISEN-

ISEN+

RSET

VC(s)

DCR

SET

OUT

VCC

Inductor windings have a characteristic distributed resistance or DCR (Direct Current Resistance). For simplicity, the inductor DCR is considered as a separate lumped quantity, as shown in Figure 6. The channel current I

, flowing through the inductor, passes through the DCR.

Equation 4 shows the s-domain equivalent voltage, V

across the inductor.

VLs() ILsL DCR+⋅()⋅=

A simple R-C network across the inductor (R

and C)

(EQ. 4)

extracts the DCR voltage, as shown in Figure 6. The voltage across the sense capacitor, V proportional to the channel current I

sL⋅

⎛⎞

-------------

s()

If the R

⎝⎠

-----------------------------------------

⋅⋅ 1+()

network components are selected such that

1-C1

DCR

1C1

, can be shown to be

, shown in Equation 5.

⋅⋅=

DCR I

(EQ. 5)

their time constant matches the inductor L/DCR time constant, then V

is equal to the voltage drop across the

DCR. The capacitor voltage V

effective internal sense resistance R current through R current. This current, I

, is then replicated across the

which is proportional to the inductor

ISEN

, is continuously sensed and is

SEN

. This develops a

ISEN

then used by the controller for load-line regulation, channel-current balancing, and overcurrent detection and limiting. Equation 6 shows that the proportion between the channel-current, I

, and the sensed current, I

, is driven

SEN

by the value of the effective sense resistance, R

ISEN

, and

the DCR of the inductor.

DCR

SENIL

The effective internal R

----------------- -

⋅=

ISEN

resistance is important to the

ISEN

(EQ. 6)

current sensing process because it sets the gain of the load line regulation loop as well as the gain of the channel-current balance loop and the overcurrent trip level. The effective internal R through use of the RSET pin. Placing a single resistor, R

resistance is user programmable and is set

ISEN

SET

from the RSET pin to the VCC pin programs the effective internal R important to note that the R

resistance according to Equation 7. It is

ISEN

resistance value must be

SET

between 20kΩ and 80kΩ for Equation 7 to be valid.

--------- -

ISEN

*Note: R

⋅=

SET

400

must be between 20kΩ and 80kΩ

SET

(EQ. 7)

Output Voltage Setting

The ISL6313 uses a digital to analog converter (DAC) to generate a reference voltage based on the logic signals at the VID pins. The DAC decodes the logic signals into one of the discrete voltages shown in Tables 2, 3 or 4. In the Intel VR11 mode of operation, each VID pin is pulled up to an internal 1.2V voltage by a weak current source (40µA), which decreases to 0A as the voltage at the VID pin varies from 0 to the internal 1.2V pull-up voltage. In AMD modes of operation the VID pins are pulled low by a week 20µA current source. External pull-up resistors or active-high output stages can augment the pull-up current sources, up to a voltage of 5V.

The ISL6313 accommodates three different DAC ranges: Intel VR11, AMD K8/K9 5-bit, and AMD 6-bit. The state of the SS and VID7 pins decide which DAC version is active. Refer to T able 1 for a description of how to select the desired DAC version.

TABLE 1. ISL6313 DAC SELECT TABLE

DAC VERSION SS PIN VID7 PIN

INTEL VR11 R

AMD 5-bit R

AMD 6-bit R

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

00000000OFF 00000001OFF

000000101.60000

000000111.59375

resistor tied to

GND

resistor tied to

VCC

resistor tied to

VCC

high

low

FN6448.2

September 2, 2008

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ISL6313

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

000001001.58750

000001011.58125

000001101.57500

000001111.56875

000010001.56250

000010011.55625

000010101.55000

000010111.54375

000011001.53750

000011011.53125

000011101.52500

000011111.51875

000100001.51250

000100011.50625

000100101.50000

000100111.49375

000101001.48750

000101011.48125

000101101.47500

000101111.46875

000110001.46250

000110011.45625

000110101.45000

000110111.44375

000111001.43750

000111011.43125

000111101.42500

000111111.41875

001000001.41250

001000011.40625

001000101.40000

001000111.39375

001001001.38750

001001011.38125

001001101.37500

001001111.36875

001010001.36250

001010011.35625

001010101.35000

001010111.34375

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

001011001.33750

001011011.33125

001011101.32500

001011111.31875

001100001.31250

001100011.30625

001100101.30000

001100111.29375

001101001.28750

001101011.28125

001101101.27500

001101111.26875

001110001.26250

001110011.25625

001110101.25000

001110111.24375

001111001.23750

001111011.23125

001111101.22500

001111111.21875

010000001.21250

010000011.20625

010000101.20000

010000111.19375

010001001.18750

010001011.18125

010001101.17500

010001111.16875

010010001.16250

010010011.15625

010010101.15000

010010111.14375

010011001.13750

010011011.13125

010011101.12500

010011111.11875

010100001.11250

010100011.10625

010100101.10000

010100111.09375

FN6448.2

September 2, 2008

Page 15

ISL6313

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

010101001.08750

010101011.08125

010101101.07500

010101111.06875

010110001.06250

010110011.05625

010110101.05000

010110111.04375

010111001.03750

010111011.03125

010111101.02500

010111111.01875

011000001.01250

011000011.00625

011000101.00000

011000110.99375

011001000.98750

011001010.98125

011001100.97500

011001110.96875

011010000.96250

011010010.95625

011010100.95000

011010110.94375

011011000.93750

011011010.93125

011011100.92500

011011110.91875

011100000.91250

011100010.90625

011100100.90000

011100110.89375

011101000.88750

011101010.88125

011101100.87500

011101110.86875

011110000.86250

011110010.85625

011110100.85000

011110110.84375

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

011111000.83750

011111010.83125

011111100.82500

011111110.81875

100000000.81250

100000010.80625

100000100.80000

100000110.79375

100001000.78750

100001010.78125

100001100.77500

100001110.76875

100010000.76250

100010010.75625

100010100.75000

100010110.74375

100011000.73750

100011010.73125

100011100.72500

100011110.71875

100100000.71250

100100010.70625

100100100.70000

100100110.69375

100101000.68750

100101010.68125

100101100.67500

100101110.66875

100110000.66250

100110010.65625

100110100.65000

100110110.64375

100111000.63750

100111010.63125

100111100.62500

100111110.61875

101000000.61250

101000010.60625

101000100.60000

101000110.59375

FN6448.2

September 2, 2008

Page 16

ISL6313

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

101001000.58750

101001010.58125

101001100.57500

101001110.56875

101010000.56250

101010010.55625

101010100.55000

101010110.54375

101011000.53750

101011010.53125

101011100.52500

101011110.51875

101100000.51250

101100010.50625

101100100.50000 11111110OFF 11111111OFF

TABLE 3. AMD 5-BIT VOLTAGE IDENTIFICATION

CODES

VID4 VID3 VID2 VID1 VID0 VDAC

11111Off

111100.800

111010.825

111000.850

110110.875

110100.900

110010.925

110000.950

101110.975

101101.000

101011.025

101001.050

100111.075

100101.100

100011.125

100001.150

011111.175

011101.200

011011.225

011001.250

TABLE 3. AMD 5-BIT VOLTAGE IDENTIFICATION

CODES (Continued)

VID4 VID3 VID2 VID1 VID0 VDAC

010111.275

010101.300

010011.325

010001.350

001111.375

001101.400

001011.425

001001.450

000111.475

000101.500

000011.525

000001.550

TABLE 4. AMD 6-BIT VOLTAGE IDENTIFICATION

CODES

VID5 VID4 VID3 VID2 VID1 VID0 VDAC

0 0 0 0 0 0 1.5500

0 0 0 0 0 1 1.5250

0000101.5000

0000111.4750

0001001.4500

0001011.4250

0001101.4000

0001111.3750

0010001.3500

0010011.3250

0010101.3000

0010111.2750

0011001.2500

0011011.2250

0011101.2000

0011111.1750

0100001.1500

0100011.1250

0100101.1000

0100111.0750

0101001.0500

0101011.0250

0101101.0000

0101110.9750

0110000.9500

0110010.9250

FN6448.2

September 2, 2008

Page 17

ISL6313

TABLE 4. AMD 6-BIT VOLTAGE IDENTIFICATION

CODES (Continued)

VID5 VID4 VID3 VID2 VID1 VID0 VDAC

0110100.9000

0110110.8750

0111000.8500

0111010.8250

0111100.8000

0111110.7750

1000000.7625

1000010.7500

1000100.7375

1000110.7250

1001000.7125

1001010.7000

1001100.6875

1001110.6750

1010000.6625

1010010.6500

1010100.6375

1010110.6250

1011000.6125

1011010.6000

1011100.5875

1011110.5750

1100000.5625

1100010.5500

1100100.5375

1100110.5250

1101000.5125

1101010.5000

1101100.4875

1101110.4750

1110000.4625

1110010.4500

1110100.4375

1110110.4250

1111000.4125

1111010.4000

1111100.3875

1111110.3750

Voltage Regulation

The integrating compensation network shown in Figure 7 insures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6313 to include the combined tolerances of each of these elements.

The output of the error amplifier, V

, is used by the

COMP

modulator to generate the PWM signals. The PWM signals control the timing of the Internal MOSFET drivers and regulate the converter output so that the voltage at FB is equal to the voltage at REF. This will regulate the output voltage to be equal to Equation 8. The internal and external circuitry that controls voltage regulation is illustrated in Figure 7.

OUTVREFVOFS

– V

–=

DROOP

(EQ. 8)

The ISL6313 incorporates differential remote-sense amplification in the feedback path. The differential sensing removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point resulting in a more accurate means of sensing output voltage.

EXTERNAL CIRCUIT ISL6313 INTERNAL CIRCUIT

COMP

REF

OUT

DROOP

+ V

OFS

VSEN

RGND

)

FIGURE 7. OUTPUT VOLT AGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

AVG

OFS

AMPLIFIER

∑

ERROR

VID

DAC

COMP

Load-Line (Droop) Regulation

Some microprocessor manufacturers require a precisely-controlled output resistance. This dependence of output voltage on load current is often termed “droop” or “load line” regulation. By adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers.

FN6448.2

September 2, 2008

Page 18

ISL6313

In other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results from fast load-current demand changes.

The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit.

As shown in Figure 7, a current proportional to the average current of all active channels, I load-line regulation resistor R across R

is proportional to the output current, effectively

, flows from FB through a

AVG

. The resulting voltage drop

creating an output voltage droop with a steady-state value defined as Equation 9:

DROOPIAVGRFB

⋅=

(EQ. 9)

The regulated output voltage is reduced by the droop voltage V

. The output voltage as a function of load current is

DROOP

derived by combining Equations 6, 8, and 9.

OUTVREFVOFS

–

⎛⎞

–=

⎜⎟ ⎝⎠

DCR

OUT

-------------

----------------- -

⋅⋅

ISEN

(EQ. 10)

For Negative Offset (connect R

1.6 RFB⋅

OFS

--------------------------

OFFSET

For Positive Offset (connect R

0.3 RFB⋅

--------------------------

OFS

OFFSET

VSEN

OFS

GND

VREF

ISL6313

OFS

to VCC):

to GND):

E/A

GND

(EQ. 12)

(EQ. 13)R

1.6V

0.3V

VCC

In Equation 10, V programmed offset voltage, I of the converter, R connected to the ISEN+ pin, R

is the reference voltage, V

REF

is the internal sense resistor

ISEN

is the total output current

OUT

is the feedback resistor, N

OFS

is the

is the active channel number, and DCR is the Inductor DCR value.

Therefore the equivalent loadline impedance, i.e. droop impedance, is equal to:

DCR

------------

----------------- -

⋅=

ISEN

(EQ. 11)

Output-Voltage Offset Programming

The ISL6313 allows the designer to accurately adjust the offset voltage by connecting a resistor, R pin to VCC or GND. When R

is connected between OFS

OFS

and VCC, the voltage across it is regulated to 1.6V. This causes a proportional current (I

) to flow into the OFS pin

OFS

and out of the FB pin, providing a negative offset. If R connected to ground, the voltage across it is regulated to

0.3V, and I

flows into the FB pin and out of the OFS pin,

OFS

providing a positive offset. The offset current flowing through the resistor between VSEN and FB will generate the desired offset voltage which is equal to the product (I These functions are shown in Figures 8 and 9.

, from the OFS

OFS

x RFB).

OFS

FIGURE 8. POSITIVE OFFSET OUTPUT VOL T AGE

VSEN

OFS

VCC

OFS

FIGURE 9. NEGATIVE OFFSET OUTP UT VOL TAGE

PROGRAMMING

OFS

PROGRAMMING

ISL6313

VREF

E/A

GND

0.3V

VCC

1.6V

Once the desired output offset voltage has been determined, use Equations 12 and 13 to set R

OFS

FN6448.2

September 2, 2008

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ISL6313

Dynamic VID

Modern microprocessors need to make changes to their core voltage as part of normal operation. They direct the ISL6313 to do this by making changes to the VID inputs. The ISL6313 is required to monitor the DAC inputs and respond to on-the-fly VID changes in a controlled manner, supervising a safe output voltage transition without discontinuity or disruption. The DAC mode the ISL6313 is operating in, determines how the controller responds to a dynamic VID change.

INTEL DYNAMIC VID TRANSITIONS

When in Intel VR11 mode the ISL6313 checks the VID inputs on the positive edge of an internal 5.5MHz clock. If a new code is established and it remains stable for 3 consecutive readings (0.36µs to 0.54µs), the ISL6313 recognizes the new code and changes the internal DAC reference directly to the new level. The Intel processor controls the VID transitions and is responsible for incrementing or decrementing one VID step at a time. In VR1 1 mode, the ISL6313 will immediately change the internal DAC reference to the new requested value as soon as the request is validated, which means the fastest recommended rate at which a bit change can occur is once every 1µs. If the VID code is changed by more then one step at a time, the DAC will try to track it at a 5.5MHz step rate. This will likely cause an overcurrent or overvoltage fault.

AMD DYNAMIC VID TRANSITIONS

When running in AMD 5-bit or 6-bit modes of operation, the ISL6313 responds differently to a dynamic VID change then when in I nte l VR 11 mo de. In the AMD modes the ISL6313 still checks the VID inputs on the positive edge of an internal

5.5MHz clock. In these modes the VID code can be changed by more than a 1-bit step at a time. If a new code is established and it remains stable for 3 consecutive readings (0.36µs to 0.54µs), the ISL6313 recognizes the change and begins slewing the DAC in 6.25mV steps at a stepping frequency of 345kHz until the VID and DAC are equal. Thus, the total time required for a VID change, t only on the size of the VID change (ΔV

The time required for a ISL6313-based converter in AMD 5-bit DAC configuration to make a 1.1V to 1.5V reference voltage change is about 186µs, as calculated using Equation 14.

DVID

------------------------- -

345 10

VID

⎛⎞

---------------------

⋅=

⎝⎠

0.00625

VID “OFF” DAC CODES

Both the Intel VR1 1 and the AMD 5-bit VID t ables include “Of f” DAC codes, which indicate to the controller to disable all regulation. Recognition of these codes is slightly different in that they must be stable for 4 consecutive readings of a 5.5MHz clock (0.54µs to 0.72µs) to be recognized. Once an “Of f” code is recognized the ISL6313 latches off, and must be reset by dropping the EN pin.

VID

DVID

, is dependent

(EQ. 14)

Compensating Dynamic VID Transitions

During a VID transition, the resulting change in voltage on the FB pin and the COMP pin causes an AC current to flow through the error amplifier compensation components from the FB to the COMP pin. This current then flows through the feedback resistor, R overshoot or undershoot at the end of the VID transition. In order to ensure the smooth transition of the output voltage during a VID change, a VID-on-the-fly compensation network is required. This network is composed of a resistor and capacitor in series, R and the FB pin.

VSEN

DVC

REF

DAC

FIGURE 10. DYNAMIC VID COMPENSATION NETWORK

This VID-on-the-fly compensation network works by sourcing AC current into the FB node to offset the effects of the AC current flowing from the FB to the COMP pin during a VID transition. To create this compensation current the ISL6313 sets the voltage on the DVC pin to be 2x the voltage on the REF pin. Since the error amplifier forces the voltage on the FB pin and the REF pin to be equal, the resulting voltage across the series RC between DVC and FB is equal to the REF pin voltage. The RC compensation components, R

and C

DVC

amount of compensation current. The amount of compensation current required is dependant

on the modulator gain of the system, K1, and the error amplifier R-C components, R between the FB and COMP pins. Use Equations 15, 16, and 17 to calculate the RC component values, R for the VID-on-the-fly compensation network. For these equations: V

is the input voltage for the power train; V

is the oscillator ramp amplitude (1.5V); and R the error amplifier R-C components between the FB and COMP pins.

------------

P-P

DVC

×=

------- -

, and can cause the output voltage to

+ R

DVC

GND

DVC

and C

DVC

ISL6313 INTERNAL CIRCUIT

, between the DVC

DVC

= I

ERROR

AMPLIFIER

COMP

, can then be selected to create the desired

and CC, that are in series

and C

DVC

and CC are

---------------- -

K1 1–

DVC

P-P

(EQ. 15)

(EQ. 16)

(EQ. 17)

FN6448.2

September 2, 2008

Page 20

ISL6313

Advanced Adaptive Zero Shoot-Through Deadtime Control (Patent Pending)

The integrated drivers incorporate a unique adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower MOSFET body-diode conduction, and to prevent the upper and lower MOSFETs from conducting simultaneously. This is accomplished by ensuring either rising gate turns on its MOSFET with minimum and sufficient delay after the other has turned off.

During turn-off of the lower MOSFET, the PHASE voltage is monitored until it reaches a -0.3V/+0.8V (forward/reverse inductor current). At this time the UGA TE is released to rise. An auto-zero comparator is used to correct the r

DS(ON)

drop in the phase voltage preventing false detection of the -0.3V phase level during r

DS(ON)

conduction period. In the case of zero current, the UGA TE is released after 35ns delay of the LGATE dropping below 0.5V. When LGATE first begins to transition low, this quick transition can disturb the PHASE node and cause a false trip, so there is 20ns of blanking time once LGA TE falls until PHASE is monitored.

Once the PHASE is high, the advanced adaptive shoot-through circuitry monitors the PHASE and UGATE voltages during a PWM falling edge and the subsequent UGATE turn-off. If either the UGATE falls to less than 1.75V above the PHASE or the PHASE falls to less than +0.8V , the LGATE is released to turn-on.

Internal Bootstrap Device

All three integrated drivers feature an internal bootstrap schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the PHASE node. This reduces voltage stress on the boot to phase pins.

1.6

1.4

The bootstrap capacitor must have a maximum voltage rating above PVCC + 4V and its capacitance value can be chosen from Equation 18:

GATE

BOOT_CAP

GATE

where Q at V

GS1

control MOSFETs. The ΔV

--------------------------------------

≥

ΔV

BOOT_CAP

QG1PVCC⋅

----------------------------------

GS1

is the amount of gate charge per upper MOSFET

⋅=

(EQ. 18)

gate-source voltage and NQ1 is the number of

BOOT_CAP

term is defined as the

allowable droop in the rail of the upper gate drive.

Gate Drive Voltage Versatility

The ISL6313 provides the user flexibility in choosing the gate drive voltage for efficiency optimization. The controller ties the upper and lower drive rails together. Simply applying a voltage from 5V up to 12V on PVCC sets both gate drive rail voltages simultaneously.

Initialization

Prior to initialization, proper conditions must exist on the EN, VCC, PVCC and the VID pins. When the conditions are met, the controller begins soft-start. Once the output voltag e is within the proper window of operation, the controller asserts PGOOD.

ISL6313 INTERNAL CIRCUIT

POR

CIRCUIT

ENABLE COMPARATOR

EXTERNAL CIRCUIT

VCC

PVCC

+12V

10.7kΩ

1.40kΩ

1.2

1.0

(µF)

0.8

0.6

BOOT_CAP

0.4

0.2 20nC

0.0

FIGURE 11. BOOTSTRAP CAP ACIT ANCE vs BOOT RIPPLE

50nC

VOLTAGE

= 100nC

GATE

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0 ΔV

BOOT_CAP

(V)

0.85V

SOFT-START

AND

FAULT LOGIC

FIGURE 12. POWER SEQUENCING USING

THRESHOLD-SENSITIVE ENABLE (EN) FUNCTION

Enable and Disable

While in shutdown mode, the LGATE and UGATE signals are held low to assure the MOSFETs remain off. The following input conditions must be met (for both Intel and AMD modes of operation) before the ISL6313 is released

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ISL6313

from shutdown mode to begin the soft-start startup sequence:

1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the ISL6313 is guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6313 will not inadvertently turn off unless the bias voltage drops substantially (see “Electrical Specifications” on page 6).

2. The voltage on EN must be above 0.85V. The EN input allows for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6313 in shutdown until the voltage at EN rises above 0.85V . The enable comparator has 110mV of hysteresis to prevent bounce.

3. The driver bias voltage applied at the PVCC pin must reach the internal power-on reset (POR) rising threshold. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6313 will not inadvertently turn off unless the PVCC bias voltage drops substantially (see “Electrical Specifications” on page 6).

For Intel VR11 and AMD 6-bit modes of operation these are the only conditions that must be met for the controller to immediately begin the soft-start sequence. If running in AMD 5-bit mode of operation there is one more condition that must be met:

4. The VID code must not be 11111 in AMD 5-bit mode. This code signals the controller that no load is present. The controller will not allow soft-start to begin if this VID code is present on the VID pins.

Once all of these conditions are met the controller will begin the soft-start sequence and will ramp the output voltage up to the user designated level.

Intel Soft-Start

The soft-start function allows the converter to bring up the output voltage in a controlled fashion, resulting in a linear ramp-up. The soft-start sequence for the Intel modes of operation is slightly differ en t th en th e AMD soft-start sequence.

For the Intel VR11 mode of operation, the soft-start sequence if composed of four periods, as shown in Figure 13. Once the ISL6313 is released from shutdown and soft-start begins (as described in “Enable and Disable” on page 20), the controller will have a fixed delay period TD1 of typically 1.10ms. After this delay period, the VR will begin first soft-start ramp until the output voltage reaches 1.1V VBOOT voltage. Then, the controller will regulate the VR voltage at 1.1V for another fixed delay period t 93µs. At the end of t

period, ISL6313 will read the VID

signals. It is recommended that the VID codes be set no later then 50µs into pe ri o d t

. If the VID code is valid,

ISL6313 will initiate the second soft-start ramp until the

, of typically

output voltage reaches the VID voltage plus/minus any offset or droop voltage.

The soft-start time is the sum of the 4 periods as shown in Equation 19.

SStd1td2td3td4

During t

+++=

, 500mV/DIV

OUT

PGOOD

FIGURE 13. SOFT-START WAVEFORMS

and td4, ISL6313 digitally controls the DAC

500µs/DIV

td3t

(EQ. 19)

voltage change at 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor R soft-start ramp time t

on the SS pin. The second

and td4 can be calculated based on

Equations 20 and 21:

1.1 R⋅

d4VVID

For example, when VID is set to 1.5V and the R 100kΩ, the first soft-start ramp time t second soft-start ramp time t

8103–μs()⋅⋅=

1.1– RSS8103–μs()⋅⋅⋅=

will be 880µs and the

will be 320µs.

is set at

(EQ. 20)

(EQ. 21)

After the DAC voltage reaches the final VID setting, PGOOD will be set to high with the fixed delay t for t

is 93µs.

. The typical value

AMD Soft-Start

For the AMD 5-bit and 6-bit modes of operation, the soft-start sequence is composed of two periods, as shown in Figure 14. At the beginning of soft-start, the VID code is immediately obtained from the VID pins, followed by a fixed delay period t the ISL6313 will begin ramping the output voltage to the desired DAC level at a fixed rate of 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor R the SS pin. The amount of time required to ramp the output

of typically 1.10ms. After this delay period

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ISL6313

voltage to the final DAC voltage is referred to as tdB, and can be calculated as shown in Equation 22:

R⋅

tDB V

VID

8103–μs()⋅⋅=

(EQ. 22)

At the end of soft-start, PGOOD will immediately go high if the VSEN voltage is within the undervoltage and overvoltage limits.

, 500mV/DIV

OUT

PGOOD

500µs/DIV

FIGURE 14. SOFT-START WAVEFORMS

Pre-Biased Soft-Start

The ISL6313 also has the ability to start up into a pre-cha rged output, without causing any unnec essary disturbance. The FB pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both MOSFETs off. Once the internal ramping

the output drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage down to the DAC-set level.

Fault Monitoring and Protection

The ISL6313 actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common power good indicator is provided for linking to external system monitors. The schematic in Figure 16 outlines the interaction between the fault monitors and the power good signal.

AVG

VSEN

100µA

VDAC + RGND

1.260V

OCP

+175mV

+225mV

OCL

REPEAT FOR

EACH CHANNEL

OCP

SOFT-START, FAULT

AND CONTROL LOGIC

OVP

140µA

IOUT

OCP

PGOOD

OUTPUT PRECHARGED

ABOVE DAC LEVEL

OUTPUT PRECHARGED

BELOW DAC LEVEL

GND>

t2 t3

(0.5V/DIV)

OUT

EN (5V/DIV)

FIGURE 15. SOFT-ST ART WAVEFORMS FOR ISL6313-BASED

MULTI-PHASE CONVERTER

reference exceeds the FB pin potential, the output drives are enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the DAC setting. Should the output be pre-charged to a level exceeding the DAC setting,

-350mV

VDAC + RGND

ISL6313 INTERNAL CIRCUITRY

FIGURE 16. POWER GOOD AND PROTECTION CIRCUITRY

Power Good Signal

The power good pin (PGOOD) is an open-drain logic output that signals whether or not the ISL6313 is regulating the output voltage within the proper levels, and whether any fault conditions exist. This pin should be tied through a resistor to a voltage source that’s equal to or less then VCC.

For Intel mode of operation, PGOOD indicates whether VSEN is within specified overvoltage and undervoltage limit s after a fixed delay from the end of soft-start. PGOOD transitions low when an undervoltage, overvoltage, or overcurrent condition is detected or when the controller is disabled by a reset from EN, POR, or one of the no-CPU VID codes. In the event of an overvoltage or overcurrent condition, or a no-CPU VID code, the controller latches off and PGOOD will not return high until EN is toggled and a successful soft-start is

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ISL6313

completed. In the case of an undervoltage event, PGOOD will return high when the output voltage rises above the undervoltage hysteresis level. PGOOD is always low prior to the end of soft-start.

For AMD modes of operation, PGOOD will always be high as long as VSEN is within the specified undervoltage, overvoltage window and soft-start has ended. PGOOD only goes low if VSEN is outside this window. Even if the controller is shut down the PGOOD signal will still stay high until VSEN falls below the undervoltage threshold.

Overvoltage Protection

The ISL6313 constantly monitors the dif ference betwe en the V

SEN

and R

voltages to detect if an overvoltage event

GND

occurs. During soft-start, while the DAC is ramping up, the overvoltage trip level is the higher of a fixed voltage 1.260V or DAC + 175mV for Intel modes of operation and DAC + 225mV for AMD modes of operation. Upon successful soft-start, the overvoltage trip level is only DAC + 175mV or DAC + 225mV depending on whether the controller is running in Intel or AMD mode. When the output voltage rises above the OVP trip level actions are taken by the ISL6313 to protect the microprocessor load.

At the inception of an overvoltage event, L L

are commanded high and the PGOOD signal is

GATE2

GATE1

and

driven low. This turns on the all of the lower MOSFETs and pulls the output voltage below a level that might cause damage to the load. The L V

falls 100mV below the OVP threshold that tripped the

SEN

outputs remain high until

GATE

overvoltage protection circuitry. The ISL6313 will continue to protect the load in this fashion as long as the overvoltage condition recurs. Once an overvoltage condition ends the ISL6313 latches off, and must be reset by toggling EN, or through POR, before a soft-start can be reinitiated.

There is an OVP condition that exists that will not latch off the ISL6313. During a soft-start sequence, if the V

SEN

voltage is above the OVP threshold an overvoltage event will occur, but will be released once V threshold. If V

then rises above the OVP trip threshold a

SEN

falls 100mV below the OVP

SEN

second time, the ISL6313 will be latched off and cannot be restarted until the controller is reset.

Pre-POR Overvoltage Protection

Prior to P ISL6313 is designed to protect the load from any overvoltage events that may occur. This is accomplished by means of an internal 10kΩ resistor tied from PHASE to LGATE, which turns on the lower MOSFET to control the output voltage until the overvoltage event ceases or the input power supply cuts off. For complete protection, the low side MOSFET should have a gate threshold well below the maximum voltage rating of the load/microprocessor.

In the event that during normal operation the P voltage falls back below the POR threshold, the pre-POR

and VCC exceeding their POR levels, the

VCC

or VCC

overvoltage protection circuitry reactivates to protect from any more pre-POR overvoltage events.

Undervoltage Detection

The undervoltage threshold is set at DAC - 350mV of the VID code. When the output voltage (V

SEN

- R

GND

) is below the undervoltage threshold, PGOOD gets pulled low. No other action is taken by the controller. PGOOD will return high if the output voltage rises above DAC - 250mV.

Open Sense Line Prevention

In the case that either of the remote sense lines, VSEN or GND, become open, the ISL6313 is designed to prevent the controller from regulating. This is accomplished by means of a small 5µA pull-up current on VSEN, and a pull-down current on RGND. If the sense lines are opened at any time, the voltage difference between V

SEN

and R

GND

will increase until an overvoltage event occurs, at which point overvoltage protection activates and the controller stops regulating. The ISL6313 will be latched off and cannot be restarted until the controller is reset.

Overcurrent Protection

The ISL6313 takes advantage of the proportionality between the load current and the average current, I overcurrent condition. Two different methods of detecting overcurrent events are available on the ISL6313. The first method continually compares the average sense current with a constant 100µA OCP reference current as shown in Figure 16. Once the average sense current exceeds the OCP reference current, a comparator triggers the converter to begin overcurrent protection procedures.

For this first method the overcurrent trip threshold is dictated by the DCR of the inductors, the number of active channels, and the RSET pin resistor, R overcurrent trip level, I

OCP

. To calculate the

SET

, using this method use Equation 23, where N is the number of active channels, DCR is the individual inductor’s DCR, and R

SET

resistor value.

OCP

100 106–R

---------------------------------------------------------------

DCR 400⋅

SET

N3⋅⋅ ⋅⋅

During VID-on-the-fly transitions the overcurrent trip level for this method is boosted to prevent false overcurrent trip events that can occur. Starting from the beginning of a dynamic VID transition, the overcurrent trip level is boosted to 140µA. The OCP level will stay at this boosted level until 50µs after the end of the dynamic VID transition, at which point it will return to the typical 100µA trip level.

The second method for detecting overcurrent events continuously compares the voltage on the IOUT pin, V to the overcurrent protection voltage, V Figure 16. The average channel sense current flows out the IOUT pin and through R

, creating the IOUT pin voltage

IOUT

which is proportional to the output current. When the IOUT

, to detect an

AVG

is the RSET pin

, as shown in

OCP

(EQ. 23)

IOUT

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ISL6313

pin voltage exceeds the V

voltage of 2.0V, the

OCP

overcurrent protection circuitry activates. Since the IOUT pin voltage is proportional to the output current, the overcurrent trip level, I R

, as shown in Equation 24.

IOUT

OCP

, can be set by selecting the proper value for

OCP

---------------------------------------------------

DCR R

SET

IOUT

N⋅⋅

400⋅⋅

(EQ. 24)

Once the output current exceeds the overcurrent trip level, V

will exceed V

IOUT

and a comparator will trigger the

OCP

converter to begin overcurrent protection procedures. At the beginning of an overcurrent shutdown, the controller

turns off both upper and lower MOSFETs and lowers PGOOD. The controller will then immediately attempt to softstart. If the overcurrent fault remains, the trip-retry cycles will continue until either the controller is disabled or the fault is cleared. If five overcurrent events occur without successfully completing soft-start, the controller will latch off after the fifth try and must be reset by toggling EN before a soft-start can be reinitiated. Note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard.

OUTPUT CURRENT, 50A/DIV

OUTPUT VOLTAGE, 500mV/DIV

FIGURE 17. OVERCURRENT BEHAVIOR IN HICCUP MODE

Individual Channel Overcurrent Limiting

The ISL6313 has the ability to limit the current in each individual channel without shutting down the entire regulator. This is accomplished by continuously comparing the sensed currents of each channel with a constant 140µA OCL reference current as shown in Figure 17. If a channel’s individual sensed current exceeds this OCL limit, the UGATE signal of that channel is immediately forced low, and the LGATE signal is forced high. This turns off the upper MOSFET(s), turns on the lower MOSFET(s), and stops the rise of current in that channel, forcing the current in the channel to decrease. That channel’s UGATE signal will not be able to return high until the sensed channel current falls back below the 140µA reference.

During VID-on-the-fly transitions the OCL trip level is boosted to prevent false overcurrent limiting events that can occur. Starting from the beginning of a dynamic VID transition, the overcurrent trip level is boosted to 196µA. The OCL level will stay at this boosted level until 50µs after the end of the dynamic VID transition, at which point it will return to the typical 140µA trip level.

General Design Guide

This design guide is intended to provide a high-level explanation of the steps necessary to create a multi-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications.

Power Stages

The first step in designing a multi-phase converter is to determine the number of phases. This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. Generally speaking, the most economical solutions are those in which each phase handles between 25A and 30A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFET s and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heat-dissipating surfaces.

MOSFETS

The choice of MOSFETs depends on the current each MOSFET will be required to conduct, the switching frequency , the capability of the MOSFETs to dissipate heat, and the availability and nature of heat sinking and air flow .

LOWER MOSFET POWER CALCULATION

The calculation for power loss in the lower MOSFET is simple, since virtually all of the loss in the lower MOSFET is due to current conducted through the channel resistance (r output current, I Equation 1), and d is the duty cycle (V

An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the

). In Equation 25, IM is the maximum continuous

DS(ON)

LOW 1()rDS ON()

is the peak-to-peak inductor current (see

P-P

OUT/VIN

⎛⎞

⎜⎟

----- N

⎝⎠

LP-P()

----------------------------------------+⋅=

1d–()⋅

(EQ. 25)

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September 2, 2008

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ISL6313

lower-MOSFET body diode. This term is dependent on the diode forward voltage at I f

, and the length of dead times, td1 and td2, at the beginning

, V

, the switching frequency,

D(ON)

and the end of the lower-MOSFET conduction interval respectively.

LOW 2()VDON()fS

⎛⎞

⋅⋅=

⎜⎟

------

-----------+

⎝⎠

P-P

⎛⎞

⎜⎟

td1⋅

------

–

⎜⎟

⎝⎠

P-P

-----------

td2⋅+

(EQ. 26)

The total maximum power dissipated in each lower MOSFET is approximated by the summation of P

LOW(1)

and P

LOW(2)

UPPER MOSFET POWER CALCULATION

In addition to r

losses, a large portion of the

DS(ON)

upper-MOSFET losses are due to currents conducted across the input voltage (V

) during switching. Since a substantially

higher portion of the upper-MOSFET losses are dependent on switching frequency , the po wer ca lculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times, the lower-MOSFET body-diode reverse-recovery charge, Q and the upper MOSFET r

conduction loss.

DS(ON)

When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 27, the required time for this commutation is t approximated associated power loss is P

UP 1()VIN

⎛⎞

⋅⋅⋅≈

----- -

⎝⎠

----------+

P-P

⎛⎞

----

⎜⎟

⎝⎠

and the

UP(1).

(EQ. 27)

At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t approximate power loss is P

⎛⎞

P-P

UP 2()VIN

⋅⋅⋅≈

----------

⎜⎟

–

----- 2

⎝⎠

. In Equation 28, the

UP(2).

⎛⎞

----

⎜⎟

⎝⎠

(EQ. 28)

A third component involves the lower MOSFET reverse-recovery charge, Q

. Since the inductor current has

fully commutated to the upper MOSFET before the lower-MOSFET body diode can recover all of Q

, it is

conducted through the upper MOSFET across VIN. The power dissipated as a result is P

UP 3()VINQrrfS

⋅⋅=

UP(3)

(EQ. 29)

Finally, the resistive part of the upper MOSFET is given in Equation 30 as P

UP 4()rDS ON()

UP(4).

⎛⎞

⎜⎟

----- N

⎝⎠

P-P

+⋅⋅≈

---------12

(EQ. 30)

The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 27, 28, 29 and 30. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies.

Package Power Dissipation

When choosing MOSFETs it is important to consider the

amount of power being dissipated in the integrated drivers located in the controller. Since there are a total of three drivers in the controller package, the total power dissipated by all three drivers must be less than the maximum allowable power dissipation for the QFN package.

Calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125°C. The maximum allowable IC power dissipation for the 6x6 QFN package is approximately 3.5W at room temperature. See “Layout Considerations” on page 31 for thermal transfer improvement suggestions.

When designing the ISL6313 into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses, P

Qg_TOT

, due to the gate charge of MOSFETs and the integrated driver’s internal circuitry and their corresponding average driver current can be estimated with Equations 31 and 32, respectively .

Qg_TOTPQg_Q1PQg_Q2IQ

Qg_Q1

Qg_Q2QG2

-- -

⎛⎞

-- -

⋅ QG2NQ2⋅+

⎝⎠

In Equations 31 and 32, P power loss and P loss; the gate charge (Q

PVCC FSWNQ1N

⋅⋅ ⋅⋅⋅=

PVCC FSWNQ2N

⋅⋅⋅⋅=

N⋅

Qg_Q1

is the total lower gate drive power

Qg_Q2

and QG2) is defined at the

VCC⋅++=

PHASE

PHASEFSWIQ

(EQ. 31)

(EQ. 32)

+⋅⋅=

is the total upper gate drive

particular gate to source drive voltage PVCC in the corresponding MOSFET data sheet; I quiescent current with no load at both drive outputs; N N

are the number of upper and lower MOSFETs per phase,

respectively; N I

VCC product is the quiescent power of the controller

is the number of active phases. The

PHASE

is the driver total

and

without capacitive load and is typically 75mW at 300kHz.

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September 2, 2008

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ISL6313

PVCC

BOOT

PHASE

HI1

LO1

UGATE

GI1R

FIGURE 18. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

PVCC

HI2

LO2

LGATE

GI2

FIGURE 19. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path resistance, P P

, and in the boot strap diode, P

DR_UP

power will be dissipated by the external gate resistors (R and R

) and the internal gate resistors (R

, the lower drive path resistance,

DR_UP

BOOT

. The rest of the

and R

GI1

GI2

) of the MOSFETs. Figures 18 and 19 show the typical upper and lower gate drives turn-on transition path. The total power dissipation in the controller itself, P

, can be roughly

estimated as Equation 33:

DRPDR_UPPDR_LOW PBOOTIQ

VCC⋅()+++=

(EQ. 33)

Inductor DCR Current Sensing Component Selection

The ISL6313 senses each individual channel’s inductor current by detecting the voltage across the output inductor DCR of that channel (As described in the “Continuous Current Sensing” on page 12). As Figure 20 illustrates, an R-C network is required to accurately sense the inductor DCR voltage and convert this information into a current, which is proportional to the total output current. The time constant of this R-C network must match the time constant of the inductor L/DCR.

Follow the steps below to choose the component values for this RC network.

1. Choose an arbitrary value for C value is 0.1µF.

2. Plug the inductor L and DCR component values, and the value for C1 chosen in step 1 into Equation 34, to calculate the value for R1.

⋅

DCR C

-------------------------

Once the R-C network components have been chosen, the effective internal R R

resistance sets the gain of the load line regulation

ISEN

resistance must then be set. The

ISEN

loop as well as the gain of the channel-current balance loop and the overcurrent trip level. The effective internal R resistance is set through a single resistor on the RSET pin, R

SET

UGATE

MOSFET

DRIVER

LGATE

ISL6313 INTERNAL

CIRCUIT

. The recommended

INDUCTOR

VL(s)

VC(s)

DCR

(EQ. 34)

ISEN

OUT

BOOT

DR_UP

DR_LOW

EXT1RG1

Qg_Q1

---------------------

⎛⎞

HI1

--------------------------------------

⎜⎟

⎝⎠

HI1REXT1

⎛⎞

HI2

--------------------------------------

⎜⎟

⎝⎠

HI2REXT2

GI1

-------------

+= R

LO1

----------------------------------------

LO1REXT1

LO2

----------------------------------------

LO2REXT2

EXT2RG2

Qg_Q1

---------------------

⋅=

Qg_Q2

---------------------

⋅=

GI2

-------------

SENSE

SEN

VC(s)

ISEN

ISEN-

ISEN+

RSET

SET

VCC

FIGURE 20. DCR SENSING CONFIGURATION

Use Equation 35 to calculate the value of R

SET

. In this equation, DCR is the DCR of the output inductor at room temperature, I

is the desired overcurrent trip level, and

OCP

N is the number of phases. It is recommended that the

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September 2, 2008

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ISL6313

desired overcurrent trip level, I

, be chosen so that it’s

OCP

30% larger then the maximum load current expected.

SET

*Note: R

DCR

----------------------------

100 10

SET

6–

must be between 20kΩ and 80kΩ

OCP

------------- -

⋅⋅=

400

--------- -

(EQ. 35)

Due to errors in the inductance or DCR it may be necessary to adjust the value of R

to match the time constants

correctly. The ef fects of time constant mismatch can be seen in the form of droop overshoot or undershoot during the initial load transient spike, as shown in Figure 21. Follow the steps below to ensure the R-C and inductor L/DCR time constants are matched accurately.

1. Capture a transient event with the oscil l o scope set to about L/DCR/2 (sec/div). For example, with L = 1µH and DCR = 1mΩ, set the oscilloscope to 500µs/div.

2. Record ΔV1 and ΔV2 as shown in Figure 21.

3. Select new values, R resistor based on the original value, R

, for the time constant

1(NEW)

1(OLD)

, using

Equation 36.

1NEW()R1OLD()

4. Replace R

with the new value and check to see that the

⋅=

V1Δ

----------

(EQ. 36)

error is corrected. Repeat the procedure if necessary.

DROOP

------------------------ -= I

(EQ. 37)

Based on the desired loadline, the loadline regulation resistor, R

*Note: RFB must be not exceed 4.0kΩ

, can be calculated from Equation 38.

RLLNR

⋅⋅

---------------------------------------

DCR

SET

⋅=

--------- -

400

(EQ. 38)

In Equation 38, RLL is the loadline resistance; N is the number of active channels; DCR is the DCR of the individual output inductors; and R

is the RSET pin resistor.

SET

If no loadline regulation is required, the resistor on the FS pin, R

, should be connected to the VCC pin. To c ho os e t he

value for R

in this situation, please refer to “Compensation

without load-line regulation” on page 28.

IOUT Pin Resistor

A copy of the average sense current flows out of the IOUT pin, and a resistor, R be used to set the overcurrent protection trip level. Based on the desired overcurrent trip threshold, I resistor, R

IOUT

, can be calculated from Equation 39.

IOUT

SET

--------------------------------

⋅

DCR I

OCP

, placed from this pin to ground can

IOUT

, the IOUT pin

OCP

N⋅

--------- -

⋅=

400

(EQ. 39)R

ΔV

FIGURE 21. TIME CONSTANT MISMATCH BEHAVIOR

OUT

TRAN

ΔI

Loadline Regulation Resistor

If loadline regulation is desired, the resistor on the FS pin, R

, should be connected to Ground in order for the internal

average sense current to flow out across the loadline regulation resistor, labeled R value sets the desired loadline required for the application. The desired loadline, R where V current I

DROOP FL.

is the desired droop voltage at the full load

in Figure 7. This resistor’s

, can be calculated by Equation 37

APA Pin Component Selection

A 100µA current flows into the APA pin and across R set the APA trip level. A 1000pF capacitor, C also be placed across the R immunity. Use Equation 40 to set R

resistor to help with noise

APA

to get the desired

APA

, should

APA trip level. An APA trip level of 500mV is recommended for most applications.

APA

APA TRIP()

---------------------------------

100 106–×

500mV

---------------------------- -

100 106–×

5kΩ===

APA

(EQ. 40)

Compensation

The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals.

COMPENSATION WITH LOAD-LINE REGULATION

The load-line regulated converter behaves in a similar manner to a peak current mode controller because the two poles at the output filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, R

and CC.

FN6448.2

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ISL6313

C2 (OPTIONAL)

Case 1:

COMP

ISL6313

------------------------------- -f 2 π LC⋅⋅⋅

CRFB

2 π f0V

----------------------------------------------------------

⋅=

------------------------------------------------------= 2 π V

⋅⋅ ⋅ ⋅

P-PRFBf0

LC⋅⋅⋅ ⋅ ⋅

P-P

VSEN

FIGURE 22. COMPENSATION CONFIGURA TION FOR

LOAD-LINE REGULATED ISL6313 CIRCUIT

Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately, there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator, by compensating the L-C poles and the ESR zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance.

Select a target bandwidth for the compensated system, f

The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. The values of the compensation components depend on the relationships of f to the L-C pole frequency and the ESR zero frequency. For each of the following three, there is a separate set of equations for the compensation components.

In Equation 41, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent series resistance of the bulk output filter capacitance; and V

P-P

is the peak-to-peak sawtooth signal amplitude as described in the “Electrical Specifications” on page 6.

Once selected, the compensation values in Equation 41 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to R value of R

while observing the transient performance on an

. Slowly increase the

oscilloscope until no further improvement is noted. Normally, C

will not need adjustment. Keep the value of CC from

Equation 41 unless some performance issue is noted. The optional capacitor C

, is sometimes needed to bypass

noise away from the PWM comparator (see Figure 22). Keep a position available for C

, and be prepared to install a

high-frequency capacitor of between 22pF and 150pF in case any leading edge jitter problem is noted.

Case 2:

Case 3:

------------------------------- 2 π LC⋅⋅⋅

CRFB

-------------------------------------------------------------------------------------- -=

2 π⋅()2f

------------------------------------->

2 π C ESR⋅⋅⋅

CRFB

P-P

----------------------------------------------------------------- -

⋅=

VINESR C⋅⋅

----------------------------------------------------------------- -= 2 π V

-------------------------------------<≤ 2 π C ESR⋅⋅⋅

2 π⋅()⋅

2 π f0V

----------------------------------------------

P-PRFBf0

P-PRFB

ESR⋅

P-P

LC⋅⋅⋅

LC⋅⋅⋅ ⋅ ⋅

L⋅⋅ ⋅ ⋅

L⋅⋅ ⋅ ⋅ ⋅

(EQ. 41)

COMPENSATION WITHOUT LOAD-LINE REGULATION

The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type III controller, as shown in Figure 23, provides the necessary compensation.

FIGURE 23. COMPENSATION CIRCUIT WITHOUT LOAD-LINE

REGULATION

The first step, is to choose the desired bandwidth, f

COMP

VSEN

ISL6313

, of the

compensated system. Choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. The type-III compensator has an extra high-frequency pole, f

. This pole can be used for

added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. A

FN6448.2

September 2, 2008

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ISL6313

good general rule is to choose fHF= 10f0, but it can be higher if desired. Choosing f

to be lower than 10f0 can

cause problems with too much phase shift below the system bandwidth.

CESR⋅

--------------------------------------------

R1R

⋅=

LC⋅ C ESR⋅–

--------------------------------------------= R

-----------------------------------------------------------------------------------------------------=

2 π⋅()2f0f

⋅⋅ ⋅ ⋅ ⋅

⎛⎞

2π

⋅

P-P

⎝⎠

------------------------------------------------------------------------------------------= V

VIN2 π f

-----------------------------------------------------------------------------------------------------=

2 π⋅()

⋅⋅ ⋅ ⋅ ⋅

f0fHFLCR

⋅⋅ ⋅⋅⋅

2 π f

f0f

LC⋅()RFBV

LC⋅ 1–⋅⋅ ⋅()⋅

LC⋅()RFBV

P-P

(EQ. 42)

P-P

In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in Equation 41, R

is selected arbitrarily. The remaining

compensation components are then selected in Equation 42. In Equation 42, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and V

P-P

is the peak-to-peak sawtooth signal amplitude as described in the Electrical Specifications on page 6.

Output Filter Design

The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. The output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand.

In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ΔI, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, ΔV Capacitors are characterized according to their capacita nce, ESR, and ESL (equivalent series inductance).

At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will

MAX

initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output-voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount as shown in Equation 43.

ΔVESL

-----

⋅ ESR ΔI⋅+≈

(EQ. 43)

The filter capacitor must have sufficiently low ESL and ESR so that ΔV < ΔV

MAX

Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation.

The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current (see “Interleaving” on page 10 and Equation 2), a voltage develops across the bulk capacitor ESR equal to I

(ESR). Thus, once the output

C(P-P)

capacitors are selected, the maximum allowable ripple voltage, V

P-P(MAX)

, determines the lower limit on the

inductance as shown in Equation 44.

⎛⎞

NV⋅

–

⎝⎠

------------------------------------------------------------------- -

ESR

⋅≥

⋅⋅

SVINVP-P MAX()

OUT

⋅

OUT

(EQ. 44)

Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ΔV

. This places an upper limit on inductance.

MAX

Equation 45 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. Equation 46 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels.

2NCV

⋅⋅⋅

---------------------------------

()

ΔI

ΔV

MAX

ΔIESR⋅()–⋅≤

(EQ. 45)

FN6448.2

September 2, 2008

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ISL6313

NC⋅⋅

1.25

-----------------------------

()

ΔI

ΔV

⋅⋅≤

ΔI ESR⋅()– VINVO–

MAX

⎛⎞ ⎝⎠

(EQ. 46)

Switching Frequency

There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper MOSFET loss calculation. These effects are outlined in “MOSFETs” on page 24, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small output-voltage ripple. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements.

Switching frequency is determined by the selection of the frequency-setting resistor, R are provided to assist in selecting the correct value for R

[]

10.61 1.035 fS()log⋅()–

500

100

(kΩ)

50 100 1k 2k

SWITCHING FREQUENCY (kHz)

FIGURE 24. R

. Figure 24 and Equation 47

vs SWITCHING FREQUENCY

(EQ. 47)

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases.

For a two-phase design, use Figure 25 to determine the input-capacitor RMS current requirement set by the duty cycle, maximum sustained output current (I of the peak-to-peak inductor current (I

L(P-P)

) to IO.

), and the ratio

0.3

)

RMS/

0.2

0.1

= 0

L(P-P)

= 0.5 I

L(P-P)

INPUT-CAPACITOR CURRENT (I

L(P-P)

00.4 1.00.2 0.6 0.8

= 0.75 I

DUTY CYCLE (V

IN/VO

)

FIGURE 25. NORMALIZED INPUT-CAP ACITOR RMS

CURRENT FOR 2-PHASE CONVERTER

Select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25x greater than the maximum input voltage. Figure 26 provides the same input RMS current information for single-phase designs. Use the same approach for selecting the bulk capacitor type and number.

0.6

)

RMS

0.4

0.2

= 0

L(P-P)

= 0.5 I

L(P-P)

INPUT-CAPACITOR CURRENT (I

00.4 1.00.2 0.6 0.8

L(P-P)

= 0.75 I

DUTY CYCLE (V

IN/VO

)

FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR SINGLE-PHASE CONVERTER

Low capacitance, high-frequency ceramic cap acitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spike s. The spikes result from the high current slew rate produced by the upper MOSFET turn on and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitics and maximize suppression.

FN6448.2

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ISL6313

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. Careful component selection, layout, and placement minimizes these voltage spikes. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying channel current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes.

There are two sets of critical components in a DC/DC converter using a ISL6313 controller. The power components are the most critical because they switch large amounts of energy. Next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling.

The power components should be placed first, which include the MOSFET s, input and output capacitors, and the inductors. It is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. Symmetrical layout allows heat to be dissipated equally across all power trains. Equidistant placement of the controller to the power trains it controls through the integrated drivers helps keep the gate drive traces equally short, resulting in equal trace impedances and similar drive capability of all set s of MOSFETs.

When placing the MOSFETs try to keep the source of the upper FETs and the drain of the lower FETs as close as thermally possible. Input Bulk capacitors should be placed close to the drain of the upper FETs and the source of the lower FETs. Locate the output inductors and output capacitors between the MOSFET s and the load. The high-frequency input and output decoupling capacitors (ceramic) should be placed as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to GND next or on the capacitor solder pad.

The critical small components include the bypass capacitors for VCC and PVCC, and many of the components surrounding the controller including the feedback network and current sense components. Locate the VCC/PVCC bypass capacitors as close to the ISL6313 as possible. It is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to EMI pick-up.

A multi-layer printed circuit board is recommended. Figure 27 shows the connections of the critical components for the converter. Note that capacitors C each represent numerous physical capacitors. Dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer.

Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to output inductors short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring.

xx(IN)

and C

xx(OUT)

could

Routing UGATE, LGATE, and PHASE Traces

Great attention should be paid to routing the UGATE, LGATE, and PHASE traces since they drive the power train MOSFETs using short, high current pulses. It is important to size them as large and as short as possible to reduce their overall impedance and inductance. They should be sized to carry at least one ampere of current (0.02” t o 0 . 0 5 ” ) . G o i n g between layers with vias should also be avoided, but if so, use two vias for interconnection when possible.

Extra care should be given to the LGATE traces in particular since keeping their impedance and inductance lo w helps to significantly reduce the possibility of shoot-through. It is also important to route each channels UGATE and PHASE traces in as close proximity as possible to reduce their inductances.

Current Sense Component Placement and Trace Routing

One of the most critical aspects of the ISL6313 regulator layout is the placement of the inductor DCR current sense components and traces. The R-C current sense components must be placed as close to their respective ISEN+ and ISEN- pins on the ISL6313 as possible.

The sense traces that connect the R-C sense components to each side of the output inductors should be routed on the bottom of the board, away from the noisy switching components located on the top of the board. These traces should be routed side by side, and they should be very thin traces. It’s important to route these traces as far away from any other noisy traces or planes as possible. These traces should pick up as little noise as possible.

Thermal Management

For maximum thermal performance in high current, high switching frequency applications, connecting the thermal GND pad of the ISL6313 to the ground plane with multiple vias is recommended. This heat spreading allows the part to achieve its full thermal potential. It is also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part.

FN6448.2

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ISL6313

(CF1)

DVC

KEY

HEAVY TRACE ON CIRCUIT PLANE LAYER

+5V

COMP

APA

VCC

OFS

FS REF

REF

DVC VSEN

RGND

RSET

BOOT1

UGATE1

PHASE1

LGATE1

ISEN1ISEN1+

+5V VCC

BOOT1

SET

LOCATE CLOSE TO IC

(MINIMIZE CONNECTION PATH)

+12V

BIN1

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

LOCATE NEAR SWITCHING TRANSISTORS;

(MINIMIZE CONNECTION PATH)

)

PATH)

BOUT

LOAD

IOUT

VID7 VID6

VID5

VID4 VID3 VID2 VID1 VID0

VRSEL

PGOOD

IOUT

GND

ISL6313

PVCC

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2ISEN2+

(CF2)

BOOT2

+12V

BIN2

HFOUT

LOCATE NEAR LOAD;

(MINIMIZE CONNECTION

FIGURE 27. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6448.2

September 2, 2008

Page 33

Package Outline Drawing

L36.6x6

36 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 08/08

ISL6313

PIN 1

INDEX AREA

(4X)

( 5.65 )

( 4.15)

Exp. Dap.

0.15

6.00

TOP VIEW

( 5.65 )

( 4.15)

Exp. Dap.

6.00

( 32x 0.50)

4X 4.00

36X 0.55 ± 0.10

Max 0.80

32x 0.50

BOTTOM VIEW

SIDE VIEW

36X 0.25 +0.05/-.07

PIN #1 INDEX AREA

0.10

4.15 +0.10/-0.15

SEE DETAIL "X"

0.10

0.08

( 4X 4.00)

TYPICAL RECOMMENDED LAND PATTERN

(36X .25)

(36X 0.75)

0 . 2 REF

DETAIL "X"

0 . 00 MIN. 0 . 05 MAX.

Dimensions are in millimeters.1.

Dimensioning and tolerancing conform to AMSEY14.5m-1994.

2. Unless otherwise specified, tolerance : Decimal ± 0.05

3. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.

FN6448.2

September 2, 2008