Datasheet isl6312 Datasheets

ISL6312

Data Sheet

Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10, VR11, and AMD Applications

The ISL6312 four-phase PWM control IC provides a precision voltage regulation system for advanced microprocessors. The integration of power MOSFET drivers into the controller IC marks a departure from the separate PWM controller and driver configuration of previous multiphase product families. By reducing the number of external parts, this integration is optimized for a cost and space saving power management solution.

One outstanding feature of this controller IC is its multi-processor compatibility, allowing it to work with both Intel and AMD microprocessors. Included are programmable VID codes for Intel VR10, VR11, as well as AMD DAC t ables. A unity gain, differential amplifier is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. The output voltage can also be positively or negatively offset through the use of a single external resistor.

The ISL6312 also includes advanced control loop features for optimal transient response to load apply and removal. One of these features is highly accurate, fully differential, continuous DCR current sensing for load line programming and channel current balance. Active Pulse Positioning (APP) modulation is another unique feature, allowing for quicker initial response to high di/dt load transients.

This controller also allows the user the flexibility to choose between PHASE detect or LGATE detect adaptive dead time schemes. This ability allows the ISL6312 to be used in a multitude of applications where either scheme is required.

Protection features of this controller IC include a set of sophisticated overvoltage, undervoltage, and overcurrent protection. Furthermore, the ISL6312 includes protection against an open circuit on the remote sensing inputs. Combined, these features provide advanced protection for the microprocessor and power system.

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Features

• Integrated Multiphase Power Conversion

- 2- or 3-Phase Operation with Internal Drivers

- 4-Phase Operation with External PWM Driver Signal

• Precision Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over-Temperature

- Adjustable Reference-Voltage Offset

• Optimal Transient Response

- Active Pulse Positioning (APP) Modulation

- Adaptive Phase Alignment (APA)

• Fully Differential, Continuous DCR Current Sensing

- Accurate Load Line Programming

- Precision Channel Current Balancing

• User Selectable Adaptive Dead Time Scheme

- PHASE Detect or LGATE Detect for Application Flexibility

• Variable Gate Drive Bias: 5V to 12V

• Multi-Processor Compatible

- Intel VR10 and VR11 Modes of Operation

- AMD Mode of Operation

• Microprocessor Voltage Identification Inputs

-8-bit DAC

- Selectable between Intel’s Extended VR10, VR11, AMD 5-bit, and AMD 6-bit DAC Tables

- Dynamic VID Technology

• Overcurrent Protection

• Multi-Tiered Overvoltage Protection

• Digital Soft-Start

• Selectable Operation Frequency up to 1.5MHz Per Phase

• Pb-Free Plus Anneal Available (RoHS Compliant)

Ordering Information

PART

NUMBER

(Note)

ISL6312CRZ* ISL6312 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 ISL6312IRZ* ISL6312 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% m atte tin plate termination finish, which are RoHS compliant and comp atible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temper ature s that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

PART

MARKING

TEMP.

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG . #

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Pinout

ISL6312ISL6312

ISL6312

(48 LD QFN)

TOP VIEW

VID6

VID7

VID5

47 46 45 44 43 42 41 40 39

ISEN3-

ISEN3+

PVCC3

LGATE3

PHASE3

UGATE3

PGOOD

38 37

BOOT3

VID4

VID3

VID2

VID1

VID0

5 VRSEL DRSEL

OVPSEL

VCC

REF OFS

10 11 12

13 14 15 16 17 18 19 20 21 22

COMP

VDIFF

IDROOP

ISL6312 Integrated Driver Block Diagram

RGND

GND

VSEN

ISEN2+

ISEN2-

ISEN1+

ISEN1-

PHASE1

UGATE1

BOOT1

LGATE1

PVCC1_2

LGATE2

BOOT2

UGATE2

PHASE2

23 24

ISEN4-

ISEN4+

PWM4

EN_PH4

DRSEL

PWM

SOFT-START

AND

FAULT LOGIC

PVCC

BOOT

UGATE

20kΩ

GATE

CONTROL

LOGIC

SHOOT-

THROUGH

PROTECTION

10kΩ

PHASE

LGATE

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Block Diagram

VSEN

RGND

VDIFF

UNDERVOLTAGE

LINE PREVENTION

DETECTION

LOGIC

OPEN SENSE

ISL6312ISL6312

PGOOD

SOFT-START

AND

FAULT LOGIC

0.85V

POWER-ON

RESET

VCC

PVCC1_2

BOOT1

OVPSEL

VRSEL

VID7 VID6

VID5 VID4 VID3 VID2 VID1 VID0

REF

COMP

OFS

IDROOP

OVERVOLTAGE

DETECTION

MODE/DAC

SELECT

DYNAMIC

VID D/A

OFFSET

LOGIC

E/A

I_TRIP

I_AVG

LOAD APPL Y

TRANSIENT

ENHANCEMENT

CLOCK AND

MODULATOR

WAVEFORM

GENERAT OR

∑

CHANNEL CURRENT BALANCE

0.2V

I_AVG

MOSFET

DRIVER

CHANNEL

DETECT

MOSFET

DRIVER

PH4 POR/

MOSFET

DRIVER

DETECT

PWM1

PWM2

PWM3

PWM4

1 N

UGATE1

PHASE1

LGATE1

DRSEL

BOOT2

UGATE2

PHASE2

LGATE2

EN_PH4

PVCC3

BOOT3 UGATE3

PHASE3

LGATE3

CURRENT

ISEN1-

CH1

SENSE

ISEN1+

CURRENT

SENSE

ISEN2-

CH2

ISEN2+

CURRENT

SENSE

ISEN3-

CH3

ISEN3+

∑

CURRENT

SENSE

ISEN4-

CH4

ISEN4+

GND

PWM4

SIGNAL

LOGIC

PWM4

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Typical Application - ISL6312 (4-Phase)

ISL6312ISL6312

+5V

COMP

VSEN RGND

VCC

OFS

FS REF

OVPSEL

IDROOP

VDIFF

ISL6312

BOOT1

UGATE1

PHASE1

LGATE1

ISEN1ISEN1+

PVCC1_2

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2ISEN2+

+12V

LOAD

+12V

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

VRSEL

PGOOD

DRSEL

GND

PVCC3

BOOT3

UGATE3

PHASE3

LGATE3

ISEN3ISEN3+

EN_PH4

PWM4

ISEN4ISEN4+

+12V

BOOT

VCC PVCC

ISL6612

PWM

+12V

UGATE PHASE

LGATE

GND

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Typical Application - ISL6312 with NTC Thermal Compensation (4-Phase)

+5V

COMP

VSEN RGND

VCC

OFS

FS REF

OVPSEL

IDROOP

ISL6312

VDIFF

BOOT1

UGATE1

PHASE1

LGATE1

PVCC1_2

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2+

ISEN1ISEN1+

ISEN2-

+12V

NTC

PLACE IN CLOSE PROXIMITY

LOAD

+12V

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

VRSEL PGOOD

DRSEL

GND

PVCC3

BOOT3

UGATE3

PHASE3

LGATE3

ISEN3-

ISEN3+

EN_PH4

PWM4

ISEN4-

ISEN4+

+12V

BOOT

VCC PVCC

ISL6612

PWM

+12V

UGATE PHASE

LGATE

GND

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Absolute Maximum Ratings

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V

BOOT Voltage, V BOOT to PHASE Voltage, V

PHASE Voltage, V

GND - 8V (<400ns, 20µJ) to 24V (<200ns, V

UGATE Voltage, V

PHASE

LGATE Voltage, V

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC + 0.3V

Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

. . . . . . . . . . . . . .GND - 0.3V to GND + 36V

BOOT

BOOT-PHASE

. . . . . . . GND - 0.3V to 15V (PVCC = 12)

PHASE

. . . . . . . .V

UGATE

- 3.5V (<100ns Pulse Width, 2µJ) to V

. . . . . . . . . . . GND - 0.3V to PVCC + 0.3V

LGATE

. . . . . . -0.3V to 15V (DC)

-0.3V to 16V (<10ns, 10µJ)

BOOT - PHASE

- 0.3V to V

PHASE

BOOT BOOT

= 12V) + 0.3V + 0.3V

Thermal Information

Thermal Resistance θJA (°C/W) θJC (°C/W)

QFN Package (Notes 1, 2). . . . . . . . . . 32 3.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .+5V to 12V ±5%

Ambient Temperature (ISL6312CRZ) . . . . . . . . . . . . . 0°C to +70°C

Ambient Temperature (ISL6312IRZ) . . . . . . . . . . . . .-40°C to +85°C

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

Tech Brief TB379.

2. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

3. Limits established by characterization and are not production tested.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

BIAS SUPPLIES

Input Bias Supply Current I Gate Drive Bias Current - PVCC1_2 Pin I Gate Drive Bias Current - PVCC3 Pin I VCC POR (Power-On Reset) Threshold VCC rising 4.25 4.38 4.50 V

PVCC POR (Power-On Reset) Threshold PVCC rising 4.25 4.38 4.50 V

PWM MODULATOR

Oscillator Frequency Accuracy, f

Adjustment Range of Switching Frequency (Note 3) 0.08 - 1.0 MHz Oscillator Ramp Amplitude, V

CONTROL THRESHOLDS

EN Rising Threshold -0.85-V EN Hysteresis -110-mV EN_PH4 Rising Threshold 1.160 1.210 1.250 V EN_PH4 Falling Threshold 1.00 1.06 1.10 V COMP Shutdown Threshold COMP falling 0.1 0.2 0.3 V

REFERENCE AND DAC

System Accuracy (1.000V - 1.600V) -0.5 - 0.5 % System Accuracy (0.600V - 1.000V) -1.0 - 1.0 % System Accuracy (0.375V - 0.600V) -2.0 - 2.0 % DAC Input Low Voltage (VR10, VR11) - - 0.4 V DAC Input High Voltage (VR10, VR11) 0.8 - - V

; EN = high 15 20 25 mA

VCC PVCC1_2 PVCC3

; EN = high 2 4.3 6 mA

; EN = high 1 2.1 3 mA

VCC falling 3.75 3.88 4.00 V

PVCC falling 3.60 3.88 4.00 V

RT = 100kΩ (± 0.1%) 225 250 275 kHz

(Note 3) - 1.50 - V

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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DAC Input Low Voltage (AMD) --0.6V DAC Input High Voltage (AMD) 1.0 - - V

PIN-ADJUSTABLE OFFSET

OFS Sink Current Accuracy (Negative Offset) R OFS Source Current Accuracy (Positive Offset) R

ERROR AMPLIFIER

DC Gain R Gain-Bandwidth Product C Slew Rate CL = 100pF, Load = ±400mA, (Note 3) - 8 - V/μs Maximum Output Voltage Load = 1mA 3.90 4.20 - V Minimum Output Voltage Load = -1mA - 1.30 1.5 V

SOFT-START RAMP

Soft-Start Ramp Rate VR10/VR11, R

Adjustment Range of Soft-Start Ramp Rate (Note 3) 0.625 - 6.25 mV/µs

PWM OUTPUT

PWM Output Voltage LOW Threshold Iload = ±500µA - - 0.5 V PWM Output Voltage HIGH Threshold Iload = ±500µA 4.5 - - V

CURRENT SENSING

Current Sense Resistance, R

ISEN

Sensed Current Tolerance ISEN1+ = ISEN2+ = ISEN3+ = ISEN4+ = 80μA 768084μA

OVERCURRENT PROTECTION

Overcurrent Trip Level - Average Channel Normal operation 110 125 140 μA

Overcurrent Trip Level - Individual Channel Normal operation 150 177 204 μA

PROTECTION

Undervoltage Threshold VSEN falling 55 60 65 %VID Undervoltage Hysteresis VSEN rising - 10 - %VID Overvoltage Threshold During Soft-Start VR10/VR11 1.24 1.28 1.32 V

Overvoltage Threshold (Default) VR10/VR11, OVPSEL tied to ground, VSEN rising VDAC +

Overvoltage Threshold (Alternate) OVPSEL tied to +5V, VSEN rising VDAC +

Overvoltage Hysteresis VSEN falling - 100 - mV

SWITCHING TIME (Note 3)

UGATE Rise Time t LGATE Rise Time t

= 10kΩ from OFS to GND 37.0 40.0 43.0 μA

OFS

= 30kΩ from OFS to VCC 50.5 53.5 56.5 μA

OFS

= 10k to ground, (Note 3) - 96 - dB

= 100pF, RL = 10k to ground, (Note 3) - 20 - MHz

= 100kΩ - 1.563 - mV/µs

AMD 2.063 mV/µs

T = +25°C 297 300 303 Ω

Dynamic VID change 143 163 183 μA

Dynamic VID change (Note 3) 209.4 238 266.6 μA

AMD 2.13 2.20 2.27 V

150mV

AMD, OVPSEL tied to ground, VSEN rising VDAC +

225mV

325mV

RUGATE; VPVCC RLGATE; VPVCC

= 12V, 3nF load, 10% to 90% - 26 - ns

= 12V, 3nF load, 10% to 90% - 18 - ns

VDAC +

175mV

VDAC +

250mV

VDAC +

350mV

VDAC +

200mV

VDAC +

275mV

VDAC +

375mV

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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

UGATE Fall Time t LGATE Fall Time t UGATE Turn-On Non-Overlap t LGATE Turn-On Non-Overlap t

FUGATE; VPVCC FLGATE; VPVCC PDHUGATE PDHLGATE

GATE DRIVE RESISTANCE (Note 3) Upper Drive Source Resistance V Upper Drive Sink Resistance V Lower Drive Source Resistance V Lower Drive Sink Resistance V

= 12V, 15mA source current 1.25 2.0 3.0 Ω

PVCC

= 12V, 15mA sink current 0.9 1.65 3.0 Ω

PVCC

= 12V, 15mA source current 0.85 1.25 2.2 Ω

PVCC

= 12V, 15mA sink current 0.60 0.80 1.35 Ω

PVCC

OVER TEMPERATURE SHUTDOWN (Note 3)

Thermal Shutdown Setpoint - 160 - °C Thermal Recovery Setpoint - 100 - °C

= 12V, 3nF load, 90% to 10% - 18 - ns

= 12V, 3nF load, 90% to 10% - 12 - ns

; V

= 12V, 3nF load, adaptive - 10 - ns

PVCC

; V

= 12V, 3nF load, adaptive - 10 - ns

PVCC

Timing Diagram

PDHUGATE

RUGATE

FUGATE

UGATE

LGATE

FLGATE

PDHLGATE

RLGATE

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Functional Pin Description

VCC

VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1μF ceramic capacitor.

PVCC1_2 and PVCC3

These pins are the power supply pins for the corresponding channel MOSFET drive, and can be connected to any voltage from +5V to +12V depending on the desired MOSFET gate-drive level. Decouple these pins with a quality

1.0μF ceramic capacitor . Leaving PVCC3 unconnected or grounded programs the

controller for 2-phase operation.

GND

GND is the bias and reference ground for the IC.

This pin is a threshold-sensitive (approxima tely 0.85V) enable input for the controller. Held low, this pin disables controller operation. Pulled high, the pin enables the controller for operation.

A resistor, placed from FS to ground, sets the switching frequency of the controller.

VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7

These are the inputs for the internal DAC that provides the reference voltage for output regulation. These pins respond to TTL logic thresholds. These pins are internally pulled high, to approximately 1.2V, by 40μA internal current sources for Intel modes of operation, and pulled low by 20μA internal current sources for AMD modes of operation. The internal pull-up current decreases to 0 as the VID voltage approaches the internal pull-up voltage. All VID pins are compat ible with external pull-up voltages not exceeding the IC’s bias voltage (VCC).

VRSEL

The state of this pin selects which of the available DAC tables will be used to decode the VID inputs and puts the controller into the corresponding mode of operation. For VR10 mode of operation VRSEL should be less then 0.6V. The VR11 mode of operation can be selected by setting VRSEL between 0.6V and

3.0V , and AMD compliance is selected if this pin is between

3.0V and VCC.

VSEN and RGND

VSEN and RGND are inputs to the precision differe ntial remote-sense amplifier and should be connected to the sense pins of the remote load.

VDIFF

VDIFF is the output of the differential remote-sense amplifier . The voltage on this pin is equal to the difference between VSEN and RGND.

FB and COMP

These pins are the internal error amplifier inverting input and output respectively. FB, VDIFF, and COMP are tied together through external R-C networks to compensate the regulator.

IDROOP

The IDROOP pin is the average channel-current sense output. Connecting this pin through a tuned parallel R-C network to FB allows the converter to incorporate output voltage droop proportional to the output current. If voltage droop is not desired leave this pin unconnected.

REF

The REF input pin is the positive input of the error amplifier. It is internally connected to the DAC output through a 1kΩ resistor. A cap acitor is used between the REF pin and gro und to smooth the voltage transition during Dynamic VID operations.

OFS

The OFS pin provides a means to program a DC current for generating an offset voltage across the re sistor betwe en FB and VDIFF. The offset current is generated via an external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left unconnected.

ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, ISEN3+, ISEN4-, and ISEN4+

These pins are used for differentially sensing the corresponding channel output currents. The sensed currents are used for channel balancing, protection, and load line regulation.

Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node between the RC sense elements surrounding the inductor of their respective channel. Tie the ISEN+ pins to the VCORE side of their corresponding channel’s sense capacitor.

UGATE1, UGATE2, and UGATE3

Connect these pins to the corresponding upper MOSFET gates. These pins are used to control the upper MOSFETs and are monitored for shoot-through prevention purposes.

BOOT1, BOOT2, and BOOT3

These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect these pins to appropriatelychosen external bootstrap capacitors. Internal bootstrap diodes connected to the PVCC pins provide the necessary bootstrap charge.

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PHASE1, PHASE2, and PHASE3

Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return path for the upper MOSFET drives.

LGATE1, LGATE2, and LGATE3

These pins are used to control the lower MOSFET s. Connect these pins to the corresponding lower MOSFETs’ gates.

PWM4

Pulse-width modulation output. Connect this pin to the PWM input pin of an Intersil driver IC if 4-phase operation is desired.

EN_PH4

This pin has two functions. First, a resistor divider connected to this pin will provide a POR power-up synch between the on-chip and external driver. The resistor divider should be designed so that when the POR-trip point of the external driver is reached the voltage on this pin should be 1.21V.

The second function of this pin is disabling PWM4 for 3-phase operation. This can be accomplished by connecting this pin to a +5V supply.

A resistor, placed from SS to ground, will set the soft-start ramp slope for the Intel DAC modes of operation. Refer to Equations 18 and 19 for proper resistor calculation.

For AMD modes of operation, the soft-start ramp frequency is preset, so this pin can be left unconnected.

OVPSEL

This pin selects the OVP trip point during normal operation. Leaving it unconnected or tieing it to ground selects the default setting of VDAC+175mV for Intel Modes of operation and VDAC+250mV for AMD modes of operation. Connecting this pin to VCC will select an OVP trip setting of VID+350mV for all modes of operation.

DRSEL

This pin selects the adaptive dead time scheme the internal drivers will use. If driving MOSFETs, tie this pin to ground to select the PHASE detect scheme or to a +5V supply through a 50kΩ resistor to select the LGATE detect scheme.

PGOOD

During normal operation PGOOD indicates whether the output voltage is within specified overvolt age an d undervoltage limits. If the output voltage exceed s these limit s or a reset event occurs (such as an overcurrent event), PGOOD is pulled low. PGOOD is always low prior to the end of soft-start.

Operation

Multiphase Power Conversion

Microprocessor load current profiles have changed to the point that using single-phase regulators is no longer a viable solution. Designing a regulator that is cost-effective, thermally sound, and efficient has become a challenge that only multiphase converters can accomplish. The ISL6322 controller helps simplify implementation by integrating vital functions and requiring minimal external components. The “Block Diagram” on page 3 provides a top level view of multiphase power conversion using the ISL6322 controller.

IL1 + IL2 + IL3, 7A/DIV

IL3, 7A/DIV

PWM3, 5V/DIV

IL2, 7A/DIV

PWM2, 5V/DIV

IL1, 7A/DIV

PWM1, 5V/DIV

1μs/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

Interleaving

The switching of each channel in a multiphase converter is timed to be symmetrically out of phase with each of the other channels. In a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. In addition, the peak-to-peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (Equations 1 and 2). Increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification.

Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (IL1, IL2, and IL3) combine to form the AC ripple current and the DC load current. The ripple component has three times the ripple frequency of each individual channel current. Each PWM pulse is terminated 1/3 of a cycle after the PWM pulse of the previous phase. The peak-to-peak current for each phase is about 7A, and the DC components of the inductor currents combine to feed the load.

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T o understand the reduction of ripple current amplitude in the multiphase circuit, examine the equation representing an individual channel peak-to-peak inductor current.

VINV

PP–()

----------------------------------------------------------=

–()V

In Equation 1, V

OUT

and V

⋅

OUT

V⋅IN⋅

are the input and output

OUT

(EQ. 1)

voltages respectively, L is the single-channel inductor value, and f

is the switching frequency.

The output capacitors conduct the ripple component of the inductor current. In the case of multiphase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Compare Equation 1 to the expression for the peak-to-peak current after the summation of N symmetrically phase-shifted inductor currents in Equation 2. Peak-to-peak ripple current decreases by an amount proportional to the number of channels. Output voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors.

CP P–()

------------------------------------------------------------------- -=

⋅–()V

OUT

⋅

OUT

V⋅IN⋅

(EQ. 2)

VINNV

Another benefit of interleaving is to reduce input ripple current. Input capacitance is determined in part by the maximum input ripple current. Multiphase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. The example in Figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current.

The converter depicted in Figure 2 delivers 1.5V to a 36A load from a 12V input. The RMS input capacitor current is 5.9A. Compare this to a single-phase converter also stepping down 12V to 1.5V at 36A. The single-phase converter has 11.9A RMS input capacitor current. The single-phase converter must use an input capacitor bank with twice the RMS current capacity as the equivalent three-phase converter.

INPUT-CAPACITOR CURRENT, 10A/DIV

Active Pulse Positioning (APP) Modulated PWM Operation

The ISL6312 uses a proprietary Active Pulse Positioning (APP) modulation scheme to control the internal PWM signals that command each channel’s driver to turn their upper and lower MOSFETs on and off. The time interval in which a PWM signal can occur is generated by an internal clock, whose cycle time is the inverse of the switching frequency set by the resistor between the FS pin and ground. The advantage of Intersil’s proprietary Active Pulse Positioning (APP) modulator is that the PWM signal has the ability to turn on at any point during this PWM time interval, and turn off immediately after the PWM signal has transitioned high. This is important because is allows the controller to quickly respond to output voltage drops associated with current load spikes, while avoiding the ring back affects associated with other modulation schemes.

The PWM output state is driven by the position of the error amplifier output signal, V signal relative to the proprietary modulator ramp waveform as illustrated in Figure 3. At the beginning of each PWM time interval, this modified V internal modulator waveform. As long as the modified V

voltage is lower then the modulator waveform

COMP

voltage, the PWM signal is commanded low. The internal MOSFET driver detects the low state of the PWM signal and turns off the upper MOSFET and turns on the lower synchronous MOSFET. When the modified V crosses the modulator ramp, the PWM output transitions high, turning off the synchronous MOSFET and turning on the upper MOSFET. The PWM signal will remain high until the modified V

voltage crosses the modulator ramp

COMP

again. When this occurs the PWM signal will transition low again.

During each PWM time interval the PWM signal can only transition high once. Once PWM transitions high it can not transition high again until the beginning of the next PWM time interval. This prevents the occurrence of double PWM pulses occurring during a single period.

, minus the current correction

COMP

signal is compared to the

COMP

voltage

CHANNEL 3 INPUT CURRENT 10A/DIV

CHANNEL 2 INPUT CURRENT 10A/DIV

CHANNEL 1 INPUT CURRENT 10A/DIV

1μs/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-

CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER

To further improve the transient response, ISL6312 also implements Intersil’s proprietary Adaptive Phase Alignment (APA) technique, which turns on all phases together under transient events with large step current. With both APP and APA control, ISL6312 can achieve excellent transient performance and reduce the deman d on the output capacitors.

Channel-Current Balance

One important benefit of multiphase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. By doing this the designer avoids the complexity of driving parallel MOSFETs and the expense of using expensive heat sinks and exotic magnetic materials.

FN9289.4

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ISL6312

In order to realize the thermal advantage, it is important that each channel in a multiphase converter be controlled to carry equal amounts of current at any load level. To achieve this, the currents through each channel must be sampled every switching cycle. The sampled currents, I

, from each

active channel are summed together and divided by the number of active channels. The resulting cycle average current, I

, provides a measure of the total load-current

AVG

demand on the converter during each switching cycle. Channel-current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented currentbalance method is illustrated in Figure 3, with error correction for Channel 1 represented. In the figure, the cycle average current, I sample, I

COMP

, to create an error signal IER.

FILTER

, is compared with the Channel 1

AVG

f(s)

AVG

MODULATOR

RAMP

WAVEFORM

÷ N

PWM1

TO GATE

CONTROL

LOGIC

Continuous Current Sampling

In order to realize proper current-balance, the currents in each channel are sensed continuously every switching cycle. During this time the current-sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current, I scaled version of the inductor current.

The ISL6312 supports inductor DCR current sensing to continuously sense each channel’s current for channelcurrent balance. The internal circuitry, shown in Figure 5 represents channel n of an N-channel converter. This circuitry is repeated for each channel in the converter, but may not be active depending on how many channels are operating.

MOSFET

DRIVER

ISL6312 INTERNAL CIRCUIT

. This sensed current, I

UGATE(n)

LGATE(n)

SEN

DCR

INDUCTOR

VL(s)

VC(s)

, is simply a

OUT

NOTE: Channel 3 and 4 are optional.

FIGURE 3. CHANNEL-1 PWM FUNCTION AND CURRENT-

BALANCE ADJUSTMENT

The filtered error signal modifies the pulse width commanded by V I

toward zero. The same method for error signal

to correct any unbalance and force

COMP

correction is applied to each active channel.

PWM

SWITCHING PERIOD

SEN

TIME

FIGURE 4. CONTINUOUS CURRENT SAMPLING

SAMPLE

SEN

VC(s)

ISEN

ISEN-(n)

ISEN+(n)

*R2 is OPTIONAL

FIGURE 5. INDUCTOR DCR CURRENT SENSING

CONFIGURATION

Inductor windings have a characteristic distributed resistance or DCR (Direct Current Resistance). For simplicity, the inductor DCR is considered as a separate lumped quantity, as shown in Figure 5. The channel current I

, flowing through the inductor, passes through the DCR.

Equation 3 shows the s-domain equivalent voltage, V

across the inductor.

VLs() ILsL DCR+⋅()⋅=

A simple R-C network across the inductor (R

and C)

(EQ. 3)

extracts the DCR voltage, as shown in Figure 5. The voltage across the sense capacitor, V proportional to the channel current I

, can be shown to be

, shown in Equation 4.

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August 1, 2007

ISL6312

sL⋅

VCs()

⎛⎞

-------------

⎝⎠

--------------------------------------

DCR

C⋅⋅ 1+()

DCR I

⋅⋅=

(EQ. 4)

In some cases it may be necessary to use a resistor divider R-C network to sense the current through the inductor. This can be accomplished by placing a second resistor, R

across the sense capacitor. In these cases the voltage across the sense capacitor , V channel current I

--------------------------------------------------------

s()

⎛⎞

⎜⎟ ⎝⎠

---------------------

R2R1+

, and the resistor divider ratio, K.

sL⋅

⎛⎞

-------------

⎝⎠

------------------------

DCR

⋅()

1R2

C⋅⋅1+

, becomes proportional to the

(EQ. 5)

⋅⋅⋅=

KDCRI

(EQ. 6)

If the R-C network components are selected such that the RC time constant matches the inductor L/DCR time constant, then V

is equal to the voltage drop across the

DCR multiplied by the ratio of the resistor divider, K. If a resistor divider is not being used, the value for K is 1.

The capacitor voltage V sense resistor R

ISEN

, is then replicated across the

. The current through R

ISEN

is proportional to the inductor current. Equation 7 shows that the proportion between the channel current and the sensed current (I

) is driven by the value of the sense resistor,

SEN

the resistor divider ratio, and the DCR of the inductor.

DCR

----------------- -

SEN

⋅⋅=

ISEN

(EQ. 7)

Output Voltage Setting

The ISL6312 uses a digital to analog converter (DAC) to generate a reference voltage based on the logic signals at the VID pins. The DAC decodes the logic signals into one of the discrete voltages shown in Tables 2, 3, 4 and 5. In Intel modes of operation, each VID pin is pulled up to an internal

1.2V voltage by a weak current source (40μA), which decreases to 0A as the voltage at the VID pin varies from 0 to the internal 1.2V pull-up voltage. In AMD modes of operation the VID pins are pulled low by a weak 20μA current source. External pull-up resistors or active-high output stages can augment the pull-up current sources, up to a voltage of 5V .

The ISL6312 accommodates four different DAC ranges: Intel VR10 (Extended), Intel VR1 1, AMD K8/K9 5- bit, and AMD 6-bit. The state of the VRSEL and VID7 pins decide which DAC version is active. Refer to Table 1 for a description of how to select the desired DAC version.

TABLE 1. ISL6312 DAC SELECT TABLE

DAC VERSION VRSEL PIN VID7 PIN

VR10(Extended) VRSEL < 0.6V -

VR11 0.8V < VRSEL < 3.0V AMD 5-Bit 3.0V < VRSEL < VCC low AMD 6-Bit 3.0V < VRSEL < VCC high

TABLE 2. VR10 (EXTENDED) VOLT AGE IDENTIFICA TION

CODES

VID4 VID3 VID2 VID1 VID0 VID5 VID6 VDAC

0 1 0 1 0 1 1 1.60000

0 1 0 1 0 1 0 1.59375

0 1 0 1 1 0 1 1.58750

0 1 0 1 1 0 0 1.58125

0 1 0 1 1 1 1 1.57500

0 1 0 1 1 1 0 1.56875

0 1 1 0 0 0 1 1.56250

0 1 1 0 0 0 0 1.55625

0 1 1 0 0 1 1 1.55000

0 1 1 0 0 1 0 1.54375

0 1 1 0 1 0 1 1.53750

0 1 1 0 1 0 0 1.53125

0 1 1 0 1 1 1 1.52500

0 1 1 0 1 1 0 1.51875

0 1 1 1 0 0 1 1.51250

0 1 1 1 0 0 0 1.50625

0 1 1 1 0 1 1 1.50000

0 1 1 1 0 1 0 1.49375

0 1 1 1 1 0 1 1.48750

0 1 1 1 1 0 0 1.48125

0 1 1 1 1 1 1 1.47500

0 1 1 1 1 1 0 1.46875

1 0 0 0 0 0 1 1.46250

1 0 0 0 0 0 0 1.45625

1 0 0 0 0 1 1 1.45000

1 0 0 0 0 1 0 1.44375

1 0 0 0 1 0 1 1.43750

1 0 0 0 1 0 0 1.43125

1 0 0 0 1 1 1 1.42500

1 0 0 0 1 1 0 1.41875

1 0 0 1 0 0 1 1.41250

1 0 0 1 0 0 0 1.40625

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ISL6312

TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION

CODES (Continued)

VID4 VID3 VID2 VID1 VID0 VID5 VID6 VDAC

1 0 0 1 0 1 1 1.40000

1 0 0 1 0 1 0 1.39375

1 0 0 1 1 0 1 1.38750

1 0 0 1 1 0 0 1.38125

1 0 0 1 1 1 1 1.37500

1 0 0 1 1 1 0 1.36875

1 0 1 0 0 0 1 1.36250

1 0 1 0 0 0 0 1.35625

1 0 1 0 0 1 1 1.35000

1 0 1 0 0 1 0 1.34375

1 0 1 0 1 0 1 1.33750

1 0 1 0 1 0 0 1.33125

1 0 1 0 1 1 1 1.32500

1 0 1 0 1 1 0 1.31875

1 0 1 1 0 0 1 1.31250

1 0 1 1 0 0 0 1.30625

1 0 1 1 0 1 1 1.30000

1 0 1 1 0 1 0 1.29375

1 0 1 1 1 0 1 1.28750

1 0 1 1 1 0 0 1.28125

1 0 1 1 1 1 1 1.27500

1 0 1 1 1 1 0 1.26875

1 1 0 0 0 0 1 1.26250

1 1 0 0 0 0 0 1.25625

1 1 0 0 0 1 1 1.25000

1 1 0 0 0 1 0 1.24375

1 1 0 0 1 0 1 1.23750

1 1 0 0 1 0 0 1.23125

1 1 0 0 1 1 1 1.22500

1 1 0 0 1 1 0 1.21875

1 1 0 1 0 0 1 1.21250

1 1 0 1 0 0 0 1.20625

1 1 0 1 0 1 1 1.20000

1 1 0 1 0 1 0 1.19375

1 1 0 1 1 0 1 1.18750

1 1 0 1 1 0 0 1.18125

1 1 0 1 1 1 1 1.17500

1 1 0 1 1 1 0 1.16875

1 1 1 0 0 0 1 1.16250

TABLE 2. VR10 (EXTENDED) VOLT AGE IDENTIFICA TION

CODES (Continued)

VID4 VID3 VID2 VID1 VID0 VID5 VID6 VDAC

1 1 1 0 0 0 0 1.15625

1 1 1 0 0 1 1 1.15000

1 1 1 0 0 1 0 1.14375

1 1 1 0 1 0 1 1.13750

1 1 1 0 1 0 0 1.13125

1 1 1 0 1 1 1 1.12500

1 1 1 0 1 1 0 1.11875

1 1 1 1 0 0 1 1.11250

1 1 1 1 0 0 0 1.10625

1 1 1 1 0 1 1 1.10000

1 1 1 1 0 1 0 1.09375

1111101OFF

1111100OFF

1111111OFF

1111110OFF

0 0 0 0 0 0 1 1.08750

0 0 0 0 0 0 0 1.08125

0 0 0 0 0 1 1 1.07500

0 0 0 0 0 1 0 1.06875

0 0 0 0 1 0 1 1.06250

0 0 0 0 1 0 0 1.05625

0 0 0 0 1 1 1 1.05000

0 0 0 0 1 1 0 1.04375

0 0 0 1 0 0 1 1.03750

0 0 0 1 0 0 0 1.03125

0 0 0 1 0 1 1 1.02500

0 0 0 1 0 1 0 1.01875

0 0 0 1 1 0 1 1.01250

0 0 0 1 1 0 0 1.00625

0 0 0 1 1 1 1 1.00000

0 0 0 1 1 1 0 0.99375

0 0 1 0 0 0 1 0.98750

0 0 1 0 0 0 0 0.98125

0 0 1 0 0 1 1 0.97500

0 0 1 0 0 1 0 0.96875

0 0 1 0 1 0 1 0.96250

0 0 1 0 1 0 0 0.95625

0 0 1 0 1 1 1 0.95000

0 0 1 0 1 1 0 0.94375

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August 1, 2007

ISL6312

TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION

CODES (Continued)

VID4 VID3 VID2 VID1 VID0 VID5 VID6 VDAC

0 0 1 1 0 0 1 0.93750

0 0 1 1 0 0 0 0.93125

0 0 1 1 0 1 1 0.92500

0 0 1 1 0 1 0 0.91875

0 0 1 1 1 0 1 0.91250

0 0 1 1 1 0 0 0.90625

0 0 1 1 1 1 1 0.90000

0 0 1 1 1 1 0 0.89375

0 1 0 0 0 0 1 0.88750

0 1 0 0 0 0 0 0.88125

0 1 0 0 0 1 1 0.87500

0 1 0 0 0 1 0 0.86875

0 1 0 0 1 0 1 0.86250

0 1 0 0 1 0 0 0.85625

0 1 0 0 1 1 1 0.85000

0 1 0 0 1 1 0 0.84375

0 1 0 1 0 0 1 0.83750

0 1 0 1 0 0 0 0.83125

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

00000000OFF

00000001OFF

000000101.60000

000000111.59375

000001001.58750

000001011.58125

000001101.57500

000001111.56875

000010001.56250

000010011.55625

000010101.55000

000010111.54375

000011001.53750

000011011.53125

000011101.52500

000011111.51875

000100001.51250

000100011.50625

000100101.50000

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

000100111.49375

000101001.48750

000101011.48125

000101101.47500

000101111.46875

000110001.46250

000110011.45625

000110101.45000

000110111.44375

000111001.43750

000111011.43125

000111101.42500

000111111.41875

001000001.41250

001000011.40625

001000101.40000

001000111.39375

001001001.38750

001001011.38125

001001101.37500

001001111.36875

001010001.36250

001010011.35625

001010101.35000

001010111.34375

001011001.33750

001011011.33125

001011101.32500

001011111.31875

001100001.31250

001100011.30625

001100101.30000

001100111.29375

001101001.28750

001101011.28125

001101101.27500

001101111.26875

001110001.26250

001110011.25625

001110101.25000

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ISL6312

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

001110111.24375

001111001.23750

001111011.23125

001111101.22500

001111111.21875

010000001.21250

010000011.20625

010000101.20000

010000111.19375

010001001.18750

010001011.18125

010001101.17500

010001111.16875

010010001.16250

010010011.15625

010010101.15000

010010111.14375

010011001.13750

010011011.13125

010011101.12500

010011111.11875

010100001.11250

010100011.10625

010100101.10000

010100111.09375

010101001.08750

010101011.08125

010101101.07500

010101111.06875

010110001.06250

010110011.05625

010110101.05000

010110111.04375

010111001.03750

010111011.03125

010111101.02500

010111111.01875

011000001.01250

011000011.00625

011000101.00000

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

011000110.99375

011001000.98750

011001010.98125

011001100.97500

011001110.96875

011010000.96250

011010010.95625

011010100.95000

011010110.94375

011011000.93750

011011010.93125

011011100.92500

011011110.91875

011100000.91250

011100010.90625

011100100.90000

011100110.89375

011101000.88750

011101010.88125

011101100.87500

011101110.86875

011110000.86250

011110010.85625

011110100.85000

011110110.84375

011111000.83750

011111010.83125

011111100.82500

011111110.81875

100000000.81250

100000010.80625

100000100.80000

100000110.79375

100001000.78750

100001010.78125

100001100.77500

100001110.76875

100010000.76250

100010010.75625

100010100.75000

FN9289.4

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ISL6312

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

100010110.74375

100011000.73750

100011010.73125

100011100.72500

100011110.71875

100100000.71250

100100010.70625

100100100.70000

100100110.69375

100101000.68750

100101010.68125

100101100.67500

100101110.66875

100110000.66250

100110010.65625

100110100.65000

100110110.64375

100111000.63750

100111010.63125

100111100.62500

100111110.61875

101000000.61250

101000010.60625

101000100.60000

101000110.59375

101001000.58750

101001010.58125

101001100.57500

101001110.56875

101010000.56250

101010010.55625

101010100.55000

101010110.54375

101011000.53750

101011010.53125

101011100.52500

101011110.51875

101100000.51250

101100010.50625

101100100.50000

TABLE 3. VR11 VOLTAGE IDENTIFICATION CODES (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

11111110OFF

11111111OFF

TABLE 4. AMD 5-BIT VOLTAGE IDENTIFICATION CODES

VID4 VID3 VID2 VID1 VID0 VDAC

11111Off

111100.800

111010.825

111000.850

110110.875

110100.900

110010.925

110000.950

101110.975

101101.000

101011.025

101001.050

100111.075

100101.100

100011.125

100001.150

011111.175

011101.200

011011.225

011001.250

010111.275

010101.300

010011.325

010001.350

001111.375

001101.400

001011.425

001001.450

000111.475

000101.500

000011.525

000001.550

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August 1, 2007

ISL6312

TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION COD ES

VID5 VID4 VID3 VID2 VID1 VID0 VDAC

0 0 0 0 0 0 1.5500

0 0 0 0 0 1 1.5250

0000101.5000

0000111.4750

0001001.4500

0001011.4250

0001101.4000

0001111.3750

0010001.3500

0010011.3250

0010101.3000

0010111.2750

0011001.2500

0011011.2250

0011101.2000

0011111.1750

0100001.1500

0100011.1250

0100101.1000

0100111.0750

0101001.0500

0101011.0250

0101101.0000

0101110.9750

0110000.9500

0110010.9250

0110100.9000

0110110.8750

0111000.8500

0111010.8250

0111100.8000

0111110.7750

1000000.7625

1000010.7500

1000100.7375

1000110.7250

1001000.7125

1001010.7000

1001100.6875

TABLE 5. AMD 6-BIT VOLTAGE IDEN TIFICATION CODES

VID5 VID4 VID3 VID2 VID1 VID0 VDAC

1001110.6750

1010000.6625

1010010.6500

1010100.6375

1010110.6250

1011000.6125

1011010.6000

1011100.5875

1011110.5750

1100000.5625

1100010.5500

1100100.5375

1100110.5250

1101000.5125

1101010.5000

1101100.4875

1101110.4750

1110000.4625

1110010.4500

1110100.4375

1110110.4250

1111000.4125

1111010.4000

1111100.3875

1111110.3750

(Continued)

Voltage Regulation

The integrating compensation network shown in Figure 6 insures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6312 to include the combined tolerances of each of these elements.

The output of the error amplifier, V triangle waveform to generate the PWM signals. The PWM signals control the timing of the Internal MOSFET drivers and regulate the converter output so that the voltage at FB is equal to the voltage at REF. This will regulate the output voltage to be equal to Equation 8. The internal and external circuitry that controls voltage regulation is illustrated in Figure 6.

, is compared to the

COMP

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August 1, 2007

ISL6312

OUTVREFVOFS

– V

–=

DROOP

(EQ. 8)

The ISL6312 incorporates an internal differential remotesense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point resulting in a more accurate means of sensing output voltage. Connect the microprocessor sense pins to the noninverting input, VSEN, and inverting input, RGND, of the remote-sense amplifier. The remote-sense output, V

DIFF

, is connected to the inverting input of the error amplifier through an external resistor.

EXTERNAL CIRCUIT ISL6312 INTERNAL CIRCUIT

COMP

VID DAC

DROOP

OUT

FIGURE 6. OUTPUT VOLT AGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

REF

IDROOP

+ V

OFS

VDIFF

VSEN

RGND

)

ERROR

AMPLIFIER

AVG

OFS

DIFFERENTIAL REMOTE-SENSE AMPLIFIER

COMP

Load-Line (Droop) Regulation

Some microprocessor manufacturers require a preciselycontrolled output resistance. This dependence of output voltage on load current is often termed “droop” or “load line” regulation. By adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers.

In other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results from fast load-current demand changes.

The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger

negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit.

As shown in Figure 6, a current proportional to the average current of all active channels, I load-line regulation resistor R across R

is proportional to the output current, effectively

, flows from FB through a

AVG

. The resulting voltage drop

creating an output voltage droop with a steady-state value defined as:

DROOPIAVGRFB

⋅=

(EQ. 9)

The regulated output voltage is reduced by the droop voltage V

. The output voltage as a function of load current is

DROOP

derived by combining Equations 7, 8, and 9.

OUTVREFVOFS

–

In Equation 10, V

⎛⎞

–=

⎜⎟ ⎝⎠

is the reference voltage, V

REF

programmed offset voltage, I of the converter, R

is the internal sense resistor

ISEN

connected to the ISEN+ pin, R

DCR

OUT

-------------

----------------- -

⋅⋅

ISEN

is the total output current

OUT

is the feedback resistor, N

OFS

(EQ. 10)

is the

is the active channel number, and DCR is the Inductor DCR value.

Therefore the equivalent loadline impedance, i.e. droop impedance, is equal to Equation 11:

DCR

------------

----------------- -

⋅=

ISEN

(EQ. 11)

Output-Voltage Offset Programming

The ISL6312 allows the designer to accurately adjust the offset voltage by connecting a resistor, R pin to VCC or GND. When R

is connected between OFS

OFS

and VCC, the voltage across it is regulated to 1.6V. This causes a proportional current (I If R regulated to 0.4V, and I

is connected to ground, the voltage across it is

OFS

flows out of the FB pin. The

OFS

) to flow into the FB pin.

OFS

offset current flowing through the resistor between VDIFF and FB will generate the desired offset voltage which is equal to the product (I

x RFB). These functions are

OFS

shown in Figures 7 and 8. Once the desired output offset voltage has been determined,

use the following formulas to set R For Negative Offset (connect R

0.4 RFB⋅

OFS

--------------------------

OFFSET

For Positive Offset (connect R

1.6 RFB⋅

OFS

--------------------------

OFFSET

OFS

to GND):

to VCC):

, from the OFS

OFS

(EQ. 12)

(EQ. 13)

FN9289.4

August 1, 2007

OFS

VDIFF

VCC

OFS

ISL6312

OFS

1:1

CURRENT

MIRROR

OFS

E/A

REF

FIGURE 7. POSITIVE OFFSET OUTPUT VOL T AGE

PROGRAMMING

OFS

VDIFF

OFS

VCC

E/A

REF

VCC

1.6V

ISL6312

a new code is established and it remains stable for 3 consecutive readings (1ms to 1.33ms), the ISL6312 recognizes the new code and changes the internal DAC reference directly to the new level. The Intel processor controls the VID transitions and is responsible for incrementing or decrementing one VID step at a time. In VR10 and VR11 settings, the ISL6312 will immediately change the internal DAC reference to the new requested value as soon as the request is validated, which means the fastest recommended rate at which a bit change can occur is once every 2ms. In cases where the reference step is too large, the sudden change can trigger overcurrent or overvoltage events.

In order to ensure the smooth transition of output voltage during a VR10 or VR11 VID change, a VID step change smoothing network is required. This network is composed of an internal 1kW resistor between the DAC and the REF pin, and the external capacitor CREF, between the REF pin and ground. The selection of CREF is based on the time duration for 1 bit VID change and the allowable delay time.

Assuming the microprocessor controls the VID change at 1 bit every TVID, the relationship between CREF and TVID is given by Equation 14.

REF

0.001 S() T

⋅=

VID

(EQ. 14)

As an example, for a VID step change rate of 5ms per bit, the value of CREF is 5600pF based on Equation 14.

1:1

OFS

GND

OFS

ISL6312

CURRENT

MIRROR

OFS

0.4V

GND

FIGURE 8. NEGATIVE OFFSET OUTP UT VOL TAGE

PROGRAMMING

Dynamic VID

Modern microprocessors need to make changes to their core voltage as part of normal operation. They direct the ISL6312 to do this by making changes to the VID inputs. The ISL6312 is required to monitor the DAC inputs and respond to on-thefly VID changes in a controlled manner, sup ervising a safe output voltage transition without discontinuity or disruption. The DAC mode the ISL6312 is operating in determines how the controller responds to a dynamic VID change.

INTEL DYNAMIC VID TRANSITIONS

When in Intel VR10 or VR11 mode the ISL6312 checks the VID inputs on the positive edge of an internal 3MHz clock. If

AMD DYNAMIC VID TRANSITIONS

When running in AMD 5-bit or 6-bit modes of operation, the ISL6312 responds differently to a dynamic VID change then when in Intel VR10 or VR11 mode. In the AMD modes the ISL6312 still checks the VID inputs on the positive edge of an internal 3MHz clock. In these modes the VID code can be changed by more than a 1-bit step at a time. If a new code is established and it remains stable for 3 consecutive readings (1ms to 1.33ms), the ISL6312 recognizes the change and begins slewing the DAC in 6.25mV steps at a stepping frequency of 330kHz until the VID and DAC are equal. Thus, the total time required for a VID change, tDVID, is dependent only on the size of the VID change (DVVID).

The time required for a ISL6312-based converter in AMD 5-bit DAC configuration to make a 1.1V to 1.5V reference voltage change is about 194ms, as calculated using Equation 15.

DVID

------------------------- -

330 10

VID

⎛⎞

---------------------

⋅=

⎝⎠

0.00625

(EQ. 15)

In order to ensure the smooth transition of output voltage during an AMD VID change, a VID step change smoothing network is required. This network is composed of an internal 1kΩ resistor between the DAC and the REF pin, and the external capacitor C For AMD VID transitions C

, between the REF pin and ground.

REF

should be a 1000pF

REF

capacitor.

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ISL6312

User Selectable Adaptive Deadtime Control Techniques

The ISL6312 integrated drivers incorporate two different adaptive deadtime control techniques, which the user can choose between. Both of these control techniques help to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower MOSFET body-diode conduction, and both help to prevent the upper and lower MOSFETs from conducting simultaneously. This is accomplished by ensuring either rising gate turns on its MOSFET with minimum and sufficient delay after the other has turned off.

The difference between the two adaptive deadtime control techniques is the method in which they detect that the lower MOSFET has transitioned off in order to turn on the upper MOSFET. The state of the DRSEL pin chooses which of the two control techniques is active. By tying the DRSEL pin directly to ground, the PHASE Detect Scheme is chosen, which monitors the voltage on the PHASE pin to determine if the lower MOSFET has transitioned off or not. Tying the DRSEL pin to VCC though a 50kΩ resistor selects the LGATE Detect Scheme, which monitors the voltage on the LGA TE pin to determine if the lower MOSFET has turned off or not. For both schemes, the method for determining whether the upper MOSFET has transitioned off in order to signal to turn on the lower MOSFET is the same.

PHASE DETECT

If the DRSEL pin is tied directly to ground, the PHASE Detect adaptive deadtime control technique is selected. For the PHASE detect scheme, during turn-off of the lower MOSFET, the PHASE voltage is monitored until it reaches a -0.3V/+0.8V (forward/reverse inductor current). At this time the UGATE is released to rise. An auto-zero comparator is used to correct the r the -0.3V phase level during r case of zero current, the UGATE is released after 35ns delay of the LGATE dropping below 0.5V. When LGATE first begins to transition low, this quick transition can disturb the PHASE node and cause a false trip, so there is 20ns of blanking time once LGA TE falls until PHASE is monitored.

Once the PHASE is high, the advanced adaptive shoot-through circuitry monitors the PHASE and UGATE voltages during a PWM falling edge and the subsequent UGATE turn-off. If either the UGATE falls to less than 1.75V above the PHASE or the PHASE falls to less than +0.8V , the LGATE is released to turn-on.

drop in the phase voltage preventing false detection of

DS(ON)

conduction period. In the

Internal Bootstrap Device

All three integrated drivers feature an internal bootstrap schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the PHASE node. This reduces voltage stress on the boot to phase pins.

1.6

1.4

1.2

1.0

(µF)

0.8

0.6

BOOT_CAP

0.4

0.2 20nC

0.0

FIGURE 9. BOOTSTRAP CAPACIT ANCE vs BOOT RIPPLE

The bootstrap capacitor must have a maximum voltage rating above PVCC + 4V and its capacitance value can be chosen from Equation 16: where Q charge per upper MOSFET at V N

is the number of control MOSFETs. The ΔV

term is defined as the allowable droop in the rail of the upper gate drive.

BOOT_CAP

GATE

≥

QG1PVCC⋅

----------------------------------

GATE

50nC

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0

VOLTAGE

GATE

--------------------------------------

ΔV

BOOT_CAP

⋅=

GS1

= 100nC

ΔV

BOOT_CAP

(V)

is the amount of gate

gate-source voltage and

GS1

BOOT_CAP

(EQ. 16)

LGATE DETECT

If the DRSEL pin is tied to VCC through a 50kΩ resistor, the LGA TE Detect adaptive deadtime control technique is selected. For the LGATE detect scheme, during turn-off of the lower MOSFET, the LGA TE voltage is monitored until it reaches

1.75V. At this time the UGA TE is r eleased to rise.

Gate Drive Voltage Versatility

The ISL6312 provides the user flexibility in choosing the gate drive voltage for efficiency optimization. The controller ties the upper and lower drive rails together. Simply applying a voltage from 5V up to 12V on PVCC sets both gate drive rail voltages simultaneously.

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ISL6312

Initialization

Prior to initialization, proper conditions must exist on the EN, VCC, PVCC and the VID pins. When the conditions are met, the controller begins soft-start. Once the output voltage is within the proper window of operation, the controller asserts PGOOD.

ISL6312 INTERNAL CIRCUIT

POR

CIRCUIT

SOFT-START

AND

FAULT LOGIC

FIGURE 10. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (EN) FUNCTION

ENABLE COMPARATOR

0.85V

1.21V

Enable and Disable

While in shutdown mode, the PWM outputs are held in a high-impedance state to assure the drivers remain off. The following input conditions must be met, for both Intel and AMD modes of operation, before the ISL6312 is released from shutdown mode to begin the soft-start startup sequence:

1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the ISL6312 is guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6312 will not inadvertently turn off unless the bias voltage drops substantially (see “Electrical Specifications” on page 6).

2. The voltage on EN must be above 0.85V. The EN input allows for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6312 in shutdown until the voltage at EN rises above 0.85V . The enable comparator has 110mV of hysteresis to prevent bounce.

3. The voltage on the EN_PH4 pin must be above 1.21V. The EN_PH4 input allows for power sequencing between the controller and the external driver.

4. The driver bias voltage applied at the PVCC pins must reach the internal power-on reset (POR) rising threshold.

EXTERNAL CIRCUIT

VCC

PVCC1

+12V

10.7kΩ

1.40kΩ

EN_PH4

In order for the ISL6312 to begin operation, PVCC1 is the only pin that is required to have a voltage applied that exceeds POR. However, for 2 or 3-phase operation PVCC2 and PVCC3 must also exceed the POR threshold. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6312 will not inadvertently turn off unless the PVCC bias voltage drops substantially (see “Electrical Specifications” on page 6).

For Intel VR10, VR11 and AMD 6-bit modes of operation these are the only conditions that must be met for the controller to immediately begin the soft-start sequence. If running in AMD 5-bit mode of operation there is one more condition that must be met:

5. The VID code must not be 11 1 1 1 in AMD 5-bit mode. This code signals the controller that no load is present. The controller will not allow soft-start to begin if this VID code is present on the VID pins.

Once all of these conditions are met the controller will begin the soft-start sequence and will ramp the output voltage up to the user designated level.

Intel Soft-Start

The soft-start function allows the converter to bring up the output voltage in a controlled fashion, resulting in a linear ramp-up. The soft-start sequence for the Intel modes of operation is slightly different then the AMD soft-start sequence.

For the Intel VR10 and VR11 modes of operation, the soft-start sequence if composed of four periods, as shown in Figure 11. Once the ISL6312 is released from shutdown and soft-start begins (as described in “Enable and Disable” on page 22), the controller will have fixed delay period TD1. After this delay period, the VR will begin first soft-start ramp until the output voltage reaches 1.1V VBOOT voltage. Then, the controller will regulate the VR voltage at 1.1V for another fixed period TD3. At the end of TD3 period, ISL6312 will read the VID signals. If the VID code is valid, ISL6312 will initiate the second soft-start ramp until the output voltage reaches the VID voltage plus/minus any offset or droop voltage.

The soft-start time is the sum of the 4 periods as shown in Equation 17.

TD1TD2TD3TD4+++=

(EQ. 17)

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August 1, 2007

VOUT, 500mV/DIV

ISL6312

TDB

------------------------- -

330 10

VID

⎛⎞

---------------------

⋅=

⎝⎠

0.00625

(EQ. 20)

After the DAC voltage reaches the final VID setting, PGOOD will be set to high with the fixed delay TDC. The typical value for TDC can range between 1.5ms and 3.0ms.

TD1

EN_VTT

PGOOD

FIGURE 11. SOFT-START WAVEFORMS

TD2

500µs/DIV

TD3 TD4

TD5

TD1 is a fixed delay with the typical value as 1.40ms. TD3 is determined by the fixed 85µs plus the time to obtain valid VID voltage. If the VID is valid before the output reaches the

1.1V, the minimum time to validate the VID input is 500ns. Therefore the minimum TD3 is about 86µs.

During TD2 and TD4, ISL6312 digitally controls the DAC voltage change at 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor R

from SS pin to GND. The

second soft-start ramp time TD2 and TD4 can be calculated based on Equations 18 and 19:

1.1 R⋅

------------------------

TD2

TD4

6.25 25⋅

----------------------------------------------------

VID

6.25 25⋅

μs()=

1.1–()RSS⋅

(EQ. 18)

μs()=

(EQ. 19)

VOUT, 500mV/DIV

TDA

EN_VTT

PGOOD

FIGURE 12. SOFT-START WAVEFORMS

TDB

500µs/DIV

TDC

Pre-Biased Soft-Start

The ISL6312 also has the ability to start up into a pre-charged output, without causing any unnecessary disturbance. The FB pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both MOSFET s of f.

OUTPUT PRECHARGED

ABOVE DAC LEVEL

For example, when VID is set to 1.5V and the R

is set at

100kΩ, the first soft-start ramp time TD2 will be 704µs and the se c o nd s oft-st a r t r a m p t im e T D4 will be 256µs.

NOTE: If the SS pin is grounded, the soft-start ramp in TD2 and TD4 will be defaulted to a 6.25mV step frequency of 330kHz.

After the DAC voltage reaches the final VID setting, PGOOD will be set to high with the fixed delay TD5. The typical value for TD5 is 440µs.

AMD Soft-Start

For the AMD 5-bit and 6-bit modes of operation, the soft-start sequence is composed of three periods, as shown in Figure 12. At the beginning of soft-start, the VID code is immediately obtained from the VID pins, followed by a fixed delay period TDA. After this delay period the ISL6312 will begin ramping the output voltage to the desired DAC level at a fixed rate of 6.25mV per step, with a stepping frequency of 330kHz. The amount of time required to ramp the output voltage to the final DAC voltage is referred to as TDB, and can be calculated as shown in Equation 20:

OUTPUT PRECHARGED

BELOW DAC LEVEL

GND>

FIGURE 13. SOFT-ST ART WAVEFORMS FOR ISL6312-BASED

MULTIPHASE CONVERTER

(0.5V/DIV)

OUT

EN (5V/DIV)

Once the internal ramping reference exceeds the FB pin potential, the output drives are enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the DAC setting. Should the output be pre-charged to a level exceeding the DAC setting, the output drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage down to the DAC-set level.

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August 1, 2007

ISL6312

Fault Monitoring and Protection

The ISL6312 actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common power good indicator is provided for linking to external system monitors. The schematic in Figure 14 outlines the interaction between the fault monitors and the power good signal.

170μA

OCL

VDAC

VRSEL

+175mV,

+250mV,

+350mV

SOFT-START, FAULT

AND CONTROL LOGIC

OVP

OVPSEL

VSEN

RGND

VDIFF

0.60 x DAC

FIGURE 14. POWER GOOD AND PROTECTION CIRCUITRY

Power Good Signal

The power good pin (PGOOD) is an open-drain logic output that signals whether or not the ISL6312 is regulating the output voltage within the proper levels, and whether any fault conditions exist. This pin should be tied to a +5V source through a resistor.

During shutdown and soft-start PGOOD pulls low and releases high after a successful soft-start and the output voltage is operating between the undervoltage and overvoltage limits. PGOOD transitions low when an undervoltage, overvoltage, or overcurrent condition is detected or when the controller is disabled by a reset from EN, EN_PH4, POR, or one of the no-CPU VID codes. In the event of an overvoltage or overcurrent condition, the controller latches off and PGOOD will not return high until after a successful soft-start. In the case of an undervoltage event, PGOOD will return high when the output voltage returns to within the undervoltage.

REPEAT FOR

EACH CHANNEL

125μA

OCP

AVG

PGOOD

ISL6312 INTERNAL CIRCUITRY

Overvoltage Protection

The ISL6312 constantly monitors the sensed output volt age on the VDIFF pin to detect if an overvoltage event occurs. When the output voltage rises above the OVP trip level actions are taken by the ISL6312 to protect the microprocessor load. The overvoltage protection trip level changes depending on what mode of operation the controller is in and what state the OVPSEL and VRSEL pins are in. Table 6 and 7 below list what the OVP trip levels are under all conditions.

At the inception of an overvoltage event, LGATE1, LGATE2 and LGATE3 are commanded high, PWM4 is commanded low, and the PGOOD signal is driven low. This turns on the all of the lower MOSFET s and pulls the output voltage below a level that might cause damage to the load. The LGATE outputs remain high and PWM4 remains low until VDIFF falls 100mV below the OVP threshold that tripped the overvoltage protection circuitry. The ISL6312 will continue to protect the load in this fashion as long as the overvoltage condition recurs. Once an overvoltage condition ends the ISL6312 latches off, and must be reset by toggling EN, or through POR, before a soft-start can be reinitiated.

TABLE 6. INTEL VR10 AND VR11 OVP THRESHOLDS

MODE OF

OPERATION

Soft-Start (TD1 and TD2)

Soft-Start (TD3 and TD4)

Normal Operation VDAC + 175mV VDAC + 350mV

TABLE 7. AMD OVP THRESHOLDS

MODE OF

OPERATION

Soft-Start 2.200V and

Normal Operation VDAC + 250mV VDAC + 350mV

OVPSEL PIN OPEN

OR TIED TO GND

1.280V and

VDAC + 175mV

(higher of the two)

VDAC + 175mV VDAC + 350mV

OVPSEL PIN OPEN

OR TIED TO GND

VDAC + 250mV

(higher of the two)

OVPSEL PIN TIED

TO VCC

1.280V and

VDAC + 350mV

(higher of the two)

OVPSEL PIN TIED

TO VCC

2.200V and

VDAC + 350mV

(higher of the two)

One exception that overrides the overvoltage protection circuitry is a dynamic VID transition in AMD modes of operation. If a new VID code is detected during normal operation, the OVP protection circuitry is disabled from the beginning of the dynamic VID transition, until 50μs after the internal DAC reaches the final VID setting. This is the only time during operation of the ISL6312 that the OVP circuitry is not active.

Pre-POR Overvoltage Protection

Prior to PVCC and VCC exceeding their POR levels, the ISL6312 is designed to protect the load from any overvoltage events that may occur. This is accomplished by means of an internal 10kΩ resistor tied from PHASE to LGATE, which

FN9289.4

August 1, 2007

turns on the lower MOSFET to control the output voltage until the overvoltage event ceases or the input power supply cuts off. For complete protection, the low side MOSFET should have a gate threshold well below the maximum voltage rating of the load/microprocessor.

In the event that during normal operation the PVCC or VCC voltage falls back below the POR threshold, the pre-POR overvoltage protection circuitry reactivates to protect from any more pre-POR overvoltage events.

Undervoltage Detection

The undervoltage threshold is set at 60% of the VID code. When the output voltage (VSEN-RGND) is below the undervoltage threshold, PGOOD gets pulled low. No other action is taken by the controller. PGOOD will return high if the output voltage rises above 70% of the VID code.

Open Sense Line Prevention

In the case that either of the remote sense lines, VSEN or GND, become open, the ISL6312 is designed to prevent the controller from regulating. This is accomplished by means of a small 5μA pull-up current on VSEN, and a pull-down current on RGND. If the sense lines are opened at any time, the voltage difference between VSEN and RGND will increase until an overvoltage event occurs, at which point overvoltage protection activates and the controller stops regulating. The ISL6312 will be latched off and cannot be restarted until the controller is reset.

ISL6312

⎛⎞ ⎜⎟

OCP

⎝⎠

OCPIOCP min,

125 106–R

----------------------------------------------------------

DCR

ISEN

N⋅⋅ ⋅

⎛⎞

1R2

---------------------

⋅=

⎜⎟

⎝⎠

(EQ. 22)

The overcurrent trip level of the ISL6312 cannot be set any lower then the I

OCP,min

overcurrent trip level lower then I

level calculated above. If an

OCP,min

is desired, then the

ISL6312A should be used in the place of the ISL6312. At the beginning of overcurrent shutdown, the controller sets

all of the UGATE and LGATE signals low, puts PWM4 in a high-impedance state, and forces PGOOD low. This turns off all of the upper and lower MOSFET s. The system remains in this state for fixed period of 12ms. If the controller is still enabled at the end of this wait period, it will attempt a softstart. If the fault remains, the trip-retry cycles will continue indefinitely until either the controller is disabled or the fault is cleared. Note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard.

OUTPUT CURRENT, 50A/DIV

Overcurrent Protection

The ISL6312 takes advantage of the proportionality between the load current and the average current, I overcurrent condition. See “Continuous Current Sampling” on page 12 for more detail on how the average current is measured. The average current is continually compared with a constant 125μA OCP reference current as shown in Figure 14. Once the average current exceeds the OCP reference current, a comparator triggers the converter to begin overcurrent protection procedures.

This method for detecting overcurrent events limits the minimum overcurrent trip threshold because of the fact the ISL6312 uses set internal R

current sense resistors.

ISEN

The minimum overcurrent trip threshold is dictated by the DCR of the inductors and the number of active channels. To calculate the minimum overcurrent trip level, I Equation 21, where N is the number of active channels, DCR is the individual inductor ’s DCR, and R

ISEN

internal current sense resistor.

OCP min,

125 106–R

----------------------------------------------------------

DCR

ISEN

N⋅⋅ ⋅

If the desired overcurrent trip level is greater then the minimum overcurrent trip level, I

OCP,min

divider R-C circuit around the inductor shown in Figure 5 should be used to set the desired trip level.

, to detect an

AVG

OCP,min

, use

is the 300Ω

(EQ. 21)

, then the resistor

OUTPUT VOLTAGE, 500mV/DIV

FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE

3ms/DIV

Individual Channel Overcurrent Limiting

The ISL6312 has the ability to limit the current in each individual channel without shutting down the entire regulator. This is accomplished by continuously comparing the sensed currents of each channel with a constant 170μA OCL reference current as shown in Figure 14. If a channel’s individual sensed current exceeds this OCL limit, the UGATE signal of that channel is immediately forced low, and the LGATE signal is forced high. This turns off the upper MOSFET(s), turns on the lower MOSFET(s), and stops the rise of current in that channel, forcing the current in the channel to decrease. That channel’s UGATE signal will not be able to return high until the sensed channel current falls back below the 170μA reference.

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ISL6312

General Design Guide

This design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications.

Power Stages

The first step in designing a multiphase converter is to determine the number of phases. This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. Generally speaking, the most economical solutions are those in which each phase handles between 25A and 30A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heatdissipating surfaces.

MOSFETS

The choice of MOSFETs depends on the current each MOSFET will be required to conduct, the switching frequency , the capability of the MOSFETs to dissipate heat, and the availability and nature of heat sinking and air flow .

LOWER MOSFET POWER CALCULATION

The calculation for power loss in the lower MOSFET is simple, since virtually all of the loss in the lower MOSFET is due to current conducted through the channel resistance (r output current, I Equation 1), and d is the duty cycle (V

). In Equation 23, IM is the maximum continuous

DS(ON)

LOW 1,

is the peak-to-peak inductor current (see

OUT/VIN

LPP,

------------------------------------ -+⋅=

DS ON()

⎛⎞

⎜⎟

----- N

⎝⎠

1d–()⋅

(EQ. 23)

LOW 2,

DON()fS

⎛⎞

⋅⋅=

⎜⎟

------

⎝⎠

----------+

⎛⎞

⎜⎟

td1⋅

------

–

⎜⎟

⎝⎠

---------2

td2⋅+

(EQ. 24)

The total maximum power dissipated in each lower MOSFET is approximated by the summation of P

LOW,1

and P

LOW,2

UPPER MOSFET POWER CALCULATION

In addition to r

losses, a large portion of the upper-

DS(ON)

MOSFET losses are due to currents conducted across the input voltage (V

) during switching. Since a substantially

higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times, the lower-MOSFET body-diode reverserecovery charge, Q

, and the upper MOSFET r

DS(ON)

conduction loss. When the upper MOSFET turns off, the lower MOSFET does

not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 25, the required time for this commutation is t approximated associated power loss is P

UP 1,VIN

⎛⎞

⋅⋅⋅≈

----- -

⎝⎠

-------- -+

⎛⎞

----

⎜⎟

⎝⎠

and the

UP,1

(EQ. 25)

At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t approximate power loss is P

⎛⎞

UP 2,VIN

⋅⋅⋅≈

-------- -

⎜⎟

–

----- 2

⎝⎠

. In Equation 26, the

UP,2

⎛⎞

----

⎜⎟

⎝⎠

(EQ. 26)

A third component involves the lower MOSFET reverserecovery charge, Q

. Since the inductor current has fully

commutated to the upper MOSFET before the lowerMOSFET body diode can recover all of Q

, it is conducted

through the upper MOSFET across VIN. The power dissipated as a result is P

VINQrrf

UP 3,

⋅⋅=

UP,3

(EQ. 27)

An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at I frequency, f

, and the length of dead times, td1 and td2, at

, V

, the switching

D(ON)

the beginning and the end of the lower-MOSFET conduction interval respectively.

Finally, the resistive part of the upper MOSFET is given in Equation 28 as P

UP 4,rDS ON()

UP,4

⎛⎞

⎜⎟

----- N

⎝⎠

+⋅⋅≈

---------12

(EQ. 28)

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August 1, 2007

The total power dissipated by the upper MOSFET at full load can now be approximated as the summa ti on of the resu l ts from Equations 25, 26, 27 and 28. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies.

Package Power Dissipation

When choosing MOSFETs it is important to consider the amount of power being dissipated in the integrated drivers located in the controller. Since there are a total of three drivers in the controller package, the total power dissipated by all three drivers must be less than the maximum allowable power dissipation for the QFN package.

ISL6312

PVCC

BOOT

PHASE

HI1

LO1

UGATE

GI1R

FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

Calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125°C. The maximum allowable IC power dissipation for the 7x7 QFN package is approximately 3.5W at room temperature. See “Layout Considerations” on page 32 for thermal transfer improvement suggestions.

When designing the ISL6312 into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses, P

Qg_TOT

, due to the gate charge of MOSFETs and the integrated driver’s internal circuitry and their corresponding average driver current can be estimated with Equations 29 and 30, respectively.

Qg_TOTPQg_Q1PQg_Q2IQ

Qg_Q1

Qg_Q2QG2

-- -

PVCC FSWNQ1N

⋅⋅ ⋅ ⋅⋅=

PVCC FSWNQ2N

⋅⋅⋅⋅=

VCC⋅++=

(EQ. 29)

PHASE

PVCC

HI2

LO2

LGATE

GI2

FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path resistance, P P

, and in the boot strap diode, P

DR_UP

power will be dissipated by the external gate resistors (R and R

) and the internal gate resistors (R

, the lower drive path resistance,

DR_UP

BOOT

. The rest of the

and R

GI1

GI2

) of the MOSFETs. Figures 16 and 17 show the typical upper and lower gate drives turn-on transition path. The total power dissipation in the controller itself, P

, can be roughly

estimated as:

(EQ. 30)

⎛⎞

In Equations 29 and 30, P power loss and P loss; the gate charge (Q

-- -

⎝⎠

N⋅

⋅ QG2NQ2⋅+

Qg_Q2

PHASEFSWIQ

is the total upper gate drive

Qg_Q1

is the total lower gate drive power

and QG2) is defined at the

+⋅⋅=

particular gate to source drive voltage PVCC in the corresponding MOSFET data sheet; I quiescent current with no load at both drive outputs; N and N phase, respectively; N phases. The I

are the number of upper and lower MOSFETs per

VCC product is the quiescent power of the

is the number of active

PHASE

is the driver total

controller without capacitive load and is typically 75mW at 300kHz.

DRPDR_UPPDR_LOW PBOOTIQ

Qg_Q1

BOOT

DR_UP

DR_LOW

EXT1RG1

---------------------

⎛⎞

HI1

--------------------------------------

⎜⎟

⎝⎠

HI1REXT1

⎛⎞

HI2

--------------------------------------

⎜⎟

⎝⎠

HI2REXT2

GI1

-------------

LO1

----------------------------------------

LO1REXT1

LO2

----------------------------------------

LO2REXT2

EXT2RG2

VCC⋅()+++=

Qg_Q1

---------------------

⋅=

---------------------

⋅=

-------------

Qg_Q2

GI2

August 1, 2007

(EQ. 31)

FN9289.4

ISL6312

Inductor DCR Current Sensing Component Selection

The ISL6312 senses each individual channel’s inductor current by detecting the voltage across the output inductor DCR of that channel (As described in the “Continuous Current Sampling” on page 12). As Figure 18 illustrates, an R-C network is required to accurately sense the inductor DCR voltage and convert this information into a current, which is proportional to the total output current. The time constant of this R-C network must match the time constant of the inductor L/DCR.

UGATE(n)

MOSFET

DRIVER

ISL6312 INTERNAL CIRCUIT

LGATE(n)

DCR

INDUCTOR

VL(s)

VC(s)

OUT

2. Plug the inductor L and DCR component values, and the value for C

chosen in step 1, into Equation 33 to

calculate the value for R1.

3. Resistor R

⋅

DCR C

should be left unpopulated.

-------------------------

If the desired overcurrent trip level, I minimum overcurrent trip level, I

OCP,min

OCPIOCP min,

, is greater then the

OCP

, then a resistor

(EQ. 33)

divider R-C circuit should be used to set the desired trip level. Follow the steps below to choose the component

values for the resistor divider R-C current sensing network:

1. Choose an arbitrary value for C

. The recommended

value is 0.1μF.

2. Plug the inductor L and DCR component values, the value for C1 chosen in step 1, the number of active channels N, and the desired overcurrent protection level

into Equations 34 and 35 to calculate the values for

OCP

R1 and R2.

⋅

0.0375 N⋅⋅

⋅

----------------------------------------------------------------------------------

1IOCP

OCP

DCR 0.0375 N⋅–⋅()⋅

OCP

---------------------------------------

OCPIOCP min,

(EQ. 34)

(EQ. 35)

SAMPLE

SEN

VC(s)

ISEN

ISEN-(n)

ISEN+(n)

*R2 is OPTIONAL

FIGURE 18. DCR SENSING CONFIGURATION

The R-C network across the inductor also sets the overcurrent trip threshold for the regulator. Before the R-C components can be selected, the desired overcurrent protection level should be chosen. The minimum overcurrent trip threshold the controller can support is dictated by the DCR of the inductors and the number of active channels. To calculate the minimum overcurrent trip level, I

OCP,min

, use Equation 32 below, where N is the number of active channels, and DCR is the individual inductor’s DCR.

OCP min,

0.0375 N⋅

-------------------------- -

DCR

(EQ. 32)

The overcurrent trip level of the ISL6312 cannot be set any lower then the I

OCP,min

level calculated above. If the

minimum overcurrent trip level is desired, follow the steps below to choose the component values for the R-C current sensing network:

1. Choose an arbitrary value for C

. The recommended

value is 0.1μF.

Due to errors in the inductance or DCR it may be necessary to adjust the value of R

and R2 to match the time constants

correctly. The ef fects of time constant mismatch can be seen in the form of droop overshoot or undershoot during the initial load transient spike, as shown in Figure 19. Follow the steps below to ensure the R-C and inductor L/DCR time constants are matched accurately.

1. Capture a transient event with the oscilloscope set to about L/DCR/2 (sec/div). For example, with L = 1μH and DCR = 1mΩ, set the oscilloscope to 500μs/div.

2. Record ΔV1 and ΔV2 as shown in Figure 19.

ΔV

FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR

OUT

TRAN

ΔI

FN9289.4

August 1, 2007

ISL6312

3. Select new values, R constant resistors based on the original values, R and R

1NEW,

2NEW,

4. Replace R

, using Equations 36 and 37.

2,OLD

⋅=

1OLD,

⋅=

2OLD,

and R2 with the new values and check to see

1,NEW

V1Δ

----------

V1Δ

----------

and R

2,NEW

, for the time

1,OLD

(EQ. 36)

(EQ. 37)

that the error is corrected. Repeat the procedure if necessary.

Loadline Regulation Resistor

If loadline regulation is desired, the IDROOP pin should be shorted to the FB pin in order for the internal average sense current to flow out across the loadline regulation resistor, labeled R the desired loadline required for the application. The desired loadline, R where V current I

DROOP

------------------------ -= I

Based on the desired loadline, the loadline regulation resistor, RFB, can be calculated from Equation 39 or Equation 40, depending on the R-C current sense circuitry being employed. If a basic R-C sense circuit consisting of C1 and R1 is being used, use Equation 39. If a resistor divider R-C sense circuit consisting of R1, R2, and C1 is being used, use Equation 40.

in Figure 6. This resistor’s value sets

, can be calculated by Equation 38

is the desired droop voltage at the full load

(EQ. 38)

COMPENSATION WITH LOAD-LINE REGULATION

The load-line regulated converter behaves in a similar manner to a peak current mode controller because the two poles at the output filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, R

C2 (OPTIONAL)

FIGURE 20. COMPENSATION CONFIGURA TION FOR

LOAD-LINE REGULATED ISL6312 CIRCUIT

and CC.

COMP

IDROOP

VDIFF

ISL6312

Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately, there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator, by compensating the L-C poles and the ESR zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance.

RLLN 300⋅⋅

--------------------------------- -

DCR

RLLN 300 R1R2+()⋅⋅ ⋅

----------------------------------------------------------------

⋅

DCR R

In Equations 39 and 40, R

is the loadline resistance; N is

(EQ. 39)

(EQ. 40)

the number of active channels; DCR is the DCR of the individual output inductors; and R1 and R2 are the current sense R-C resistors.

If no loadline regulation is required, the IDROOP pin should be left open and not connected to anything. To choose the value for R

in this situation, please refer to the

Compensation Without Loadline Regulation section.

Compensation

The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals.

Select a target bandwidth for the compensated system, f0. The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. The values of the compensation components depend on the relationships of f0 to the L-C pole frequency and the ESR zero frequency. For each of the following three, there is a separate set of equations for the compensation components.

In Equation 41, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent series resistance of the bulk output filter capacitance; and VPP is the peak-topeak sawtooth signal amplitude as described in the “Electrical Specifications” on page 6 .

Once selected, the compensation values in Equation 41 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to RC. Slowly increase the value of RC while observing the transient performance on an oscilloscope until no further improvement is noted. Normally, CC will not need adjustment. Keep the value of CC from Equation 41 unless some performance issue is noted.

FN9289.4

August 1, 2007

ISL6312

Case 1:

Case 2:

Case 3:

------------------------------- -f 2 π LC⋅⋅⋅

CRFB

------------------------------- 2 π LC⋅⋅⋅

CRFB

2 π f0VppLC⋅⋅⋅ ⋅ ⋅

--------------------------------------------------------

⋅=

0.66 V

0.66 VIN⋅

----------------------------------------------------= 2 π V

⋅⋅ ⋅ ⋅

PPRFBf0

-------------------------------------<≤

2 π C ESR⋅⋅ ⋅

VPP2 π⋅()⋅

---------------------------------------------------------------- -

⋅=

0.66 V

-------------------------------------------------------------------------------------= 2 π⋅()

-------------------------------------> 2 π C ESR⋅⋅ ⋅

0.66 VIN⋅

VPPR

2 π f0VppL⋅⋅ ⋅ ⋅

---------------------------------------------

⋅=

0.66 V

0.66 VINESR C⋅⋅ ⋅

----------------------------------------------------------------= 2 π V

PPRFBf0

⋅

LC⋅⋅⋅

⋅

LC⋅⋅⋅ ⋅ ⋅

ESR⋅⋅

(EQ. 41)

L⋅⋅ ⋅ ⋅ ⋅

The optional capacitor C2, is sometimes needed to bypass noise away from the PWM comparator (see Figure 20). Keep a position available for C

, and be prepared to install a high-

frequency capacitor of between 22pF and 150pF in case any leading edge jitter problem is noted.

COMPENSATION WITHOUT LOAD-LINE REGULATION

The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type III controller, as shown in Figure 20, provides the necessary compensation.

The first step is to choose the desired bandwidth, f

, of the

compensated system. Choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. The type-III compensator has an extra high-frequency pole, f

. This pole can be used for

added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. A good general rule is to choose f higher if desired. Choosing f

= 10f0, but it can be

to be lower than 10f0 can

cause problems with too much phase shift below the system bandwidth.

COMP

ISL6312

IDROOP

VDIFF

FIGURE 21. COMPENSATION CIRCUIT WITHOUT LOAD-LINE

REGULATION

In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in Equation 42, R

is selected arbitrarily. The remaining

compensation components are then selected according to Equation 42.

In Equation 42, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and V

is the peak-to-

peak sawtooth signal amplitude as described in “Electrical Specifications” on page 6.

CESR⋅

--------------------------------------------

R1R

⋅=

LC⋅ C ESR⋅–

--------------------------------------------= R

-------------------------------------------------------------------------------------------------------------=

2 π⋅()

⎛⎞

VPP2π

⋅

⎝⎠

---------------------------------------------------------------------------------------- -=

0.75 V

0.75 VIN2 π f

-------------------------------------------------------------------------------------------------------------=

2 π⋅()

0.75 VIN⋅

f0f

⋅⋅ ⋅ ⋅ ⋅

f0fHFLCR

⋅⋅ ⋅⋅⋅

2 π f

f0f

⋅⋅ ⋅ ⋅ ⋅

LC⋅()RFBV

LC⋅ 1–⋅⋅ ⋅()⋅⋅

LC⋅()RFBV

PP–()

(EQ. 42)

PP–()

Output Filter Design

The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. The output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand.

FN9289.4

August 1, 2007

ISL6312

In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ΔI, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, ΔV

MAX

. Capacitors are characterized according to their capacita nce, ESR, and ESL (equivalent series inductance).

At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total outputvoltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount:

ΔVESL

-----

⋅ ESR ΔI⋅+≈

(EQ. 43)

The filter capacitor must have sufficiently low ESL and ESR so that ΔV < ΔV

MAX

Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation.

output-voltage deviation than the leading edge. Equation 46 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels.

2NCV

⋅⋅⋅

---------------------------------

1.25

-----------------------------

()

ΔI

NC⋅⋅

()

ΔI

ΔV

⋅⋅≤

MAX

ΔIESR⋅()–⋅≤

MAX

ΔI ESR⋅()– VINVO–

⎛⎞ ⎝⎠

(EQ. 45)

(EQ. 46)

Switching Frequency

There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper MOSFET loss calculation. These effects are outlined in “MOSFETs” on page 26, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small output-voltage ripple as outlined in “Compensation without load-line regulation” on page 30. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements.

Switching frequency is determined by the selection of the frequency-setting resistor, R are provided to assist in selecting the correct value for R

[]

1000

10.61 1.035 fS()log⋅()–

RT10

. Figure 22 and Equation 47

(EQ. 47)

The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current (see “Interleaving” on page 10 and Equation 2), a voltage develops across the bulk capacitor ESR equal to I

(ESR). Thus, once the output

C,PP

capacitors are selected, the maximum allowable ripple voltage, V

PP(MAX)

, determines the lower limit on the

inductance.

⎛⎞

NV⋅

–

⎝⎠

------------------------------------------------------------------- -

⋅≥

ESR

⋅⋅

SVINVPP MA X()

OUT

⋅

OUT

(EQ. 44)

Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ΔV

. This places an upper limit on inductance.

MAX

Equation 45 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater

100

(kΩ)

10 100 1000 10000

FIGURE 22. RT vs SWITCHING FREQUENCY

SWITCHING FREQUENCY (kHz)

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases.

FN9289.4

August 1, 2007

ISL6312

0.3 I

= 0

L(P-P)

)

RMS/

0.2

0.1

INPUT-CAPACITOR CURRENT (I

= 0.25 I

L(P-P)

00.4 1.00.2 0.6 0.8

L(P-P)

DUTY CYCLE (V

= 0.5 I = 0.75 I

O/VIN

)

FIGURE 23. NORMALIZED INPUT -CAP ACITOR RMS CURRENT

vs DUTY CYCLE FOR 4-PHASE CONVERTER

For a four-phase design, use Figure 23 to determine the input-capacitor RMS current requirement set by the duty cycle, maximum sustained output current (I of the peak-to-peak inductor current (I

), and the ratio

) to IO. Select a

(P-P)

bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated.

The voltage rating of the capacitors should also be at least

1.25x greater than the maximum input voltage. Figures 24 and 25 provide the same input RMS current information for three-phase and two-phase designs respectively. Use the same approach for selecting the bulk capacitor type and number.

0.3

= 0

(P-P)

)

RMS/

0.2

= 0.25 I

(P-P)

I I

L L

(P-P) (P-P)

= 0.5 I = 0.75 I

close as possible to each upper MOSFET drain to minimize board parasitics and maximize suppression.

0.3

)

RMS/

0.2

0.1

= 0

(P-P)

= 0.5 I

(P-P)

INPUT-CAPACITOR CURRENT (I

(P-P)

00.4 1.00.2 0.6 0.8

= 0.75 I

DUTY CYCLE (V

IN/VO

)

FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR 2-PHASE CONVERTER

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. Careful component selection, layout, and placement minimizes these voltage spikes. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying channel current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes.

0.1

INPUT-CAPACITOR CURRENT (I

00.4 1.00.2 0.6 0.8 DUTY CYCLE (V

IN/VO

)

FIGURE 24. NORMALIZED INPUT-CAP ACITOR RMS

CURRENT FOR 3-PHASE CONVERTER

Low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. The spikes result from the high current slew rate produced by the upper MOSFET turn on and off. Select low ESL ceramic capacitors and place one as

There are two sets of critical components in a DC/DC converter using a ISL6312 controller. The power components are the most critical because they switch large amounts of energy. Next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling.

The power components should be placed first, which include the MOSFET s, input and output capacitors, and the inductors. It is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. Symmetrical layout allows heat to be dissipated equally across all power trains. Equidistant placement of the controller to the first three power trains it controls through the integrated drivers helps keep the gate drive traces equally short, resulting in equal trace impedances and similar drive capability of all sets of MOSFETs.

FN9289.4

August 1, 2007

ISL6312

When placing the MOSFETs try to keep the source of the upper FETs and the drain of the lower FETs as close as thermally possible. Input Bulk capacitors should be placed close to the drain of the upper FETs and the source of the lower FETs. Locate the output inductors and output capacitors between the MOSFET s and the load. The high-frequency input and output decoupling capacitors (ceramic) should be placed as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to GND next or on the capacitor solder pad.

The critical small components include the bypass capacitors for VCC and PVCC, and many of the components surrounding the controller including the feedback network and current sense components. Locate the VCC/PVCC bypass capacitors as close to the ISL6312 as possible. It is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to EMI pick-up.

A multi-layer printed circuit board is recommended. Figure 26 shows the connections of the critical components for the converter. Note that capacitors C

xxIN

and C

xxOUT

could each represent numerous physical capacitors. Dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to output inductors short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring.

Routing UGATE, LGA TE, and PHASE Traces

Great attention should be paid to routing the UGATE, LGATE, and PHASE traces since they drive the power train MOSFETs using short, high current pulses. It is important to size them as large and as short as possible to reduce their overall impedance and inductance. They should be sized to carry at least one ampere of current (0.02” t o 0 . 0 5 ” ) . G o i n g between layers with vias should also be avoided, but if so, use two vias for interconnection when possible.

Extra care should be given to the LGATE traces in particular since keeping their impedance and inductance lo w helps to significantly reduce the possibility of shoot-through. It is also important to route each channels UGATE and PHASE traces in as close proximity as possible to reduce their inductances.

Current Sense Component Placement and Trace Routing

One of the most critical aspects of the ISL6312 regulator layout is the placement of the inductor DCR current sense components and traces. The R-C current sense components must be placed as close to their respective ISEN+ and ISEN- pins on the ISL6312 as possible.

The sense traces that connect the R-C sense components to each side of the output inductors should be routed on the bottom of the board, away from the noisy switching components located on the top of the board. These traces should be routed side by side, and they should be very thin traces. It’s important to route these traces as far away from any other noisy traces or planes as possible. These traces should pick up as little noise as possible.

Thermal Management

For maximum thermal performance in high current, high switching frequency applications, connecting the thermal GND pad of the ISL6312 to the ground plane with multiple vias is recommended. This heat spreading allows the part to achieve its full thermal potential. It is also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9289.4

August 1, 2007

ISL6312

(CF1)

+5V

+12V

COMP

VSEN RGND

VCC

OFS

FS REF

REF

OVPSEL

VID7

VID6

VID5

VID4

VID3

VID2 VID1 VID0

VRSEL

PGOOD

EN1

EN2

DRSEL

GND

IDROOP

VDIFF

ISL6312

LOCATE CLOSE TO IC

(MINIMIZE CONNECTION PATH)

BOOT1

UGATE1

PHASE1

LGATE1

ISEN1ISEN1+

PVCC1_2

BOOT2

UGATE2

PHASE2

LGATE2

ISEN2-

ISEN2+

PVCC3

BOOT3

UGATE3

PHASE3

LGATE3

ISEN3-

ISEN3+

EN_PH4

BOOT1

(CF2)

+12V

BOOT2

BOOT3

VCC PVCC

BOOT

ISL6612

PWM4

ISEN4-

ISEN4+

PWM

+12V

UGATE

PHASE

LGATE

GND

KEY

HEAVY TRACE ON CIRCUIT PLANE LAYER

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

BIN1

LOCATE NEAR SWITCHING TRANSISTORS;

(MINIMIZE CONNECTION PATH)

BIN2

BIN3

LOCATE NEAR LOAD;

(MINIMIZE CONNECTION

+12V

BIN4

HFOUT

)

PATH)

BOUT

LOAD

FIGURE 26. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

FN9289.4

August 1, 2007

Package Outline Drawing

L48.7x7

48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06

7.00

PIN 1

INDEX AREA

ISL6312

44X

5.5

0.50 48

PIN #1 INDEX AREA

(4X) 0.15

( 6 . 80 TYP )

( 4 . 30 )

TOP VIEW

TYPICAL RECOMMENDED LAND PATTERN

7.00

0 . 90 ± 0 . 1

( 44X 0 . 5 )

( 48X 0 . 23 )

( 48X 0 . 60 )

48X 0 . 40± 0 . 1

BOTTOM VIEW

SIDE VIEW

0 . 2 REF

DETAIL "X"

0 . 00 MIN. 0 . 05 MAX.

BASE PLANE

4. 30 ± 0 . 15

M0.10 C AB

0.23 +0.07 / -0.05

SEE DETAIL "X"

0.10

SEATING PLANE

C0.08

NOTES:

Dimensions are in millimeters.1. Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Unless otherwise specified, tolerance : Decimal ± 0.05

Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

6. located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN9289.4

August 1, 2007

Datasheet isl6312 Datasheets

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