Datasheet ISL62883BHRTZ, ISL62883HRTZ, ISL62883IRTZ Datasheet (Intersil) [ru]

Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs

ISL62883, ISL62883B

The ISL62883 is a multiphase PWM buck regulator for
miroprocessor core power supply. The multiphase buck converter
uses interleaved phase to reduce the total output voltage ripple with
each phase carrying a portion of the total load current, providing
better system performance, superior thermal management, lower
component cost, reduced power dissipation, and smaller
implementation area. The ISL62883 uses two integrated gate
drivers and an external gate driver to provide a complete solution.
The PWM modulator is based on Intersil's Robust Ripple Regulator

3

) technology™. Compared with traditional modulators, the R3™

(R
modulator commands variable switching frequency during load
transients, achieving faster transient response. With the same
modulator, the switching frequency is reduced at light load,
increasing the regulator efficiency.

The ISL62883 is fully compliant with IMVP-6.5™ specifications. It
responds to PSI# and DPRSLPVR signals by adding or dropping
PWM3 and Phase-2 respectively, adjusting overcurrent protection
threshold accordingly, and entering/exiting diode emulation mode.
It reports the regulator output current through the IMON pin. It
senses the current by using either a discrete resistor or inductor
DCR whose variation over temperature can be thermally
compensated by a single NTC thermistor. It uses differential
remote voltage sensing to accurately regulate the processor die
voltage. The adaptive body diode conduction time reduction
function minimizes the body diode conduction loss in diode
emulation mode. User-selectable overshoot reduction function
offers an option to aggressively reduce the output capacitors as
well as the option to disable it for users concerned about
increased system thermal stress. In 2-Phase configuration, the
ISL62883 offers the FB2 function to optimize 1-Phase
performance.

The ISL62883B has the same functions as the ISL62883, but
comes in a different package.

Features

• Precision Multiphase Core Voltage Regulation

- 0.5% System Accuracy Over-Temperature

- Enhanced Load Line Accuracy

• Microprocessor Voltage Identification Input

- 7-Bit VID Input, 0.300V to 1.500V in 12.5mV Steps

- Supports VID Changes On-The-Fly

• Supports Multiple Current Sensing Methods

- Lossless Inductor DCR Current Sensing

- Precision Resistor Current Sensing

• Supports PSI# and DPRSLPVR modes

• Superior Noise Immunity and Transient Response

• Current Monitor and Thermal Monitor

• Differential Remote Voltage Sensing

• High Efficiency Across Entire Load Range

• Programmable 1-, 2- or 3-Phase Operation

• Two Integrated Gate Drivers

• Excellent Dynamic Current Balance Between Phases

• FB2 Function in 2-Phase Configuration to Optimize 1-Phase
Performance

• Adaptive Body Diode Conduction Time Reduction

• User-selectable Overshoot Reduction Function

• Small Footprint 40 Ld 5x5 or 48 Ld 6x6 TQFN Package

• Pb-Free (RoHS Compliant)

Applications

• Notebook Computers

June 21, 2011
FN6891.4

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

Ordering Information

ISL62883, ISL62883B

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL62883HRTZ 62883 HRTZ -10 to +100 40 Ld 5x5 TQFN L40.5x5

ISL62883IRTZ 62883 IRTZ -40 to +100 40 Ld 5x5 TQFN L40.5x5

ISL62883BHRTZ 62883 BHRTZ -10 to +100 48 Ld 6x6 TQFN L48.6x6

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347

for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb­free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62883

TB363

.

, ISL62883B. For more information on MSL please see techbrief

Pin Configurations

N#
_E

CLK

ISEN1

R

LPV

PRS
D

VSEN

ISL62883B

(48 LD TQFN)

TOP VIEW

6

_ON
VR

RTN

VID

VID5

(BOTTOM)

ISUM-

ISUM+

D4
VI

VDD

ID3VID2
V

NC

VIN

D1
VI

IMON

ID0
V

38 37

23 24

NC

NC

36

35

34

33

32

31

30

29

28

27

26

25

BOOT1

BOOT2
UGATE2

PHASE2

VSSP2

LGATE2

NC

VCCP

PWM3

LGATE1

VSSP1

PHASE1

UGATE1

PGOOD

PSI#

RBIAS

VR_TT#

NTC

VW

COMP

FB

SEN3/FB2

ISEN2

ISL62883

(40 LD TQFN)

TOP VIEW

R
V

#

P

N

L

N

E

S

_

O

R

_

K
L

P

R
V

C

D

39 38 37 36 35 34 33 32 31

40

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

RTN

VSEN

ISEN1

6

5

D

D

I

I

V

V

GND PAD

(BOTTOM)

ISUM-

ISUM+

4
D

I
V

VDD

2

1

3
D

I
V

VIN

D

I
V

IMON

0

D

D

I

I

V

V

BOOT1

UGATE1

30

29

28

27

26

25

24

23

22

21

BOOT2

UGATE2

PHASE2

VSSP2

LGATE2

VCCP

PWM3

LGATE1

VSSP1

PHASE1

NC

PGOOD

PSI#

RBIAS

VR_TT#

NTC

GND

VW

COMP

FB

ISEN3/FB2

NC

NC

48

47 46 45 44 43 42 41 40 39

1

2

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22

ISEN2

2

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Pin Function Descriptions

GND

Signal common of the IC. Unless otherwise stated, signals are
referenced to the GND pin.

PGOOD

Power-Good open-drain output indicating when the regulator is
able to supply regulated voltage. Pull-up externally with a 680Ω
resistor to VCCP or 1.9kΩ to 3.3V.

PSI#

Low load current indicator input. When asserted low, indicates a
reduced load-current condition. For ISL62883, when PSI# is
asserted low, PWM3 will be disabled.

RBIAS

147k resistor to GND sets internal current reference.

VR_TT#

Thermal overload output indicator.

NTC

Thermistor input to VR_TT# circuit.

VW

A resistor from this pin to COMP programs the switching
frequency (8kΩ gives approximately 300kHz).

COMP

This pin is the output of the error amplifier. Also, a resistor across
this pin and GND adjusts the overcurrent threshold.

FB

This pin is the inverting input of the error amplifier.

ISEN3/FB2

When the ISL62883 is configured in 3-phase mode, this pin is
ISEN3. ISEN3 is the individual current sensing for phase 3. When
the ISL62883 is configured in 2-phase mode, this pin is FB2.
There is a switch between the FB2 pin and the FB pin. The switch
is on in 2-phase mode and is off in 1-phase mode. The
components connecting to FB2 are used to adjust the
compensation in 1-phase mode to achieve optimum
performance.

ISEN2

Individual current sensing for Phase-2. When ISEN2 is pulled to
5V VDD, the controller will disable Phase-2 and allow other
phases to operate.

ISEN1

Individual current sensing for Phase-1.

RTN

Remote voltage sensing return. Connect to ground at
microprocessor die.

ISUM- and ISUM+

Droop current sense input.

VDD

5V bias power.

VIN

Battery supply voltage, used for feed-forward.

IMON

An analog output. IMON outputs a current proportional to the
regulator output current.

BOOT1

Connect an MLCC capacitor across the BOOT1 and the PHASE1
pins. The boot capacitor is charged through an internal boot
diode connected from the VCCP pin to the BOOT1 pin, each time
the PHASE1 pin drops below VCCP minus the voltage dropped
across the internal boot diode.

UGATE1

Output of the Phase-1 high-side MOSFET gate driver. Connect the
UGATE1 pin to the gate of the Phase-1 high-side MOSFET.

PHASE1

Current return path for the Phase-1 high-side MOSFET gate driver.
Connect the PHASE1 pin to the node consisting of the high-side
MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-1.

VSSP1

Current return path for the Phase-1 low-side MOSFET gate driver.
Connect the VSSP1 pin to the source of the Phase-1 low-side
MOSFET through a low impedance path, preferably in parallel
with the trace connecting the LGATE1 pin to the gate of the
Phase-1 low-side MOSFET.

LGATE1

Output of the Phase-1 low-side MOSFET gate driver. Connect the
LGATE1 pin to the gate of the Phase-1 low-side MOSFET.

PWM3

PWM output for Channel 3. When PWM3 is pulled to 5V VDD, the
controller will disable Phase-3 and allow other phases to operate.

VCCP

Input voltage bias for the internal gate drivers. Connect +5V to
the VCCP pin. Decouple with at least 1µF of an MLCC capacitor to
VSSP1 and VSSP2 pins respectively.

VSEN

Remote core voltage sense input. Connect to microprocessor die.

3

LGATE2

Output of the Phase-2 low-side MOSFET gate driver. Connect the
LGATE2 pin to the gate of the Phase-2 low-side MOSFET.

FN6891.4

June 21, 2011

ISL62883, ISL62883B

VSSP2

Current return path for the Phase-2 converter low-side MOSFET
gate driver. Connect the VSSP2 pin to the source of the Phase-2
low-side MOSFET through a low impedance path, preferably in
parallel with the trace connecting the LGATE2 pin to the gate of
the Phase-2 low-side MOSFET.

PHASE2

Current return path for the Phase-2 high-side MOSFET gate driver.
Connect the PHASE2 pin to the node consisting of the high-side
MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-2.

UGATE2

Output of the Phase-2 high-side MOSFET gate driver. Connect the
UGATE2 pin to the gate of the Phase-2 high-side MOSFET.

BOOT2

Connect an MLCC capacitor across the BOOT2 and the PHASE2
pins. The boot capacitor is charged through an internal boot
diode connected from the VCCP pin to the BOOT2 pin, each time
the PHASE2 pin drops below VCCP minus the voltage dropped
across the internal boot diode.

VID0, VID1, VID2, VID3, VID4, VID5, VID6

VID input with VID0 = LSB and VID6 = MSB.

VR_ON

Voltage regulator enable input. A high level logic signal on this
pin enables the regulator.

DPRSLPVR

Deeper sleep enable signal. A high level logic signal on this pin
indicates that the microprocessor is in deeper sleep mode.

CLK_EN#

Open drain output to enable system PLL clock. It goes low 13
switching cycles after V

is within 10% of V

core

boot

.

NC

No Connect.

BOTTOM (on ISL62883B)

The bottom pad of ISL62883B is electrically connected to the
GND pin inside the IC.

4

FN6891.4

June 21, 2011

Block Diagram

Σ

ISL62883, ISL62883B

VR_ON

PSI#

DPRSLPVR

RBIAS

VID0

VID1

VID2

VID3

VID4

VID5

VID6

RTN

FB

COMP

VW

IMON

ISUM+

ISUM-

MODE

CONTROL

DAC
AND

SOFT

START

IMON

IDROOP

CURRENT

SENSE

Σ

VIN

VSEN

ISEN1 ISEN3 ISEN2

VIN

CLOCK

VDAC

COMP VW

E/A

2.5X

CURRENT
BALANCE

IBAL

PROTECTION

WOC OC

WOC

CURRENT
COMPARATORS

OC

PGOOD CLK_EN#

PGOOD &
CLK_EN#

LOGIC

FLT

IBAL VIN VDAC

MODULATOR

COMP

COMP

IBAL VIN VDAC

MODULATOR

COMP

IBAL VIN VDAC

MODULATOR

COMP

NUMBER OF

PHASES

GAIN

SELECT

60UA

6µA

54µA

1.24V

DRIVER

SHOOT THROUGH

PROTECTION

PWM CONTROL LOGIC

DRIVER

SHOOT THROUGH

PROTECTION

PWM CONTROL LOGIC

ADJ. OCP

THRESHOLD

1.20V

DRIVER

DRIVER

VDD

COMP

VR_TT#

NTC

BOOT2

UGATE2

PHASE2

LGATE2

VSSP2

PWM3

BOOT1

UGATE1

PHASE1

VCCP

LGATE1

VSSP1

GND

5

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V

Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V

Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V

Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)

Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)

UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . PHASE - 0.3V (DC) to BOOT

. . . . . . . . . . . . . . . . . . . . . . . PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT

LGATE Voltage (LGATE). . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to VDD + 0.3V

. . . . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)

Open Drain Outputs, PGOOD, VR_TT#,

CLK_EN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.

NOTES:

4. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

5. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Thermal Resistance (Typical) θ

40 Ld TQFN Package (Notes 4, 5) . . . . . . . 32 3

48 Ld TQFN Package (Notes 4, 5) . . . . . . . 29 2

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

(°C/W) θJC (°C/W)

JA

Recommended Operating Conditions

Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 25V

Ambient Temperature

ISL62883HRTZ, ISL62883BHRTZ . . . . . . . . . . . . . . . . .-10°C to +100°C

ISL62883IRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C

Junction Temperature

ISL62883HRTZ, ISL62883BHRTZ . . . . . . . . . . . . . . . . .-10°C to +125°C

ISL62883IRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Electrical Specifications Operating Conditions: VDD = 5V, T

limits apply over the operating temperature range, -40°C to +100°C.

PARAMETER SYMBOL TEST CONDITIONS

INPUT POWER SUPPLY

+5V Supply Current I

Battery Supply Current I

V

Input Resistance R

IN

Power-On-Reset Threshold POR

VDD

VIN

VIN

POR

SYSTEM AND REFERENCES

System Accuracy HRTZ

V

BOOT

Maximum Output Voltage V

Minimum Output Voltage V

R

Voltage R

BIAS

%Error (V

IRTZ

%Error (V

CC_CORE(max)

CC_CORE(min)

CC_CORE

CC_CORE

VR_ON = 1V 4 4.6 mA

VR_ON = 0V 1 µA

VR_ON = 0V 1 µA

VR_ON = 1V 900 kΩ

VDD rising 4.35 4.5 V

r

VDD falling 4.00 4.15 V

f

No load; closed loop, active mode range

)

VID = 0.75V to 1.50V

VID = 0.5V to 0.7375V -8 +8 mV

VID = 0.3V to 0.4875V -15 +15 mV

No load; closed loop, active mode range

)

VID = 0.75V to 1.50V

VID = 0.5V to 0.7375V -10 +10 mV

VID = 0.3V to 0.4875V -18 +18 mV

VID = [0000000] 1.500 V

VID = [1100000] 0.300 V

= 147kΩ 1.45 1.47 1.49 V

BIAS

= -40°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface

A

MIN

(Note 6) TYP

-0.5 +0.5 %

-0.8 +0.8 %

1.0945 1.100 1.1055 V

MAX

(Note 6) UNITS

6

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Electrical Specifications Operating Conditions: VDD = 5V, T

= -40°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface

A

limits apply over the operating temperature range, -40°C to +100°C. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 6) TYP

MAX

(Note 6) UNITS

CHANNEL FREQUENCY

Nominal Channel Frequency f

SW(nom)

Rfset = 7kΩ, 3 channel operation, V

= 1V 285 300 315 kHz

COMP

Adjustment Range 200 500 kHz

AMPLIFIERS

Current-Sense Amplifier Input Offset I

Error Amp DC Gain A

v0

Error Amp Gain-Bandwidth Product GBW C

= 0A -0.15 +0.15 mV

FB

90 dB

= 20pF 18 MHz

L

ISEN

Imbalance Voltage Maximum of ISENs - Minimum of ISENs 1 mV

Input Bias Current 20 nA

POWER GOOD AND PROTECTION MONITORS

PGOOD Low Voltage V

PGOOD Leakage Current I

OL

OH

I

= 4mA 0.26 0.4 V

PGOOD

PGOOD = 3.3V -1 1 µA

PGOOD Delay tpgd CLK_EN# LOW to PGOOD HIGH 6.3 7. 6 8.9 ms

GATE DRIVER

UGATE Pull-Up Resistance R

UGATE Source Current I

UGATE Sink Resistance R

UGATE Sink Current I

LGATE Pull-Up Resistance R

LGATE Source Current I

LGATE Sink Resistance R

LGATE Sink Current I

UGATE to LGATE Deadtime t

LGATE to UGAT E De adtim e t

UGPU

UGSRC

UGPD

UGSNK

LGPU

LGSRC

LGPD

LGSNK

UGFLGR

LGFUGR

200mA Source Current 1.0 1.5 Ω

UGATE - PHASE = 2.5V 2.0 A

250mA Sink Current 1.0 1.5 Ω

UGATE - PHASE = 2.5V 2.0 A

250mA Source Current 1.0 1.5 Ω

LGATE - VSSP = 2.5V 2.0 A

250mA Sink Current 0.5 0.9 Ω

LGATE - VSSP = 2.5V 4.0 A

UGATE falling to LGATE rising, no load 23 ns

LGATE falling to UGATE rising, no load 28 ns

BOOTSTRAP DIODE

Forward Voltage V

Reverse Leakage I

F

R

PVCC = 5V, IF = 2mA 0.58 V

VR = 25V 0.2 µA

PROTECTION

Overvoltage Threshold OV

Severe Overvoltage Threshold OV

OC Threshold Offset at Rcomp = Open
Circuit

H

HS

VSEN rising above setpoint for >1ms 150 195 240 mV

VSEN rising for >2µs 1.525 1.55 1.575 V

3-phase configuration, ISUM- pin current 28.4 30.3 32.2 µA

2-phase configuration, ISUM- pin current 18.3 20.2 22.1 µA

1-phase configuration, ISUM- pin current 8.2 10.1 12.0 µA

Current Imbalance Threshold One ISEN above another ISEN for >1.2ms 9 mV

Undervoltage Threshold UV

f

VSEN falling below setpoint for >1.2ms -355 -295 -235 mV

LOGIC THRESHOLDS

VR_ON Input Low V

IL(1.0V)

0.3 V

7

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Electrical Specifications Operating Conditions: VDD = 5V, T

= -40°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface

A

limits apply over the operating temperature range, -40°C to +100°C. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

VR_ON Input High HRTZ

VID0-VID6, PSI#, and DPRSLPVR Input
Low

VID0-VID6, PSI#, and DPRSLPVR Input
High

PWM

PWM3 Output Low V

PWM3 Output High V

PWM Tri-State Leakage PWM = 2.5V 2 µA

THERMAL MONITOR

NTC Source Current NTC = 1.3V 53 60 67 µA

Over-Temperature Threshold V (NTC) falling 1.18 1.2 1.22 V

VR_TT# Low Output Resistance R

CLK_EN# OUTPUT LEVELS

CLK_EN# Low Output Voltage V

CLK_EN# Leakage Current I

V

IH(1.0V)

IRTZ

V

IH(1.0V)

V

IL(1.0V)

V

IH(1.0V)

OL(5.0V)

OH(5.0V)

TT

OL

OH

Sinking 5mA 1.0 V

Sourcing 5mA 3.5 V

I = 20mA 6.5 9 Ω

I = 4mA 0.26 0.4 V

CLK_EN# = 3.3V -1 1 µA

MIN

(Note 6) TYP

0.7 V

0.75 V

0.7 V

MAX

(Note 6) UNITS

0.3 V

CURRENT MONITOR

IMON Output Current I

IMON Clamp Voltage V

Current Sinking Capability 275 µA

IMON

IMONCLAMP

ISUM- pin current = 20μA 108 120 132 µA

ISUM- pin current = 10μA 51 60 69 µA

ISUM- pin current = 5μA 22 30 37.5 µA

1.1 1.15 V

INPUTS

VR_ON Leakage Current I

VIDx Leakage Current I

PSI# Leakage Current I

DPRSLPVR Leakage Current I

DPRSLPVR

VR_ON

VIDx

PSI#

VR_ON = 0V -1 0µA

VR_ON = 1V 0 1 µA

VIDx = 0V -1 0µA

VIDx = 1V 0.45 1 µA

PSI# = 0V -1 0µA

PSI# = 1V 0.45 1 µA

DPRSLPVR = 0V -1 0µA

DPRSLPVR = 1V 0.45 1 µA

SLEW RATE

Slew Rate (For VID Change) SR 56.5mV/µs

NOTE:

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.

8

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Gate Driver Timing Diagram

PWM

t

LGFUGR

UGATE

t

RU

1V

t

FU

LGATE

1V

t

t

FL

t

UGFLGR

RL

9

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Simplified Application Circuits

V+5 Vin

V+5

VCCP

ISL62883

VSS

VINVDD

PWM3

ISEN3

BOOT2

UGATE2

PHASE2

LGATE2

VSSP2

ISEN2

BOOT1

UGATE1

PHASE1

LGATE1

VSSP1

ISEN1

ISUM+

ISUM-

PGOOD

CLK_EN#

VID<0:6>

PSI#

DPRSLPVR

VR_ON

Rdroop

VCCSENSE
VSSSENSE

IMON

Rbias

Rntc

o

C

Rimon

Rfset

RBIAS

NTC

PGOOD
VR_TT#VR_TT#
CLK_EN#

VIDs
PSI#
DPRSLPVR
VR_ON
VW

COMP

FB

VSEN

RTN

IMON

(Bottom Pad)

Cis

Ris

V+5

FCCM

ISL6208

PWM

Cs3

Cs2

Cs1

Cn

Ri

VCC

GND

UGATE
PHASE

BOOT

LGATE

o

Rs3

Rs2

Rs1

C

Rn

Rsum3

Rsum2

Rsum1

Vin

L3

L2

L1

V

o

PGOOD

CLK_EN#

VID<0:6>

PSI#

DPRSLPVR

VR_ON

Rdroop

VCCSENSE
VSSSENSE

IMON

Rbias

Rntc

o

C

Rimon

FIGURE 1. TYPICAL APPLICATION CIRCUIT USING DCR SENSING

FCCM

PWM

Cs3

Cs2

Cs2

Cn

Ri

V+5

VCC

ISL6208

LGATE

GND

UGATE
PHASE

BOOT

Vin

L3

Rs3

L2

Rs2

L1

Rs1

Rsum3

Rsum2

Rsum1

Rfset

V+5 Vin

RBIAS

NTC

PGOOD
VR_TT#VR_TT#
CLK_EN#
VIDs
PSI#
DPRSLPVR
VR_ON
VW

ISL62883

COMP

FB

VSEN

RTN

IMON

(Bottom Pad)

V+5

VCCP

VSS

VINVDD

PWM3

ISEN3

BOOT2

UGATE2

PHASE2

LGATE2

VSSP2

ISEN2

BOOT1

UGATE1

PHASE1

LGATE1

VSSP1

ISEN1

ISUM+

ISUM-

Ris

Cis

Rsen3

Rsen2

Rsen1

V

o

FIGURE 2. TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING

10

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Theory of Operation

Multiphase R

MASTER

CLOCK

gmVo

Vcrs1

Crs1

Vcrs2

Crs2

Vcrs3

Crs3

VW

Vcrm

COMP

Master

Clock

Clock1

PWM1

Clock2

PWM2

Clock3

PWM3

FIGURE 4. R

3

™

Modulator

MASTER CLOCK CIRCUIT

VW

COMP

Vcrm

Crm

VW

VW

VW

FIGURE 3. R

MASTER

CLOCK

Phase

Sequencer

SLAVE CIRCUIT 1

Clock1

gm

SLAVE CIRCUIT 2

Clock2

gm

SLAVE CIRCUIT 3

Clock3

gm

3

PWM1

S

Q

R

PWM2

S

Q

R

PWM3

S

Q

R

™ MODULATORCIRCUIT

VW

Vcrs3

Vcrs2 Vcrs1

3

™ MODULATOR OPERATION PRINCIPLES IN

STEADY STATE

Phase1

Phase2

Phase3

Hysteretic

Window

Clock1
Clock2
Clock3

L1

I

L1

L2

I

L2

L3

I

L3

Vo

Co

VW

COMP

Vcrm

Master

Clock

Clock1

PWM1

Clock2

PWM2

Clock3

PWM3

VW

Vcrs1

Vcrs3

Vcrs2

FIGURE 5. R

3

™ MODULATOROPERATION PRINCIPLES IN LOAD

INSERTION RESPONSE

The ISL62883 is a multiphase regulator, which implements Intel™
IMVP-6.5™ protocol. It can be programmed for 1-, 2- or 3-phase
operation for microprocessor core applications. It uses Intersil
patented R

3

™ (Robust Ripple Regulator™) modulator. The R3™
modulator combines the best features of fixed frequency PWM
and hysteretic PWM while eliminating many of their shortcomings.
Figure 3 conceptually shows the ISL62883 multiphase R

3

™

modulator circuit, and Figure 4 shows the operation principles.

A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called VW window in the following discussion.

Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C
to gmVo, where gm is a gain factor. Crm voltage V

with a current source equal

rm

crm

is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a one­shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If the ISL62883 is in
3-phase mode, the master clock signal will be distributed to the
three phases, and the Clock1~3 signals will be 120° out-of­phase. If the ISL62883 is in 2-phase mode, the master clock
signal will be distributed to Phases 1 and 2, and the Clock1 and
Clock2 signals will be 180° out-of-phase. If the ISL62883 is in
1-phase mode, the master clock signal will be distributed to
Phases 1 only and be the Clock1 signal.

Each slave circuit has its own ripple capacitor C

, whose voltage

rs

mimics the inductor ripple current. A gm amplifier converts the
inductor voltage into a current source to charge and discharge

. The slave circuit turns on its PWM pulse upon receiving the

C

rs

clock signal, and the current source charges Crs. When Crs

11

FN6891.4

June 21, 2011

ISL62883, ISL62883B

voltage V

hits VW, the slave circuit turns off the PWM pulse,

Crs

and the current source discharges Crs.

Since the ISL62883 works with V

, which are large-amplitude

crs

and noise-free synthesized signals, the ISL62883 achieves lower
phase jitter than conventional hysteretic mode and fixed PWM
mode controllers. Unlike conventional hysteretic mode
converters, the ISL62883 has an error amplifier that allows the
controller to maintain a 0.5% output voltage accuracy.

Figure 5 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency, which allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the VW voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the ISL62883 excellent
response speed.

The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.

Diode Emulation and Period Stretching

Phase

UGATE

LGATE

IL

FIGURE 6. DIODE EMULATION

ISL62883 can operate in diode emulation (DE) mode to improve
light load efficiency. In DE mode, the low-side MOSFET conducts
when the current is flowing from source to drain and doesn’t not
allow reverse current, emulating a diode. As Figure 6 shows, when
LGATE is on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage drop across
the ON-resistance. The ISL62883 monitors the current through
monitoring the phase node voltage. It turns off LGATE when the
phase node voltage reaches zero to prevent the inductor current
from reversing the direction and creating unnecessary power loss.

If the load current is light enough, as Figure 6 shows, the inductor
current will reach and stay at zero before the next phase node
pulse, and the regulator is in discontinuous conduction mode
(DCM). If the load current is heavy enough, the inductor current
will never reach 0A, and the regulator is in CCM although the
controller is in DE mode.

CCM/DCM BOUNDARY
VW

Vcrs

iL

LIGHT DCM

VW

Vcrs

iL

DEEP DCM

Vcrs

iL

VW

FIGURE 7. PERIOD STRETCHING

Figure 7 shows the operation principle in diode emulation mode at
light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size, therefore is the same, making the inductor current
triangle the same in the three cases. The ISL62883 clamps the
ripple capacitor voltage V
inductor current. It takes the COMP voltage longer to hit V

in DE mode to make it mimic the

crs

crs

,
naturally stretching the switching period. The inductor current
triangles move further apart from each other such that the
inductor current average value is equal to the load current. The
reduced switching frequency helps increase light load efficiency.

Start-up Timing

With the controller's VDD voltage above the POR threshold, the
start-up sequence begins when VR_ON exceeds the 3.3V logic
high threshold. The ISL62883 uses digital soft start to ramp up
DAC to the boot voltage of 1.1V at about 2.5mV/µs. Once the
output voltage is within 10% of the boot voltage for 13 PWM
cycles (43µs for frequency = 300kHz), CLK_EN# is pulled low and
DAC slews at 5mV/µs to the voltage set by the VID pins. PGOOD
is asser ted high in approximately 7ms. Figure 8 shows the typical
start-up timing. Similar results occur if VR_ON is tied to V
the soft-start sequence starting 120µs after V

crosses the

DD

POR threshold.

VDD

VR_ON

2.5mV/µs

800µs

DAC

CLK_EN#

PGOOD

FIGURE 8. SOFT-START WAVEFORMS

5mV/µs

VBOOT

90%

13 SWITCHING

CYCLES

VID
COMMAND
VOLTAGE

~7ms

DD

, with

12

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Voltage Regulation and Load Line
Implementation

After the start sequence, the ISL62883 regulates the output
voltage to the value set by the VID inputs per Table 1. The
ISL62883 will control the no-load output voltage to an accuracy of
±0.5% over the range of 0.75V to 1.5V. A differential amplifier
allows voltage sensing for precise voltage regulation at the
microprocessor die.

TAB LE 1 . V ID TA BLE

VID6 VID5 VID4 VID3 VID2 VID1 VID0 V

00000001.5000

00000011.4875

00000101.4750

00000111.4625

00001001.4500

00001011.4375

00001101.4250

00001111.4125

00010001.4000

00010011.3875

00010101.3750

00010111.3625

00011001.3500

00011011.3375

00011101.3250

00011111.3125

00100001.3000

00100011.2875

00100101.2750

00100111.2625

00101001.2500

00101011.2375

00101101.2250

00101111.2125

00110001.2000

00110011.1875

00110101.1750

00110111.1625

00111001.1500

00111011.1375

00111101.1250

00111111.1125

01000001.1000

01000011.0875

01000101.0750

01000111.0625

(V)

O

TAB LE 1 . V ID TA BLE

VID6 VID5 VID4 VID3 VID2 VID1 VID0 VO (V)

01001001.0500

01001011.0375

01001101.0250

01001111.0125

01010001.0000

01010010.9875

01010100.9750

01010110.9625

01011000.9500

01011010.9375

01011100.9250

01011110.9125

01100000.9000

01100010.8875

01100100.8750

01100110.8625

01101000.8500

01101010.8375

01101100.8250

01101110.8125

01110000.8000

01110010.7875

01110100.7750

01110110.7625

01111000.7500

01111010.7375

01111100.7250

01111110.7125

10000000.7000

10000010.6875

10000100.6750

10000110.6625

10001000.6500

10001010.6375

10001100.6250

10001110.6125

10010000.6000

10010010.5875

10010100.5750

10010110.5625

10011000.5500

10011010.5375

10011100.5250

(Continued)

13

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Σ

TABLE 1. VID TABLE

VID6 VID5 VID4 VID3 VID2 VID1 VID0 VO (V)

10011110.5125

10100000.5000

10100010.4875

10100100.4750

10100110.4625

10101000.4500

10101010.4375

10101100.4250

10101110.4125

10110000.4000

10110010.3875

10110100.3750

10110110.3625

10111000.3500

10111010.3375

10111100.3250

10111110.3125

11000000.3000

11000010.2875

11000100.2750

11000110.2625

11001000.2500

11001010.2375

11001100.2250

11001110.2125

11010000.2000

11010010.1875

11010100.1750

11010110.1625

11011000.1500

11011010.1375

11011100.1250

11011110.1125

11100000.1000

11100010.0875

11100100.0750

11100110.0625

11101000.0500

11101010.0375

11101100.0250

11101110.0125

11110000.0000

11110010.0000

(Continued)

TAB LE 1 . V ID TA BLE

VID6 VID5 VID4 VID3 VID2 VID1 VID0 VO (V)

11110100.0000

11110110.0000

11111000.0000

11111010.0000

11111100.0000

11111110.0000

FB

IDROOP

COMP

FIGURE 9. DIFFERENTIAL SENSING AND LOAD LINE

E/A

VDAC

INTERNAL TO IC

IMPLEMENTATION

RDROOP

VDROOP

DAC

X 1

(Continued)

VIDS

RTN

VSS

VCC

“CATCH”

RESISTOR

VID<0:6>

VSS

“CATCH”

RESISTOR

SENSE

VR LOCAL

VO

SENSE

As the load current increases from zero, the output voltage will
droop from the VID table value by an amount proportional to the
load current to achieve the load line. The ISL62883 can sense the
inductor current through the intrinsic DC Resistance (DCR)
resistance of the inductors Figure 1 shows on page 10 or through
resistors in series with the inductors as Figure 2 shows also on
page 10. In both methods, capacitor C

voltage represents the

n

inductor total currents. A droop amplifier converts Cn voltage into
an internal current source with the gain set by resistor Ri. The
current source is used for load line implementation, current
monitor and overcurrent protection.

Figure 9 shows the load line implementation. The ISL62883
drives a current source I

out of the FB pin, described by

droop

Equation 1.

2xV

Cn

=

----------------

R

i

(EQ. 1)

I

droop

When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding thus sustaining the load line accuracy with
reduced cost.

I

flows through resistor R

droop

and creates a voltage drop

droop

of:

V

droopRdroopIdroop

V

is the droop voltage required to implement load line.

droop

Changing R
slope. Since I
recommended to first scale I
then select an appropriate R

×=

or scaling I

droop

also sets the overcurrent protection level, it is

droop

can both change the load line

droop

based on OCP requirement,

droop

value to obtain the desired

droop

(EQ. 2)

load line slope.

14

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Differential Sensing

Figure 9 also shows the differential voltage sensing scheme.
VCC

SENSE

and VSS

are the remote voltage sensing signals

SENSE

from the processor die. A unity gain differential amplifier senses the
VSS

voltage and add it to the DAC output. The error amplifier

SENSE

regulates the inverting and the non-inverting input voltages to be
equal as shown in Equation 3:

VCC

SENSE

V+

droop

V

DAC

+=

VSS

SENSE

(EQ. 3)

Rewriting Equation 3 and substitution of Equation 2 gives:

VCC

SENSE

VSS

– V

SENSE

DACRdroopIdroop

×–=

(EQ. 4)

Equation 4 is the exact equation required for load line
implementation.

The VCC

SENSE

and VSS

signals come from the processor

SENSE

die. The feedback will be open circuit in the absence of the
processor. As shown in Figure 9, it is recommended to add a
“catch” resistor to feed the VR local output voltage back to the
compensator, and add another “catch” resistor to connect the VR
local output ground to the RTN pin. These resistors, typically
10Ω~100Ω, will provide voltage feedback if the system is
powered up without a processor installed.

Phase Current Balancing

Rdcr3

L3

Phase3

ISEN3

INTERNAL

TO IC

ISEN2

ISEN1

Rs

Cs

Phase2

Rs

Cs

Phase1

Rs

Cs

FIGURE 10. CURRENT BALANCING CIRCUIT

IL3

L2

IL2

L1

IL1

The ISL62883 monitors individual phase average current by
monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 10
shows the current balancing circuit recommended for ISL62883.
Each phase node voltage is averaged by a low-pass filter
consisting of R

should be routed to inductor phase-node pad in order to

pin. R

s

and Cs, and presented to the corresponding ISEN

s

eliminate the effect of phase node parasitic PCB DCR.
Equations 5 thru 7 give the ISEN pin voltages:

V

ISEN1

V

ISEN2

V

ISEN3

where R
and R

R

+()IL1×=

dcr1Rpcb1

R

+()IL2×=

dcr2Rpcb2

R

+()IL3×=

dcr3Rpcb3

, R

dcr2

and R

dcr1

are parasitic PCB DCR between the inductor output

pcb3

are inductor DCR; R

dcr3

side pad and the output voltage rail; and I
inductor average currents.

Rpcb3

Rdcr2

Rpcb2

Rdcr1

Rpcb1

pcb1

, IL2 and IL3 are

L1

(EQ. 5)

(EQ. 6)

(EQ. 7)

, R

pcb2

V

o

The ISL62883 will adjust the phase pulse-width relative to the
other phases to make V

ISEN1=VISEN2=VISEN3

IL1=IL2=IL3, when there are R
R

pcb1=Rpcb2=Rpcb3

.

dcr1=Rdcr2=Rdcr3

, thus to achieve

and

Using same components for L1, L2 and L3 will provide a good
match of R

, R

R

pcb1

pcb2

dcr1

and R

and R

dcr2

. It is recommended to have symmetrical

pcb3

. Board layout will determine

dcr3

, R

layout for the power delivery path between each inductor and the

V3n

V2n

V1n

Rpcb3

Rpcb2

Rpcb1

.

V

o

output voltage rail, such that R

Phase3

ISEN3

Cs

INTERNAL

TO IC

Phase2

ISEN2

Cs

Phase1

ISEN1

Cs

FIGURE 11. DIFFERENTIAL-SENSING CURRENT BALANCING

CIRCUIT

pcb1=Rpcb2=Rpcb3

V3p

Rs

Rs

Rs

V2p

Rs

Rs

Rs

V1p

Rs

Rs

Rs

L3

L2

L1

Rdcr3

IL3

Rdcr2

IL2

Rdcr1

IL1

Sometimes, it is difficult to implement symmetrical layout. For
the circuit shown in Figure 10, asymmetric layout causes
different R

pcb1

, R

pcb2

and R

thus current imbalance.

pcb3

Figure 11 shows a differential-sensing current balancing circuit
recommended for ISL62883. The current sensing traces should
be routed to the inductor pads so they only pick up the inductor
DCR voltage. Each ISEN pin sees the average voltage of three
sources: its own phase inductor phase-node pad, and the other
two phases inductor output side pads. Equations 8 thru 10 give
the ISEN pin voltages:

V

ISEN1V1pV2nV3n

V

ISEN2V1nV2pV3n

V

ISEN3V1nV2nV3p

The ISL62883 will make V

++ V1nV2pV

V

1pV2nV3n

++ V1nV2nV

V

1nV2pV3n

++=

++=

++=

++=

++=

ISEN1

= V

3n

3p

ISEN2

= V

ISEN3

(EQ. 8)
(EQ. 9)

(EQ. 10)

as in:

(EQ. 11)

(EQ. 12)

Rewriting Equation 11 gives:

– V2pV2n–=

V

1pV1n

(EQ. 13)

and rewriting Equation 12 gives:

V

– V3pV3n–=

2pV2n

(EQ. 14)

Combining Equations 13 and 14 gives:

– V2pV2n– V3pV3n–==

V

1pV1n

(EQ. 15)

Therefore:

R

× R

dcr1IL1

× R

dcr2IL2

×==

dcr3IL3

(EQ. 16)

15

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Current balancing (IL1=IL2=IL3) will be achieved when there is
R

dcr1=Rdcr2=Rdcr3

. R

pcb1

, R

pcb2

and R

will not have any

pcb3

effect.

REP RATE = 10kHz

REP RATE = 25kHz

REP RATE = 50kHz

Since the slave ripple capacitor voltages mimic the inductor
currents, R3™ modulator can naturally achieve excellent current
balancing during steady state and dynamic operations. Figure 12
shows current balancing performance of the ISL62883
evaluation board with load transient of 12A/51A at different rep
rates. The inductor currents follow the load current dynamic
change with the output capacitors supplying the difference. The
inductor currents can track the load current well at low rep rate,
but cannot keep up when the rep rate gets into the hundred-kHz
range, where it’s out of the control loop bandwidth. The controller
achieves excellent current balancing in all cases.

CCM Switching Frequency

The R
sets the VW windows size, therefore sets the switching frequency.
When the ISL62883 is in continuous conduction mode (CCM),
the switching frequency is not absolutely constant due to the
nature of the R
R3™ Modulator section, the effective switching frequency will
increase during load insertion and will decrease during load
release to achieve fast response. On the other hand, the
switching frequency is relatively constant at steady state.
Variation is expected when the power stage condition, such as
input voltage, output voltage, load, etc. changes. The variation is
usually less than 15% and doesn’t have any significant effect on
output voltage ripple magnitude. Equation 17 gives an estimate
of the frequency-setting resistor R
approximately 300kHz switching frequency. Lower resistance
gives higher switching frequency.

resistor between the COMP and the VW pins sets the

fset

3

™ modulator. As explained in the Multiphase

value. 8kΩ R

fset

fset

gives

REP RATE = 100kHz

REP RATE = 200kHz

FIGURE 12. ISL62883 EVALUATION BOARD CURRENT BALANCING

DURING DYNAMIC OPERATION. CH1: IL1, CH2: I
CH3: IL2, CH4: IL3

LOAD

R

kΩ() Period μs()0.29–()2.65×=

fset

Phase Count Configurations

The ISL62883 can be configured for 3-, 2- or 1-phase operation.

For 2-phase configuration, tie the PWM3 pin to 5V. Phase-1 and
Phase-2 PWM pulses are 180° out-of-phase. In this
configuration, the ISEN3/FB2 pin (pin 9) serves the FB2 function.

For 1-phase configuration, tie the PWM3 and ISEN2 pins to 5V. In
this configuration, only Phase-1 is active. The ISEN3/FB2, ISEN2,
and ISEN1 pins are not used because there is no need for either
current balancing or FB2 function.

,

(EQ. 17)

16

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Modes of Operation

TABLE 2. ISL62883 MODES OF OPERATION

OPERATIONAL

CONFIGURATION PSI# DPRSLPVR

3-phase Configuration 0 0 2-phase CCM

011-phase DE

1 0 3-phase CCM

111-phase DE

2-phase Configuration 0 0 1-phase CCM

011-phase DE

1 0 2-phase CCM

111-phase DE

1-phase Configuration 0 0 1-phase CCM

011-phase DE

1 0 1-phase CCM

111-phase DE

MODE

Table 2 shows the ISL62883 operational modes, programmed by
the logic status of the PSI# and the DPRSLPVR pins. In 3-phase
configuration, the ISL62883 enters 2-phase CCM for (PSI# = 0 and
DPRSLPVR = 0) by dropping PWM3 and operating phases 1 and 2
180° out-of-phase. It also reduces the overcurrent and the
way-overcurrent protection levels to 2/3 of the initial values. The
ISL62883 enters 1-phase DE mode when DPRSLPVR = 1. It drops
phases 2 and 3, and reduces the overcurrent and the way­overcurrent protection levels to 1/3 of the initial values.

In 2-phase configuration, the ISL62883 enters 1-phase CCM for
(PSI# = 0 and DPRSLPVR = 0). It drops Phase-2 and reduces the
overcurrent and the way-overcurrent protection levels to 1/2 of
the initial values. The ISL62883 enters 1-phase DE mode when
DPRSLPVR = 1 by dropping phase 2.

In 1-phase configuration, the ISL62883 does not change the
operational mode when the PSI# signal changes status. It enters
1-phase DE mode when DPRSLPVR = 1.

Dynamic Operation

The ISL62883 responds to VID changes by slewing to the new
voltage at 5mV/µs slew rate. As the output approaches the VID
command voltage, the dv/dt moderates to prevent overshoot.
Geyserville-III transitions commands one LSB VID step (12.5mV)
every 2.5µs, controlling the effective dv/dt at 5mv/µs. The
ISL62883 is capable of 5mV/µs slew rate.

When the ISL62883 is in DE mode, it will actively drive the output
voltage up when the VID changes to a higher value. It’ll resume
DE mode operation after reaching the new voltage level. If the
load is light enough to warrant DCM, it will enter DCM after the
inductor current has crossed zero for four consecutive cycles. The
ISL62883 will remain in DE mode when the VID changes to a
lower value. The output voltage will decay to the new value and
the load will determine the slew rate.

During load insertion response, the Fast Clock function increases
the PWM pulse response speed. The ISL62883 monitors the
VSEN pin voltage and compares it to 100ns - filtered version.

When the unfiltered version is 20mV below the filtered version,
the controller knows there is a fast voltage dip due to load
insertion, hence issues an additional master clock signal to
deliver a PWM pulse immediately.

3

™ modulator intrinsically has voltage feed forward. The

The R
output voltage is insensitive to a fast slew rate input voltage
change.

Protections

The ISL62883 provides overcurrent, current-balance,
undervoltage, overvoltage, and over-temperature protections.

The ISL62883 determines overcurrent protection (OCP) by
comparing the average value of the droop current I
internal current source threshold. It declares OCP when I
above the threshold for 120µs. A resistor R

comp

pin to GND programs the OCP current source threshold, as Table 3
shows. It is recommended to use the nominal R
ISL62883 detects the R

value at the beginning of start up,

comp

comp

and sets the internal OCP threshold accordingly. It remembers the
R

value until the VR_ON signal drops below the POR

comp

threshold.

TABLE 3. ISL62883 OCP THRESHOLD

R

comp

MIN. (kΩ)

320 400 480 22.7 45.3 68

210 235 260 20.7 41.3 62

155 165 175 18 36 54

104 120 136 20 37.33 56

NOMINAL

(kΩ)

none none 20 40 60

78 85 92 22.7 38.7 58

62 66 70 20.7 42.7 64

45 50 55 18 44 66

MAX.

(kΩ)

The default OCP threshold is the value when R

OCP THRESHOLD (µA)

1-PHASE

MODE

2-PHASE

MODE

comp

populated. It is recommended to scale the droop current I
such that the default OCP threshold gives approximately the
desired OCP level, then use R

to fine tune the OCP level if

comp

necessary.

For overcurrent conditions above 2.5 times the OCP level, the
PWM outputs will immediately shut off and PGOOD will go low to
maximize protection. This protection is also referred to as
way-overcurrent protection or fast-overcurrent protection, for
short-circuit protections.

The ISL62883 monitors the ISEN pin voltages to determine
current-balance protection. If the ISEN pin voltage difference is
greater than 9mV for 1ms, the controller will declare a fault and
latch off.

The ISL62883 will declare undervoltage (UV) fault and latch off if
the output voltage is less than the VID set value by 300mV or
more for 1ms. It’ll turn off the PWM outputs and dessert PGOOD.

The ISL62883 has two levels of overvoltage protections. The first
level of overvoltage protection is referred to as PGOOD
overvoltage protection. If the output voltage exceeds the VID set

with an

droop

droop

is

from the COMP

value. The

3-PHASE

MODE

is not

droop

17

FN6891.4

June 21, 2011

ISL62883, ISL62883B

value by +200mV for 1ms, the ISL62883 will declare a fault and
dessert PGOOD.

The ISL62883 takes the same actions for all of the above fault
protections: desertion of PGOOD and turn-off of the high-side and
low-side power MOSFETs. Any residual inductor current will decay
through the MOSFET body diodes. These fault conditions can be
reset by bringing VR_ON low or by bringing V

below the POR

DD

threshold. When VR_ON and VDD return to their high operating
levels, a soft-start will occur.

The second level of overvoltage protection is different. If the
output voltage exceeds 1.55V, the ISL62883 will immediately
declare an OV fault, dessert PGOOD, and turn on the low-side
power MOSFETs. The low-side power MOSFETs remain on until
the output voltage is pulled down below 0.85V when all power
MOSFETs are turned off. If the output voltage rises above 1.55V
again, the protection process is repeated. This behavior provides
the maximum amount of protection against shorted high-side
power MOSFETs while preventing output ringing below ground.
Resetting VR_ON cannot clear the 1.55V OVP. Only resetting V

DD

will clear it. The 1.55V OVP is active all the time when the
controller is enabled, even if one of the other faults have been
declared. This ensures that the processor is protected against
high-side power MOSFET leakage while the MOSFETs are
commanded off.

The ISL62883 has a thermal throttling feature. If the voltage on
the NTC pin goes below the 1.18V OT threshold, the VR_TT# pin is
pulled low indicating the need for thermal throttling to the
system. No other action is taken within the ISL62883 in response
to NTC pin voltage.

Table 4 summarizes the fault protections.

.

FAULT TYPE

Overcurrent 120µs PWM tri-state,

Way-Overcurrent
(2.5xOC)

Overvoltage +200mV 1ms

Undervoltage -300mV

Phase Current
Unbalance

Overvoltage 1.55V Immediately Low-side MOSFET

Over-Temperature 1ms N/A

TABLE 4. FAULT PROTECTION SUMMARY

FAULT DURATION

BEFORE

PROTECTION

<2µs

PROTECTION

ACTION

PGOOD latched

low

on until V
<0.85V, then

PWM tri-state,

PGOOD latched

core

low.

FAULT

RESET

VR_ON

toggle or

VDD toggle

VDD toggle

Current Monitor

The ISL62883 provides the current monitor function. The IMON
pin outputs a high-speed analog current source that is 3 times of
the droop current flowing out of the FB pin. Thus Equation 18:

I

IMON

3I

×=

droop

(EQ. 18)

As Figures 1 and 2 show, a resistor R

is connected to the

imon

IMON pin to convert the IMON pin current to voltage. A capacitor
can be paralleled with R

to filter the voltage information. The

imon

IMVP-6.5™ specification requires that the IMON voltage
information be referenced to VSSSENSE.

The IMON pin voltage range is 0V to 1.1V. A clamp circuit
prevents the IMON pin voltage from going above 1.1V.

FB2 Function

The FB2 function is only available when the ISL62883 is in
2-phase configuration, when pin 9 serves the FB2 function
instead of the ISEN3 function.

C1

FB2

Vref

R2

C3.1

C3.2

E/A

FB

VSEN

COMP

CONTROLLER I N

1-PHAS E MODE

C2

R1

CONTROLLER I N

2-PHASE MODE

C2

R3

VSEN

R1

FIGURE 13. FB2 FUNCTION IN 2-PHASE MODE

C1

C3.1

FB2

Vref

C3.2

E/A

FB

R3

Figure 13 shows the FB2 function. A switch (called FB2 switch)
turns on to short the FB and the FB2 pins when the controller is in
2-phase mode. Capacitors C3.1 and C3.2 are in parallel, serving
as part of the compensator. When the controller enters 1-phase
mode, the FB2 switch turns off, removing C3.2 and leaving only
C3.1 in the compensator. The compensator gain will increase
with the removal of C3.2. By properly sizing C3.1 and C3.2, the
compensator cab be optimal for both 2-phase mode and 1-phase
mode.

When the FB2 switch is off, C3.2 is disconnected from the FB pin.
However, the controller still actively drives the FB2 pin voltage to
follow the FB pin voltage such that C3.2 voltage always follows
C3.1 voltage. When the controller turns on the FB2 switch, C3.2
will be reconnected to the compensator smoothly.

The FB2 function ensures excellent transient response in both
2-phase mode and 1-phase mode. If one decides not to use the
FB2 function, simply populate C3.1 only.

Adaptive Body Diode Conduction Time
Reduction

In DCM, the controller turns off the low-side MOSFET when the
inductor current approaches zero. During on-time of the low-side
MOSFET, phase voltage is negative and the amount is the
MOSFET R
current. A phase comparator inside the controller monitors the
phase voltage during on-time of the low-side MOSFET and
compares it with a threshold to determine the zero-crossing point
of the inductor current. If the inductor current has not reached
zero when the low-side MOSFET turns off, it’ll flow through the
low-side MOSFET body diode, causing the phase node to have a
larger voltage drop until it decays to zero. If the inductor current
has crossed zero and reversed the direction when the low-side
MOSFET turns off, it’ll flow through the high-side MOSFET body
diode, causing the phase node to have a spike until it decays to
zero. The controller continues monitoring the phase voltage after
turning off the low-side MOSFET and adjusts the phase

voltage drop, which is proportional to the inductor

dson

R2

COMP

18

FN6891.4

June 21, 2011

ISL62883, ISL62883B

comparator threshold voltage accordingly in iterative steps such
that the low-side MOSFET body diode conducts for approximately
40ns to minimize the body diode-related loss.

Overshoot Reduction Function

The ISL62883 has an optional overshoot reduction function.
Using R
R

BIAS

= 47kΩ enables this function and using

BIAS

=147kΩ disables this function.

When a load release occurs, the energy stored in the inductors
will dump to the output capacitor, causing output voltage
overshoot. The inductor current freewheels through the low-side
MOSFET during this period of time. The overshoot reduction
function turns off the low-side MOSFET during the output voltage
overshoot, forcing the inductor current to freewheel through the
low-side MOSFET body diode. Since the body diode voltage drop
is much higher than MOSFET R

voltage drop, more energy is

dson

dissipated on the low-side MOSFET therefore the output voltage
overshoot is lower.

If the overshoot reduction function is enabled, the ISL62883
monitors the COMP pin voltage to determine the output voltage
overshoot condition. The COMP voltage will fall and hit the clamp
voltage when the output voltage overshoots. The ISL62883 will
turn off LGATE1 and LGATE2, and tri-state PWM3 when COMP is
being clamped. All the low-side MOSFETs in the power stage will
be turned off. When the output voltage has reached its peak and
starts to come down, the COMP voltage starts to rise and is no
longer clamped. The ISL62883 will resume normal PWM
operation.

When PSI# is low, indicating a low power state of the CPU, the
controller will disable the overshoot reduction function as large
magnitude transient event is not expected and overshoot is not a
concern.

While the overshoot reduction function reduces the output voltage
overshoot, energy is dissipated on the low-side MOSFET, causing
additional power loss. The more frequent transient event, the more
power loss dissipated on the low-side MOSFET. The MOSFET may
face severe thermal stress when transient events happen at a high
repetitive rate. User discretion is advised when this function is
enabled.

Key Component Selection

R

BIAS

The ISL62883 uses a resistor (1% or better tolerance is
recommended) from the RBIAS pin to GND to establish highly
accurate reference current sources inside the IC. Using

=47kΩ enables the overshoot reduction function and using

R

BIAS

= 147kΩ disables this function. Do not connect any other

R

BIAS

components to this pin. Do not connect any capacitor to the RBIAS
pin as it will create instability.

Care should be taken in layout that the resistor is placed very close
to the RBIAS pin and that a good quality signal ground is
connected to the opposite side of the R

Ris and C

is

As Figures 1 and 2, show, the ISL62883 needs the Ris-Cis
network across the ISUM+ and the ISUM- pins to stabilize the

BIAS

resistor.

droop amplifier. The preferred values are R

= 82.5Ω and

is

Cis= 0.01µF. Slight deviations from the recommended values are
acceptable. Large deviations may result in instability.

Inductor DCR Current-Sensing Network

Phase1

L

DCR

Figure 14 shows the inductor DCR current-sensing network for a
3-phase solution. An inductor current flows through the DCR and
creates a voltage drop. Each inductor has two resistors in R
and Ro connected to the pads to accurately sense the inductor
current by sensing the DCR voltage drop. The R
resistors are connected in a summing network as shown, and feed
the total current information to the NTC network (consisting of
R

ntcs

temperature coefficient (NTC) thermistor, used to
temperature-compensate the inductor DCR change.

The inductor output side pads are electrically shorted in the
schematic, but have some parasitic impedance in actual board
layout, which is why one cannot simply short them together for the
current-sensing summing network. It is recommended to use
1Ω~10Ω R
smaller than the rest of the current sensing circuit, the following
analysis will ignore it for simplicity.

The summed inductor current information is presented to the
capacitor C
frequency-domain relationship between inductor total current

(s) and Cn voltage VCn(s):

I

o

VCns()

R

ntcnet

A

cs

where N is the number of phases.

Phase2 Phase3

Rsum

Rsum

Rsum

×

DCR

----------- -

N

Rntcs

Rntc

Ro

Ro

Ro

Rp

is a negative

ntc

s()× Acs× s()=

I

o

L

DCRLDCR

Io

FIGURE 14. DCR CURRENT-SENSING NETWORK

, R

and Rp) and capacitor Cn. R

ntc

to create quality signals. Since Ro value is much

o

. Equations 19 thru 23 describe the

n

⎛⎞

R

⎜⎟

ntcnet

-----------------------------------------

⎜⎟
⎜⎟

R

⎝⎠

R

-------------------------------------------------- -

=

R

1

----------------------

s()

=

1

+

R

sum

--------------

+

ntcnet

ntcsRntc

ntcsRntcRp

+

------------

ω

+()Rp×
++

s

------

ω

L

s

sns

N

sum

Cn

Vcn

Ri

and Ro

(EQ. 19)

(EQ. 20)

(EQ. 21)

ISUM+

ISUM-

sum

19

FN6891.4

June 21, 2011

ISL62883, ISL62883B

DCR

----------- -

ω

=

L

L

------------------------------------------------------

=

ω

sns

R

ntcnet

-----------------------------------------

R

ntcnet

×

+

1

R

sum

--------------

R

sum

--------------

N

×

C

n

N

(EQ. 22)

(EQ. 23)

Transf er funct ion Acs(s) always has unity gain at DC. The inductor
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC R

ntc

values decreases as its temperature decreases. Proper

, R

selections of R

represent the inductor total DC current over the temperature

V

Cn

sum

ntcs

, Rp and R

parameters ensure that

ntc

range of interest.

There are many sets of parameters that can properly temperature­compensate the DCR change. Since the NTC network and the R
resistors form a voltage divider, V

is always a fraction of the

cn

sum

inductor DCR voltage. It is recommended to have a higher ratio of
Vcn to the inductor DCR voltage, so the droop circuit has higher
signal level to work with.

A typical set of parameters that provide good temperature
compensation are: R
and R

= 10kΩ (ERT-J1VR103J). The NTC network parameters

ntc

= 3.65kΩ, Rp= 11kΩ, R

sum

ntcs

= 2.61kΩ

may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current-sensing network parameters to minimize engineering
time.

(s) also needs to represent real-time Io(s) for the controller to

V

Cn

achieve good transient response. Transfer function Acs(s) has a
pole ω
A

cs

and a zero ωL. One needs to match ωL and ω

sns

(s) is unity gain at all frequencies. By forcing ωL equal to ω

sns

so

sns

and solving for the solution, Equation 24 solves for the value of

Cn.

×

+

L

R

sum

--------------

N

R

sum

--------------

N

(EQ. 24)

DCR×

------------------------------------------------------------

=

C

n

R

ntcnet

-----------------------------------------

R

ntcnet

i

o

V

o

FIGURE 16. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO

SMALL

i

o

V

o

FIGURE 17. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO

LARGE

For example, given N = 3, R
R

ntcs

=2.61kΩ, R

= 10kΩ, DCR = 0.88mΩ and L = 0.36µH,

ntc

= 3.65kΩ, Rp=11kΩ,

sum

Equation 24 gives Cn= 0.406µF.

Assuming the compensator design is correct, Figure 15 shows the
expected load transient response waveforms if C
selected. When the load current I
output voltage V

If C

value is too large or too small, VCn(s) will not accurately

n

also has a square response.

core

has a square change, the

core

is correctly

n

represent real-time Io(s) and will worsen the transient response.
Figure 16 shows the load transient response when Cn is too
small. V

will sag excessively upon load insertion and may

core

create a system failure. Figure 17 shows the transient response
when Cn is too large. V

is sluggish in drooping to its final

core

value. There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU reliability.

i

o

i

L

i

o

V

o

FIGURE 15. DESIRED LOAD TRANSIENT RESPONSE

WAVEFORMS

20

V

o

RING

BACK

FIGURE 18. OUTPUT VOLTAGE RING BACK PROBLEM

June 21, 2011

FN6891.4

ISL62883, ISL62883B

ISUM+

Rntcs

Rntc

FIGURE 19. OPTIONAL CIRCUITS FOR RING BACK REDUCTION

Rp

Cn.1

Rn

OPTIONAL

Vcn

Cn.2

Ri

Cip

Rip

OPTIONAL

ISUM-

Figure 18 shows the output voltage ring back problem during
load transient response. The load current i
change, but the inductor current i

cannot accurately follow.

L

has a fast step

o

Instead, iL responds in first order system fashion due to the
nature of current loop. The ESR and ESL effect of the output
capacitors makes the output voltage V

dip quickly upon load

o

current change. However, the controller regulates Vo according to
the droop current i

, which is a real-time representation of iL;

droop

therefore it pulls Vo back to the level dictated by iL, causing the
ring back problem. This phenomenon is not observed when the
output capacitor have very low ESR and ESL, such as all ceramic
capacitors.

Figure 19 shows two optional circuits for reduction of the ring
back. R

and Cip form an R-C branch in parallel with Ri, providing

ip

a lower impedance path than Ri at the beginning of io change.
Rip and Cip do not have any effect at steady state. Through
proper selection of R

and Cip values, i

ip

can resemble io

droop

rather than iL, and Vo will not ring back. The recommended value
for Rip is100Ω. Cip should be determined through tuning the load
transient response waveforms on an actual board. The
recommended range for C

is the capacitor used to match the inductor time constant. It

C

n

is 100pF~2000pF.

ip

usually takes the parallel of two (or more) capacitors to get the
desired value. Figure 19 shows that two capacitors C
are in parallel. Resistor R

ring back. At steady state, C

the V

o

is an optional component to reduce

n

n.1+Cn.2

provides the desired

n.1

and C

n.2

Cn capacitance. At the beginning of io change, the effective
capacitance is less because R

branch. As explained in Figure 16, Vo tends to dip when Cn is

C

n.1

too small, and this effect will reduce the V
is more pronounced when C
more pronounced when R
R

increases the ripple of the Vn signal if C

n

recommended to keep C
usually is a few ohms. C

increases the impedance of the

n

ring back. This effect

is much larger than C

n.1

is bigger. However, the presence of

n

greater than 2200pF. Rn value

n.2

, C

n.1

and Rn values should be

n.2

o

n.2

is too small. It is

n.2

. It is also

determined through tuning the load transient response
waveforms on an actual board.

Resistor Current-Sensing Network

Phase1

L

DCR

Rsen

Figure 20 shows the resistor current-sensing network for a
3-phase solution. Each inductor has a series current-sensing
resistor R
accurately capture the inductor current information. The R
and Ro resistors are connected to capacitor Cn. R
form a a filter for noise attenuation. Equations 25 thru 27 give

(s) expression:

V

Cn

VCns()

A

Rsen

ω

Rsen

Transfer function A
Current-sensing resistor R
variation over temperature, so there is no need for the NTC
network.

The recommended values are R

Phase2 Phase3

L

DCRLDCR

Rsen Rsen

Io

FIGURE 20. RESISTOR CURRENT-SENSING NETWORK

. R

sen

R

------------

s()

=

---------------------------

=

R

--------------

and Ro are connected to the R

sum

sen

sum

N

N

1

----------------------

------------

1

+

ω

1

×

I

o

s

sns

C

n

Rsen

s()× A

Rsum

Rsum

Rsum

Vcn

Ro

Ro

Ro

× s()=

Rsen

Cn

sen

sum

(s) always has unity gain at DC.

value will not have significant

sen

=1kΩ and Cn= 5600pF.

sum

Ri

Overcurrent Protection

Refer to Equation 1 and Figures 9, 14 and 20; resistor Ri sets the
droop current I
is recommended to design I
resistor.

For example, the OCP threshold is 60µA for 3-phase solution. We
will design I

droop

1.55 times of the full load current.

For inductor DCR sensing, Equation 28 gives the DC relationship

(s) and Io(s).

of V

cn

⎛⎞
⎜⎟

-----------------------------------------

V

⎜⎟

Cn

⎜⎟

R

⎝⎠

ntcnet

. Table 3 shows the internal OCP threshold. It

droop

without using the R

droop

to be 38.8µA at full load, so the OCP trip level is

R

ntcnet

+

R

sum

--------------

N

×

DCR

----------- -

N

×=

I

o

ISUM+

ISUM-

pads to

sum

and Cn

(EQ. 25)

(EQ. 26)

(EQ. 27)

comp

(EQ. 28)

21

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Substitution of Equation 28 into Equation 1 gives Equation 29:

droop

R

2

-----------------------------------------

---- -

R

i

R

ntcnet

ntcnet

+

R

sum

--------------

N

DCR

----------- -

×=

×× I

N

o

(EQ. 29)

Therefore:

2R

------------------------------------------------------------------------------- -

R

=

i

⎛⎞

NR

× I

ntcnet

⎝⎠

ntcnet

+

DCR× Io×

R

sum

--------------

N

×

(EQ. 30)

droop

Substitution of Equation 20 and application of the OCP condition
in Equation 30 gives Equation 31:

2

× DCR× I

-------------------------------------------------------------------------------------------------------------------------

R

=

i

where I

R

⎛⎞

-------------------------------------------------- -

N

× I

⎜⎟

R

⎝⎠

is the full load current, I

omax

++

R

ntcsRntcRp

+()Rp×

ntcsRntc

++

ntcsRntcRp

+

R

sum

--------------

N

×

omax

×

droopmax

droopmax

(EQ. 31)

is the

+()Rp×

R

ntcsRntc

-------------------------------------------------- -

corresponding droop current. For example, given N = 3,
R

= 3.65kΩ, Rp= 11kΩ, R

sum

DCR = 0.88mΩ, I

omax

=51A and I

=2.61kΩ, R

ntcs

droopmax

=10kΩ,

ntc

= 40.9µA, Equation

31 gives Ri= 606Ω.

For resistor sensing, Equation 32 gives the DC relationship of

(s) and Io(s).

V

cn

R

sen

------------

V

Cn

×=

I

o

N

(EQ. 32)

Substitution of Equation 32 into Equation 1 gives Equation 33:

I

droop

sen

---- -

------------

××=

I

o

N

R

i

(EQ. 33)

R

2

Therefore:

2R

×

R

i

---------------------------

=

×

NI

senIo

droop

(EQ. 34)

Substitution of Equation 34 and application of the OCP condition

in Equation 30 gives:

2R

×

R

=

i

where I

senIomax

--------------------------------------

×

NI

droopmax

is the full load current, I

omax

droopmax

is the

(EQ. 35)

corresponding droop current. For example, given N = 3,
R

sen

gives R

=1mΩ, I

=831Ω.

i

omax

=51A and I

droopmax

= 40.9µA, Equation 35

A resistor from COMP to GND can adjust the internal OCP
threshold, providing another dimension of fine-tune flexibility.
Table 3 shows the detail. It is recommended to scale I

droop

such
that the default OCP threshold gives approximately the desired
OCP level, then use R

to fine tune the OCP level if necessary.

comp

Load Line Slope

Refer to Figure 9.

For inductor DCR sensing, substitution of Equation 29 into

Equation 2 gives the load line slope expression:

LL

V

droop

----------------- -

I

o

2R

droop

----------------------

R

i

R

ntcnet

-----------------------------------------

R

ntcnet

+

R

sum

--------------

N

DCR

----------- -

××== (EQ. 36)

N

For resistor sensing, substitution of Equation 33 into Equation 2

gives the load line slope expression:

2R

V

droop

----------------- -

LL

==

I

o

×

senRdroop

-----------------------------------------

NR

×

i

(EQ. 37)

Substitution of Equation 30 and rewriting Equation 36, or
substitution of Equation 34 and rewriting Equation 37 gives the
same result in Equation 38:

I

o

----------------

R

droop

One can use the full load condition to calculate R
example, given I
LL = 1.9mΩ, Equation 38 gives R

It is recommended to start with the R

I

droop

omax

LL×=

=51A, I

droopmax

droop

= 40.9µA and

droop

=2.37kΩ.

value calculated by

droop

(EQ. 38)

. For

Equation 38, and fine tune it on the actual board to get accurate
load line slope. One should record the output voltage readings at
no load and at full load for load line slope calculation. Reading
the output voltage at lighter load instead of full load will increase
the measurement error.

Current Monitor

Refer to Equation 18 for the IMON pin current expression.

Refer to Figures 1 and 2, the IMON pin current flows through
R

. The voltage across R

imon

V

Rimon

3I×

×=

droopRimon

is expressed in Equation 39:

imon

(EQ. 39)

Rewriting Equation 38 gives Equation 40:

I

o

I

droop

------------------

R

droop

LL×=

(EQ. 40)

Substitution of Equation 40 into Equation 39 gives Equation 41:

3IoLL×

V

Rimon

---------------------

R

droop

×=

R

imon

(EQ. 41)

Rewriting Equation 41 and application of full load condition gives
Equation 42:

V

×

RimonRdroop

=

imon

= 963mV at I

=7.85kΩ.

--------------------------------------------

imon

LL×

3I

o

= 51A, Equation 42 gives

omax

can be paralleled with R

imonCimon

(EQ. 42)

=2.37kΩ,

droop

to filter the IMON

imon

time constant is the user’s choice. It

R

For example, given LL = 1.9mΩ, R
V

Rimon

R

imon

A capacitor C
pin voltage. The R
is recommended to have a time constant long enough such that
switching frequency ripples are removed.

Compensator

Figure 15 shows the desired load transient response waveforms.
Figure 21 shows the equivalent circuit of a voltage regulator (VR)
with the droop function. A VR is equivalent to a voltage source
(= VID) and output impedance Z

out

(s). If Z
load line slope LL, i.e. constant output impedance, in the entire
frequency range, V

will have square response when Io has a

o

square change.

(s) is equal to the

out

22

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Zout(s)=LL

VID

VR

i

o

Load

V

o

FIGURE 21. VOLTAGE REGULATOR EQUIVALENT CIRCUIT

Intersil provides a Microsoft Excel-based spreadsheet to help design
the compensator and the current sensing network, so the VR
achieves constant output impedance as a stable system. Please
contact Intersil Application support at www.intersil.com/design/
Figure 24

shows a screenshot of the spreadsheet.

.

A VR with active droop function is a dual-loop system consisting
of a voltage loop and a droop loop which is a current loop.
However, neither loop alone is sufficient to describe the entire
system. The spreadsheet shows two loop gain transfer functions,
T1(s) and T2(s), that describe the entire system. Figure 22
conceptually shows T1(s) measurement set-up and Figure 23
conceptually shows T2(s) measurement set-up. The VR senses
the inductor current, multiplies it by a gain of the load line slope,
then adds it on top of the sensed output voltage and feeds it to
the compensator. T(1) is measured after the summing node, and
T2(s) is measured in the voltage loop before the summing node.
The spreadsheet gives both T1(s) and T2(s) plots. However, only
T2(s) can be actually measured on an ISL62883 regulator.

T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s) and has
more meaning of system stability.

T2(s) is the voltage loop gain with closed droop loop. It has more
meaning of output voltage response.

Design the compensator to get stable T1(s) and T2(s) with
sufficient phase margin, and output impedance equal or smaller
than the load line slope.

C

out

EXCITATION

OUTPUT

V

o

i

o

Ω

20

ISOLATION
TRANSFORMER

Q1

V

in

LOOP GAIN =

GATE

DRIVER

Q2

Mod.

Comp

CHANNEL B

CHANNEL A

NETWORK

ANALYZER

L

LOAD LINE SLOPE

EA

VID

FIGURE 22. LOOP GAIN T1(s) MEASUREMENT SET-UP

C

VID

out

Ω

V

o

i

o

20

EXCITATION

OUTPUT

ISOLATION
TRANSFORMER

Q1

V

in

LOOP GAIN =

GATE

DRIVER

Q2

Mod.

Comp

CHANNEL B
CHANNEL A

L

LOAD LINE SLOPE

EA

NETWORK

ANALYZER

FIGURE 23. LOOP GAIN T2(s) MEASUREMENT SET-UP

CHANNEL BCHANNEL A

CHANNEL BCHANNEL A

23

FN6891.4

June 21, 2011

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

Compensation & Current Sensing Network Design for Intersil Multiphase R^3 Regulators for IMVP-6.5

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3KDVHGHJUHH

)UHTXHQF\+]

3KDVHGHJUHH

Jia Wei, [e-mail], 919-405-3605

Attention: 1. "Analysis ToolPak" Add-in is required. To turn on, go to Tools--Add-Ins, and check "Analysis ToolPak"

2. Green cells require user input

Operation Parameters

Controller Part Number:

Phase Number: 3

Full Load Current: 51 Amps

Switching Frequency: 300 kHz

Inductance Per Phase: 0.36 uH

CPU Socket Resistance: 0.9

Desired Load-Line Slope: 1.9

Loop Gain, Gain Curve

24

Estimated Full-Load Efficiency: 87 %

Number of Output Bulk Capacitors: 4

Capacitance of Each Output Bulk Capacitor: 270 uF

ESR of Each Output Bulk Capacitor: 4.5

ESL of Each Output Bulk Capacitor: 0.6 nH R2 338.213

Number of Output Ceramic Capacitors: 24 R3 0.530

Capacitance of Each Output Ceramic Capacitor: 10 uF C1 148.140 pF C1 150 pF

ESR of Each Output Ceramic Capacitor: 3

ESL of Each Output Ceramic Capacitor: 3 nH C3 40.069 pF C3 39 pF

Desired ISUM- Pin Current at Full Load: 40.9 uA T1 Bandwidth: 212kHz T2 Bandwidth: 66kHz

(This sets the over-current protection level) T1 Phase Margin: 58.9° T2 Phase Margin: 89.3°

Changing the settings in red requires deep understanding of control loop design

Place the 2nd compensator pole fp2 at: 2.2 Rsum 3.65

Tune Ki to get the desired loop gain bandwidth Rntc 10

Tune the compensator gain factor Ki:

(Recommended Ki range is 0.8~2) Rp 11

















( ( ( ( ( (



Loop Gain, Phase Curve

ISL6288x

Vin: 12 volts

Vo: 1.15 volts

m

m

m
m

xfs

1.3 Rntcs 2.61

7V
7V

Recommended Value User-Selected Value

R1 2.369

C2 455.369 pF C2 390 pF

(Switching Frequency)



















( ( ( ( ( (



Compensator Parameters Current Sensing Network Parameters

iK

)(

sA

V

s

k
k
k

R1 2.37
R2 324
R3 0.536

Use User-Selected Value (Y/N)?

§

s

¨



ZZ

1

i

¨

2

f

©

§

·

s

¨

¸



1

¨

¸

2

f

©

¹

N

s

¸

¨

¸



1

¸

¨

¸

SS

2

f

¹

©

¹

21

zz

§

·

s

¨

¸



1

¨

¸

2

f

SS

21

pp

©

¹

k
k
k

·

§

·

Performance and Stability

Operation Parameters

Inductor DCR 0.88

Output Impedance, Gain Curve

Recommended Value User Selected Value

Cn 0.406 uF Cn 0.406 uF

Ri 606.036

Output Impedance, Phase Curve

m
k
k
k
k

ISL62883, ISL62883B

Ri 604









June 21, 2011

FN6891.4

( ( ( ( ( (

7V
7V









( ( ( ( ( (

FIGURE 24. SCREENSHOT OF THE COMPENSATOR DESIGN SPREADSHEET

ISL62883, ISL62883B

Optional Slew Rate Compensation Circuit For
1-Tick VID Transition

Rdroop

Cvid

Rvid

COMP

FB

E/A

INTERNAL

Idroop_vid

Σ

VDAC

Ivid

DAC

X 1

TO IC

VID<0:6>

Vfb

Ivid

Vcore

Idroop_vid

FIGURE 25. OPTIONAL SLEW RATE COMPENSATION CIRCUIT

FOR1-TICK VID TRANSITION

VIDs

RTN

VSS

Vcore

OPTIONAL

VID<0:6>

VSSSENSE

In the mean time, the R

branch current I

vid-Cvid

time domain

vid

expression is shown in Equation 44:

t–

------------------------------

⎛⎞

I

vid

t() C

× 1e

vid

It is desired to let I

dV

C

fb

out

------------------------

----------- -

C

×

vid

dt

R

dV

----------- -

dt

vid

droop

fb

R

–

dV

core

----------------- -

dt

×

vidCvid

droop_vid

(t). So there are:

⎜⎟

×=

⎜⎟
⎝⎠

(t) cancel I

LL×

×=

(EQ. 44)

(EQ. 45)

and:

× C

R

vidCvid

out

LL×=

(EQ. 46)

The result is expressed in Equation 47:

R

=

vidRdroop

(EQ. 47)

and:

dV

core

C

out

------------------------

C

vid

R

droop

For example: given LL = 1.9mΩ, R
C

= 1320µF, dV

out

Equation 47 gives R
C

= 350pF.

vid

It’s recommended to select the calculated R
with the calculated C

----------------- -

LL×

dt

----------------- -

×=

dV

fb

----------- -

dt

=2.37kΩ,

/dt = 5mV/us and dVfb/dt = 15mV/µs,

core

=2.37kΩ and Equation 48 gives

vid

droop

vid

value and tweak it on the actual board to

vid

(EQ. 48)

value and start

get the best performance.

During normal transient response, the FB pin voltage is held
constant, therefore is virtual ground in small signal sense. The
R

network is between the virtual ground and the real

vid-Cvid

ground, and hence has no effect on transient response.

Voltage Regulator Thermal Throttling

During a large VID transition, the DAC steps through the VIDs at a
controlled slew rate of 2.5µs per tick (12.5mV), controlling
output voltage V

slew rate at 5mV/µs.

core

Figure 25 shows the waveforms of 1-tick VID transition. During
1-tick VID transition, the DAC output changes at approximately
15mV/µs slew rate, but the DAC cannot step through multiple
VIDs to control the slew rate. Instead, the control loop response
speed determines V

slew rate. Ideally, V

core

will follow the FB

core

pin voltage slew rate. However, the controller senses the inductor

core

current increase during the up transition, as the I

droop_vid

waveform shows, and will droop the output voltage V
accordingly, making V

slew rate slow. Similar behavior occurs

core

during the down transition.

To cont rol V
the R

vid-Cvid

When V
induced I

I

droop

where C

slew rate during 1-tick VID transition, one can add

core

branch, whose current I

increases, the time domain expression of the

core

change is expressed in Equation 43:

droop

dV

LL×

C

out

------------------------

t()

R

droop

is the total output capacitance.

out

core

----------------- -

× 1e

dt

cancels I

vid

-------------------------

⎛⎞

C

⎜⎟

–

×=

⎜⎟
⎝⎠

out

droop_vid

t–

LL×

.

(EQ. 43)

25

54uA

NTC

+

V

R

NTC

NTC

-

1.24V

R

s

FIGURE 26. CIRCUITRY ASSOCIATED WITH THE THERMAL

THROTTLING FEATURE OF THE ISL62882

64uA

SW1

-

+

SW2

1.20V

INTERNAL TO

ISL62882

VR_TT#

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Figure 26 shows the thermal throttling feature with hysteresis.
An NTC network is connected between the NTC pin and GND. At
low temperature, SW1 is on and SW2 connects to the 1.20V side.
The total current flowing out of the NTC pin is 60µA. The voltage
on NTC pin is higher than threshold voltage of 1.20V and the
comparator output is low. VR_TT# is pulled up by the external
resistor.

When temperature increases, the NTC thermistor resistance
decreases so the NTC pin voltage drops. When the NTC pin
voltage drops below 1.20V, the comparator changes polarity and
turns SW1 off and throws SW2 to 1.24V. This pulls VR_TT# low
and sends the signal to start thermal throttle. There is a 6µA
current reduction on NTC pin and 40mV voltage increase on
threshold voltage of the comparator in this state. The VR_TT#
signal will be used to change the CPU operation and decrease
the power consumption. When the temperature drops down, the
NTC thermistor voltage will go up. If NTC voltage increases to
above 1.24V, the comparator will flip back. The external
resistance difference in these two conditions is expressed in
Equation 49:

1.24V

---------------

54μ A

1.20V

---------------

– 2.96 k=

60μ A

(EQ. 49)

One needs to properly select the NTC thermistor value such that
the required temperature hysteresis correlates to 2.96kΩ
resistance change. A regular resistor may need to be in series
with the NTC thermistor to meet the threshold voltage values.

For example, given Panasonic NTC thermistor with B = 4700, the
resistance will drop to 0.03322 of its nominal at +105°C, and
drop to 0.03956 of its nominal at +100°C. If the required
temperature hysteresis is +105°C to +100°C, the required
resistance of NTC will be:

2.96k Ω

-------------------------------------------------------

0.03956 0.03322–()

467k Ω=

(EQ. 50)

Therefore a larger value thermistor, such as 470k NTC should be
used.

At +105°C, 470kΩ NTC resistance becomes
(0.03322×470kΩ) = 15.6kΩ. With 60µA on the NTC pin, the
voltage is only (15.6kΩ×60µA) = 0.937V. This value is much
lower than the threshold voltage of 1.20V. Therefore, a regular
resistor needs to be in series with the NTC. The required
resistance can be calculated by Equation 51:

1.20V

---------------

60μ A

15.6k Ω– 4.4kΩ=

(EQ. 51)

represent the DC current flowing through the inductors.
Recommended values are R

= 10kΩ and Cs= 0.22µF.

s

Layout Guidelines

Table 5 shows the layout considerations. The designators refer to
the reference design shown in Figure 27.

TABLE 5. LAYOUT CONSIDERATION

PIN NAME LAYOUT CONSIDERATION

EP GND Create analog ground plane underneath the

controller and the analog signal processing
components. Don’t let the power ground plane
overlap with the analog ground plane. Avoid noisy
planes/traces (e.g.: phase node) from crossing
over/overlapping with the analog plane.

1 PGOOD No special consideration

2 PSI# No special consideration

3 RBIAS Place the Rbias resistor (R16) in general proximity

of the controller. Low impedance connection to the
analog ground plane.

4 VR_TT# No special consideration

5 NTC The NTC thermistor (R9) needs to be placed close

to the thermal source that is monitor to determine
thermal throttling. Usually it’s placed close to
Phase-1 high-side MOSFET.

6 VW Place the capacitor (C4) across VW and COMP in

close proximity of the controller

7 COMP Place the compensator components (C3, C6 R7,

8FB

9 ISEN3/FB2 A capacitor (C7) decouples it to VSUM-. Place it in

10 ISEN2 A capacitor (C9) decouples it to VSUM-. Place it in

11 ISEN1 A capacitor (C10) decouples it to VSUM-. Place it in

12 VSEN Place the VSEN/RTN filter (C12, C13) in close

13 RTN

R11, R10 and C11) in general proximity of the
controller.

general proximity of the controller.
An optional capacitor is placed between this pin
and COMP. (It’s only used when the controller is
configured 2-phase). Place it in general proximity
of the controller.

general proximity of the controller.

general proximity of the controller.

proximity of the controller for good decoupling.

4.42k is a standard resistor value. Therefore, the NTC branch
should have a 470k NTC and 4.42k resistor in series. The part
number for the NTC thermistor is ERTJ0EV474J. It is a 0402
package. The NTC thermistor will be placed in the hot spot of the
board.

Current Balancing

Refer to Figures 1 and 2. The ISL62883 achieves current
balancing through matching the ISEN pin voltages. R
form filters to remove the switching ripple of the phase node
voltages. It is recommended to use rather long R
constant such that the ISEN voltages have minimal ripple and

26

sCs

and Cs

s

time

FN6891.4

June 21, 2011

ISL62883, ISL62883B

TABLE 5. LAYOUT CONSIDERATION

PIN NAME LAYOUT CONSIDERATION

14 ISUM- Place the current sensing circuit in general

15 ISUM+

proximity of the controller.
Place C82 very close to the controller.
Place NTC thermistors R42 next to Phase-1
inductor (L1) so it senses the inductor temperature
correctly.
Each phase of the power stage sends a pair of
VSUM+ and VSUM- signals to the controller. Run
these two signals traces in parallel fashion with
decent width (>20mil).
IMPORTANT: Sense the inductor current by routing
the sensing circuit to the inductor pads.
Route R63 and R71 to the Phase-1 side pad of
inductor L1. Route R88 to the output side pad of
inductor L1.
Route R65 and R72 to the Phase-2 side pad of
inductor L2. Route R90 to the output side pad of
inductor L2.
Route R67 and R73 to the Phase-3 side pad of
inductor L3. Route R92 to the output side pad of
inductor L3.
If possible. Route the traces on a different layer
from the inductor pad layer and use vias to
connect the traces to the center of the pads. If no
via is allowed on the pad, consider routing the
traces into the pads from the inside of the
inductor. The following drawings show the two
preferred ways of routing current sensing traces.

Inductor

(Continued)

Inductor

Vias

TABLE 5. LAYOUT CONSIDERATION

PIN NAME LAYOUT CONSIDERATION

25 VCCP A capacitor (C22) decouples it to GND. Place it in

close proximity of the controller.

26 LGATE2 Run these two traces in parallel fashion with

27 VSSP2

28 PHASE2 Run these two traces in parallel fashion with

29 UGATE2

30 BOOT2 Use decent wide trace (>30mil). Avoid any

31~37 VID0~6 No special consideration.

38 VR_ON No special consideration.

39 DPRSLPVR No special consideration.

40 CLK_EN# No special consideration.

Other Phase Node Minimize phase node copper area. Don’t let the

Other Minimize the loop consisting of input capacitor,

decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing VSSP2 to the Phase-2 low­side MOSFET (Q5 and Q1) source pins instead of
general power ground plane for better
performance.

decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing PHASE2 trace to the Phase-2
high-side MOSFET (Q4 and Q10) source pins
instead of general Phase-2 node copper.

sensitive analog signal trace from crossing over or
getting close.

phase node copper overlap with/getting close to
other sensitive traces. Cut the power ground plane
to avoid overlapping with phase node copper.

high-side MOSFETs and low-side MOSFETs (e.g.:
C27, C33, Q2, Q8, Q3 and Q9).

(Continued)

Current-Sensing

Traces

16 VDD A capacitor (C16) decouples it to GND. Place it in

close proximity of the controller.

17 VIN A capacitor (C17) decouples it to GND. Place it in

close proximity of the controller.

18 IMON Place the filter capacitor (C21) close to the CPU.

19 BOOT1 Use decent wide trace (>30mil). Avoid any

sensitive analog signal trace from crossing over or
getting close.

20 UGATE1 Run these two traces in parallel fashion with

21 PHASE1

22 VSSP1 Run these two traces in parallel fashion with

23 LGATE1

24 PWM3 No special consideration.

decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing PHASE1 trace to the Phase-1
high-side MOSFET (Q2 and Q8) source pins instead
of general
Phase-1 node copper.

decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing VSSP1 to the Phase-1 low­side MOSFET (Q3 and Q9) source pins instead of
general power ground plane for better
performance.

Current-Sensing

Traces

27

FN6891.4

June 21, 2011

28

34

DNP

IRF7821

Q10

IRF7832 IRF7832

Q11

DNP

IRF7821

Q8

IRF7832 IRF7832

Q9

DNP

IRF7821

Q12

IRF7832 IRF7832

Q13

TITLE:

1UF

C26

ENGINEER:

L2

0.36UH

10K

R72

3.65K3.65K

OUT

VSUM+

L1

R90

ISEN2

R65R63

OUT

0.36UH

10K

R88

R71

3.65K

OUT

OUT

ISEN1

VSUM+

L3

0.36UH

10K

R67

R73

R92

OUT

OUT

ISEN3

VSUM+

IN

+5V

ISL62883 REFERENCE DESIGN

3-PHASE, DCR SENSING

BOOT2

UGATE2

PHASE2

VSSP2

LGATE2

VCCP

PWM3

LGATE1

VSSP1

PHASE1

IN

+5V

IN

VIN

0.47UF

C20

56

IN

VIN

30

29

28

27

26

25

IN

24

23

22

21

1UF

C22

R50

C21

7.87K

R41

2.61K

R38

11K

R42

10K

NTC

----->

PLACE NEAR L1

0.1UF

C25

C24

56UF

+5V

OUT

0.22UF

IN

IN

IN

56UF

IMON

VSSSENSE

VSUM+

VSUM-

45

C28

C34

10UF

R57

C31

0

0.22UF

C27

C33

10UF

C30

R56

0

0.22UF

C29

C35

10UF

C32

R58

0

0.22UF

U3

PHASE

UGATE

GND LGATE

ISL6208

10UF

Q4

Q5

10UF

Q2

Q3

10UF

Q6

Q7

FCCMBOOT

VCCPWM

78

IN

VID0

IN

VID1

IN

VID2

IN

VID3

IN

D

C C

B B

A A

VID4

IN

VID5

IN

VID6

IN

VR_ON

DPRSLPVR

----

-------

----

----

R110

C83

-------------

---­ISEN3

ISEN2
ISEN1

IN

OUT

CLK_EN#

IN

+3.3V

OUT

PGOOD

IN

PSI#

IN

+1.1V

OUT

VR_TT#

OPTIONAL

R4

R6

C4

8.66K

-------

DNP

OPTIONAL

C6

2.37K

39PF

C3

R7

560PF

150PF

324K

-------------

IN

IN

IN

C7

8

1000PF

R10

536

R11

2.37K

C9

0.22UF

0.22UF

VCORE

R12

499

R8

C11

390PF

C10

0.22UF

IN

VCCSENSE

VSSSENSE

R16

147K

R9

NTCTBD
TBD

R17

10

IN

IN

R18

10

R19

1.91K

1

2

3

4

5

6

7

8

9

10

41

R23

1.91K

PGOOD

PSI#

RBIAS

VR_TT#

NTC

VW

COMP

FB

ISEN3

ISEN2

R20

0

EP

OPTIONAL

----

-----

----

C13 C12

38

40

39

VR_ON

CLK_EN#

DPRSLPVR

ISL62883HRZ

ISEN1

RTN

VSEN

12

11

-----

330PF

1000PF

-------------

----

-------------

36

35

37

VID5

VID6

U6

ISUM+

ISUM-

14

16

151318

C16

R26

C15

604

C81

820PF
OPTIONAL

67

33

34

VID3

VID4

VID2

IMON

VDD

VIN

17

R37

1

1UF

C17

82.5

C82

R30

0.01UF

R109

100

32

31

VID0

VID1

UGATE1

BOOT1

19

20

R40

0

0.22UF

C18

0.039UF

----

2

C39

C52

C57

270UF

C42

10UF

C44

270UF

C43

10UF

OUT

C40

270UF

C41

10UF

11

VSUM-

C55

C54

C50

OUT

C49

C60

C67

10UF10UF

10UF

C61

C68

10UF

C63

10UF

C71

10UF

10UF

C64

10UF

C72

10UF

VSUM-

LAYOUT NOTE:

ROUTE UGATE1 TRACE IN PARALLEL
WITH THE PHASE1 TRACE GOING TO
THE SOURCE OF Q2 AND Q8

1

ROUTE LGATE1 TRACE IN PARALLEL
WITH THE VSSP1 TRACE GOING TO

OUT

THE SOURCE OF Q3 AND Q9

SAME RULE APPLIES TO OTHER PHASES

VSUM-

JIA WEI

23

OUT

270UF

C47

10UF

C56

10UF

C65

10UF

C73

10UF

DATE:

JULY 2009

PAGE:

1

VCORE

C48

10UF

C59

10UF

C66

10UF

C74

10UF

1OF1

1

10UF10UF

10UF

10UF

D

ISL62883, ISL62883B

FIGURE 27. 3-PHASE REFERENCE DESIGN

June 21, 2011

FN6891.4

ISL62883, ISL62883B

Reference Design Bill of Materials

QTY REFERENCE VALUE DESCRIPTION MANUFACTURER PART NUMBER PACKAGE

1 C11 390pF Multilayer Cap, 16V, 10% GENERIC H1045-00391-16V10 SM0603

1 C12 330pF Multilayer Cap, 16V, 10% GENERIC H1045-00331-16V10 SM0603

1 C13 1000pF Multilayer Cap, 16V, 10% GENERIC H1045-00102-16V10 SM0603

1 C15 0.01µF Multilayer Cap, 16V, 10% GENERIC H1045-00103-16V10 SM0603

3 C16, C22, C26 1µF Multilayer Cap, 16V, 20% GENERIC H1045-00105-16V20 SM0603

1 C18 0.47µF Multilayer Cap, 16V, 10% GENERIC H1045-00474-16V10 SM0603

1 C20 0.1µF Multilayer Cap, 16V, 10% GENERIC H1045-00104-16V10 SM0603

8 C21, C7, C9, C10, C17,

C30, C31, C32

2 C24, C25 56µF Radial SP Series Cap, 25V, 20% SANYO 25SP56M CASE-CC

6 C27, C28, C29, C33,

C34, C35

1 C3 150pF Multilayer Cap, 16V, 10% GENERIC H1045-00151-16V10 SM0603

4 C39, C44, C52, C57 270µF SPCAP, 2V, 4.5MOHM

1 C4 1000pF Multilayer Cap, 16V, 10% GENERIC H1045-00102-16V10 SM0603

24 C40-C43, C47-C50,

C53-C56, C59-C69,

C78

1 C6 39pF Multilayer Cap, 16V, 10% GENERIC H1045-00390-16V10 SM0603

1 C81 820pF Multilayer Cap, 16V, 10% GENERIC H1045-00821-16V10 SM0603

1 C82 0.039µF Multilayer Cap, 16V, 10% GENERIC H1045-00393-16V10 SM0603

1 C83 560pF Multilayer Cap, 16V, 10% GENERIC H1045-00561-16V10 SM0603

3 L1, L2, L3 0.36µH Inductor, Inductance 20%, DCR 5% NEC-TOKIN

3 Q2, Q4, Q6 N-Channel Power MOSFET IR IRF7821 PWRPAKSO8

6 Q3, Q5, Q7, Q9, Q11,

Q13

3 Q8, Q10, Q12 DNP

1 R10 536 Thick Film Chip Resistor, 1% GENERIC H2511-05360-1/16W1 SM0603

1 R109 100 Thick Film Chip Resistor, 1% GENERIC H2511-01000-1/16W1 SM0603

1 R11 2.37k Thick Film Chip Resistor, 1% GENERIC H2511-02371-1/16W1 SM0603

1 R110 2.37k Thick Film Chip Resistor, 1% GENERIC H2511-02371-1/16W1 SM0603

1 R12 499 Thick Film Chip Resistor, 1% GENERIC H2511-04990-1/16W1 SM0603

1 R16 147k Thick Film Chip Resistor, 1% GENERIC H2511-01473-1/16W1 SM0603

2 R17, R18 10 Thick Film Chip Resistor, 1% GENERIC H2511-00100-1/16W1 SM0603

4 R19, R71, R72, R73 10k Thick Film Chip Resistor, 1% GENERIC H2511-01002-1/16W1 SM0603

1 R23 1.91k Thick Film Chip Resistor, 1% GENERIC H2511-01911-1/16W1 SM0603

1 R26 82.5 Thick Film Chip Resistor, 1% GENERIC H2511-082R5-1/16W1 SM0603

5 R20, R40, R56, R57,

R58

1 R30 604 Thick Film Chip Resistor, 1% GENERIC H2511-06040-1/16W1 SM0603

0.22µF Multilayer Cap, 16V, 10% GENERIC H1045-00224-16V10 SM0603

10µF Multilayer Cap, 25V, 20% GENERIC H1065-00106-25V20 SM1206

PANASONIC

POLYMER CAP, 2.5V, 4.5mΩ

10µF Multilayer Cap, 6.3V, 20% MURATA

N-Channel Power MOSFET IR IRF7832 PWRPAKSO8

0 Thick Film Chip Resistor, 1% GENERIC H2511-00R00-1/16W1 SM0603

KEMET

PANASONIC

TDK

PANASONIC

EEFS X0D471E4
T520V477M2R5A(1)E4R5

GRM21BR61C106KE15L
ECJ2FB0J106K
C2012X5R0J106K

MPCH1040LR36
ETQP4LR36AFC

SM0805

10mmx10mm

29

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Reference Design Bill of Materials (Continued)

QTY REFERENCE VALUE DESCRIPTION MANUFACTURER PART NUMBER PACKAGE

4 R37, R88, R90, R92 1 Thick Film Chip Resistor, 1% GENERIC H2511-01R00-1/16W1 SM0603

1 R38 11k Thick Film Chip Resistor, 1% GENERIC H2511-01102-1/16W1 SM0603

1R4 DNP

1 R41 2.61k Thick Film Chip Resistor, 1% GENERIC H2511-02611-1/16W1 SM0603

1 R42 10k NTC Thermistor, 10k NTC PANASONIC ERT-J1VR103J SM0603

1 R50 7.87k Thick Film Chip Resistor, 1% GENERIC H2511-07871-1/16W1 SM0603

1 R6 8.66k Thick Film Chip Resistor, 1% GENERIC H2511-08662-1/16W1 SM0603

3 R63, R65, R67 3.65k Thick Film Chip Resistor, 1% GENERIC H2511-03651-1/16W1 SM0805

2 R8, R9 DNP

1 R7 324k Thick Film Chip Resistor, 1% GENERIC H2511-03243-1/16W1 SM0603

1 U3 Synchronous Rectified MOSFET

Driver

1 U6 IMVP-6.5 PWM Controller INTERSIL ISL62883HRTZ QFN-40

INTERSIL ISL6208CBZ SOIC8_150_50

30

FN6891.4

June 21, 2011

Typical Performance

V

(V)

ISL62883, ISL62883B

92

90

88

86

84

82

80

78

EFFICIENCY(%)

76

74

72

70

0 5 10 15 20 25 30 35 40 45 50 55 60 65

V

= 8V

IN

V

= 12V

IN

V

= 19V

IN

I

(A)

OUT

FIGURE 28. 3-PHASE CCM EFFICIENCY, VID = 1.075V,

V

=8V, V

IN1

95

90

85

80

75

EFFICIENCY (%)

70

65

VIN = 8V

= 12.6V AND V

IN2

VIN = 12V

IN3

VIN = 19V

= 19V

1.10

1.08

1.06

1.04

1.02

(V)

1.00

OUT

V

0.98

0.96

0.94

0.92
0 5 10 15 20 25 30 35 40 45 50 55 60 65

I

OUT

(A)

FIGURE 29. 3-PHASE CCM LOAD LINE, VID = 1.075V,

V

OUT

0.885

0.875

0.865

0.855

0.845

0.835

IN1

=8V, V

= 12.6V AND V

IN2

IN3

= 19V

60

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

I

OUT

(A)

FIGURE 30. 2-PHASE CCM EFFICIENCY, VID = 0.875V,

V

=8V, V

IN1

95

90

85

80

75

EFFICIENCY (%)

70

65

60

0.1 1 10 100

VIN = 8V

VIN = 19V

= 12.6V AND V

IN2

I

OUT

VIN = 12V

(A)

IN3

= 19V

FIGURE 32. 1-PHASE DEM EFFICIENCY, VID = 0.875V,

V

=8V, V

IN1

= 12.6V AND V

IN2

IN3

= 19V

0.825
0 101112131415

123456789

I

OUT

(A)

FIGURE 31. 2-PHASE CCM LOAD LINE, VID = 0.875V,

V

=8V, V

IN1

0.885

0.875

0.865

(V)

0.855

OUT

V

0.845

0.835

0.825
0 101112131415

123456789

= 12.6V AND V

IN2

I

OUT

(A)

IN3

= 19V

FIGURE 33. 1-PHASE DEM LOAD LINE, VID = 0.875V,

V

IN1

=8V, V

= 12.6V AND V

IN2

IN3

= 19V

31

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Typical Performance (Continued)

FIGURE 34. SOFT-START, VIN= 19V, IO= 0A, VID = 0.95V,

Ch1: PHASE1, Ch2: V

FIGURE 36. CLK_EN# DELAY, V

Ch1: PHASE1, Ch2: V

, Ch3: PHASE2, Ch4: PHASE3

O

= 19V, IO=2A, VID=1.5V,

IN

, Ch3: IMON, Ch4: CLK_EN#

O

FIGURE 35. SHUT DOWN, V

Ch1: PHASE1, Ch2: V

= 19V, IO= 1A, VID = 0.95V,

IN

, Ch3: PHASE2, Ch4: PHASE3

O

FIGURE 37. PRE-CHARGED START UP, V

Ch1: PHASE1, Ch2: V

, Ch3: IMON, Ch4: VR_ON

O

= 19V, VID = 0.95V,

IN

FIGURE 38. STEADY STATE, V

Ch1: PHASE1, Ch2: V

= 19V, IO= 51A, VID = 0.95V,

IN

, Ch3: PHASE2, Ch4: PHASE3

O

32

1000

900

800

(mV)

700

600

SENSE

500

400

SPEC

300

IMON-VSS

200

100

0

0 5 10 15 20 25 30 35 40 45 50

VIN = 8V

I

OUT

VIN = 12V

(A)

VIN = 19V

FIGURE 39. IMON, VID = 1.075V

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Typical Performance (Continued)

FIGURE 40. LOAD TRANSIENT RESPONSE WITH OVERSHOOT

FIGURE 42. LOAD TRANSIENT RESPONSE WITH OVERSHOOT

REDUCTION FUNCTION DISABLED, V
CLARKSFIELD CPU TEST CONDITION: VID = 0.95V,
I

= 12A/51A, di/dt = “FASTEST”, LL = 1.9mΩ

O

REDUCTION FUNCTION DISABLED, V
CLARKSFIELD CPU TEST CONDITION: VID = 0.95V,
I

= 12A/51A, di/dt = “FASTEST”, LL = 1.9mΩ

O

=12V, SV

IN

=12V, SV

IN

FIGURE 41. LOAD TRANSIENT RESPONSE WITH OVERSHOOT

REDUCTION FUNCTION DISABLED, V
CLARKSFIELD CPU TEST CONDITION: VID = 0.95V,
I

= 12A/51A, di/dt = “FASTEST”, LL = 1.9mΩ

O

FIGURE 43. LOAD TRANSIENT RESPONSE WITH OVERSHOOT

REDUCTION FUNCTION DISABLED, V
CLARKSFIELD CPU TEST CONDITION: VID = 0.95V,
I

= 12A/51A, di/dt = “FASTEST”, LL = 1.9mΩ

O

=12V, SV

IN

=12V, SV

IN

FIGURE 44. 2-PHASE MODE LOAD INSERTION RESPONSE WITH

OVERSHOOT REDUCTION FUNCTION DISABLED,
3-PHASE CONFIGURATION, PSI# = 0, DPRSLPVR =
0, V

= 12V, VID = 0.875V, IO=4A/17A,

IN

di/d = “FASTEST

33

FIGURE 45. 2-PHASE MODE LOAD INSERTION RESPONSE WITH

OVERSHOOT REDUCTION FUNCTION DISABLED,
3-PHASE CONFIGURATION, PSI# = 0, DPRSLPVR=0,
V

= 12V, VID = 0.875V, IO= 4A/17A, di/dt =

IN

“FASTEST”

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Typical Performance (Continued)

FIGURE 46. PHASE ADDING/DROPPING (PSI# TOGGLE),

I

= 15A, VID = 1.075V, Ch1: PHASE1, Ch2: VO,

O

Ch3: PHASE2, Ch4: PHASE3

FIGURE 48. VID ON THE FLY, 1.075V/0.875V, 3-PHASE

CONFIGURATION, PSI#=1, DPRSLPVR=0, Ch1:
PHASE1, Ch2: V

, Ch3: PHASE2, Ch4: PHASE3

O

FIGURE 47. DEEPER SLEEP MODE ENTRY/EXIT,

I

= 1.5A, HFM VID = 1.075V, LFM VID = 0.875V,

O

DEEPER SLEEP VID = 0.875V, Ch1: PHASE1, Ch2:
V

, Ch3: PHASE2, Ch4: PHASE3

O

FIGURE 49. VID ON THE FLY, 1.075V/0.875V, 3-PHASE

CONFIGURATION, PSI#=0, DPRSLPVR=0, Ch1:
PHASE1, Ch2: V

, Ch3: PHASE2, Ch4: PHASE3

O

FIGURE 50. VID ON THE FLY, 1.075V/0.875V, 3-PHASE

CONFIGURATION, PSI# = 0, DPRSLPVR = 1, Ch1:
PHASE1, Ch2: V

, Ch3: PHASE2, Ch4: PHASE3

O

34

FIGURE 51 . VID ON THE FLY, 1 .075V /0.875V, 3-P HASE

CONFIGURATION, PSI# = 1, DPRSLPVR = 1, Ch1:
PHASE1, Ch2: V

, Ch3: PHASE2, Ch4: PHASE3

O

June 21, 2011

FN6891.4

ISL62883, ISL62883B

Typical Performance (Continued)

Phase Margin

Gain

FIGURE 52. LOAD TRANSIENT RESPONSE WITH OVERSHOOT

REDUCTION FUNCTION ENABLED, V

=12V, SV

IN

CLARKSFIELD CPU TEST CONDITION: VID = 0.95V,
I

= 12A/51A, di/dt = “FASTEST”, LL = 1.9mΩ,

O

Ch1: LGATE1, Ch2: V

, Ch3: LGATE2, Ch4: ISL6208

O

LGATE

1000

900

800

700

(mV)

600

SENSE

500

400

SPEC

300

IMON-VSS

200

100

0

0 5 10 15 20 25 30 35 40 45 50

VIN = 8V

I

(A)

OUT

VIN = 12V

VIN = 19V

FIGURE 54. IMON, VID = 1.075V

FIGURE 53. REFERENCE DESIGN LOOP GAIN T2(s)

MEASUREMENT RESULT

5.0

4.5

4.0

3.5

3.0
PSI# = 0, DPRSLPVR = 0, 2-PHASE CCM

2.5

2.0

Z(f) (mΩ)

1.5

1.0

0.5

0.0

1k 10k

PSI# = 1, DPRSLPVR = 0, 3-PHASE CCM

100k

FREQUENCY (Hz)

FIGURE 55. REFERENCE DESIGN FDIM RESULT

1M

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

35

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Package Outline Drawing

L40.5x5

40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 9/10

6

PIN 1

INDEX AREA

(4X)

0.15

PACKAGE OUTLINE

3.50

5.00

5.00

TOP VIEW

A

B

0.40

4X 3.60

36X 0.40

5.00

40X 0.4± 0 .1

0.750

0.050

(36X 0.40

BOTTOM VIEW

SIDE VIEW

6

PIN #1 INDEX AREA

0.20

b

4

SEE DETAIL “X”

//

BASE PLANE
SEATING PLANE

3.50

B0.10 M AC

C0.10

C

0.08

C

TYPICAL RECOMMENDED LAND PATTERN

36

(40X 0.20)

(40X 0.60)

0.2 REF

C

NOTES:

Dimensions are in millimeters.1.

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

2.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

Dimension b applies to the metallized terminal and is measured

4.

between 0.15mm and 0.27mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

The configuration of the pin #1 identifier is optional, but must be

6.
located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

JEDEC reference drawing: MO-220WHHE-1

7.

5

0.00 MIN

0.05 MAX

DETAIL "X"

FN6891.4

June 21, 2011

ISL62883, ISL62883B

Package Outline Drawing

L48.6x6

48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 4/07

6

PIN 1

INDEX AREA

6.00

A

B

4X

4.4

0.40

44X

37

36

48

6

PIN #1 INDEX AREA

1

(4X)

( 5. 75 TYP )

0.15

( 4. 40 )

TOP VIEW

TYPICAL RECOMMENDED LAND PATTERN

6.00

( 44 X 0 . 40 )

( 48X 0 . 20 )

( 48X 0 . 65 )

MAX 0.80

4 .40 ± 0.15

25

24

48X 0.45 ± 0.10

BOTTOM VIEW

SIDE VIEW

0 . 2 REF

C

0 . 00 MIN.

0 . 05 MAX.

5

12

13

4

0.10 CM

0.05 M

48X 0.20

SEE DETAIL "X"

BASE PLANE

AB

C

C

0.10

SEATING PLANE

C

0.08 C

DETAIL "X"

37

NOTES:

Dimensions are in millimeters.1.
Dimensions in ( ) for Reference Only.

2.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4.

Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

The configuration of the pin #1 identifier is optional, but must be

6.
located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN6891.4

June 21, 2011