Datasheet ISL6262CRZ, ISL6262IRZ Datasheet (Intersil)

ISL6262

Data Sheet May 15, 2006

Two-Phase Core Regulator for IMVP-6 Mobile CPUs

The ISL6262 is a two-phase buck converter regulator implementing Intel® IMVP-6 protocol, with embedded gate drivers. The two-phase buck converter uses two interleaved channels to effectively double the output voltage ripple frequency and thereby reduce output voltage ripple amplitude with fewer components, lower component cost, reduced power dissipation, and smaller real estate area.

The heart of the ISL6262 is R Robust Ripple Regulator modulator. Compared with the traditional multiphase buck regulator, the R has the fastest transient response. This is due to the R modulator commanding variable switching frequency during a load transient.

Intel Mobile Voltage Positioning (IMVP) is a smart voltage regulation technology, which ef fectively reduces power dissipation in Intel Pentium processors. To boost battery life, the ISL6262 supports DPRSLRVR (deeper sleep), DPRSTP# and PSI# functions and maximizes the efficiency via automatically enabling different phase operation modes. At heavy load operation of the active mode, the regulator commands the two phase continuous conduction mode (CCM) operation. While the PSI# is asserted at the medium load in the active mode, the ISL6262 smoothly disables one phase and operates in a one-phase CCM. When the CPU enters deeper sleep mode, the ISL6262 enables diode emulation to maximize the efficiency at the light load.

A 7-bit digital-to-analog converter (DAC) allows dynamic adjustment of the core output voltage from 0.300V to 1.500V . A 0.5% system accuracy of the core output voltage over temperature is achieved by the ISL6262.

A unity-gain differential amplifier is provided for remote CPU die sensing. This allows the voltage on the CPU die to be accurately measured and regulated per Intel IMVP-6 specifications. Current sensing can be realized using either lossless inductor DCR sensing or precision resistor sensing. A single NTC thermistor network thermally compensates the gain and the time constant of the DCR variations.

Technology™, Intersil’s

Technology™

FN9199.2

Features

• Precision Two-phase CORE Voltage Regulator

- 0.5% System Accuracy Over Temperature

- Enhanced load line accuracy

• Internal Gate Driver with 2A Driving Capability

• Dynamic Phase Adding/Dropping

• Microprocessor Voltage Identification Input

- 7-Bit VID Input

- 0.300V to 1.500V in 12.5mV Steps

- Support VID Change on-the-fly

• Multiple Current Sensing Schemes Supported

- Lossless Inductor DCR Current Sensing

- Precision Resistive Current Sensing

• Thermal Monitor

• User Programmable Switching Frequency

• Differential Remote CPU Die Voltage Sensing

• Static and Dynamic Current Sharing

• Overvoltage, Undervoltage, and Overcurrent Protection

• Pb-Free Plus Anneal Available (RoHS Compliant)

Ordering Information

PART

NUMBER

ISL6262CRZ (Note)

ISL6262CRZ-T (Note)

ISL6262IRZ (Note)

ISL6262IRZ-T (Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

ISL6262CRZ -10 to 100 48 Ld 7x7 QFN

ISL6262IRZ -40 to 100 48 Ld 7x7 QFN

TEMP.

(°C) PACKAGE

(Pb-free)

PKG.

DWG. #

L48.7x7

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Technology™ is a trademark of Intersil Americas Inc.

Pinout

ISL6262

ISL6262 (7x7 QFN)

TOP VIEW

3V3

CLK_EN#

DPRSTP#

DPRSLPVR

VR_ON

VID6

VID5

VID4

VID3

VID2

VID1

48 47 46 45 44 43 42 41 40 39 38 37

VID0

PGOOD

PSI#

PGD_IN

RBIAS

VR_TT#

NTC

SOFT

OCSET

COMP

FB2

13 14 15 16 17 18 19 20 21 22 23 24

RTN

VSEN

VDIFF

DFB

DROOP

GND PAD

(BOTTOM)

VIN

VSUM

GND

VDD

BOOT1

UGATE1

PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2

PHASE2

UGATE2

BOOT2

ISEN2

ISEN1

FN9199.2

May 15, 2006

ISL6262

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 -+7V

Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V

Boot1,2 and UGATE1,2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30V

ALL Other Pins. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)

Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . . . -0.3 -+7V

Recommended Operating Conditions

Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V

Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . -10°C to 100°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . -10°C to 125°C

Ambient Temperature, Industrial . . . . . . . . . . . . . . . -40°C to 100°C

Junction Temperature, Industrial . . . . . . . . . . . . . . . -40°C to 125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

Tech Brief TB379.

2. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

Thermal Resistance (Typical)

θJA

°C/W θJC°C/W

QFN Package (Notes 1, 2). . . . . . . . . . 29 4.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

Electrical Specifications V

= 5V, TA = -40°C to 100°C, Unless Otherwise Specified.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

INPUT POWER SUPPLY

+5V Supply Current I

VDD

VR_ON = 3.3V - 3.1 3.6 mA

VR_ON = 0V - - 1 µA +3.3V Supply Current I Battery Supply Current at VIN pin I

3V3 VIN

POR (Power-On Reset) Threshold POR

POR

No load on CLK_EN# - - 1 µA

VR_ON = 0V, VIN = 25V, - - 1 µA

VDD Rising - 4.35 4.5 V

VDD Falling 3.9 4.1 - V

SYSTEM AND REFERENCES

System Accuracy %Error

cc_core

ISL6262CRZ

No load, closed loop, active mode,

)

TA = 0°C to 100°C, VID = 0.75-1.5V -0.5 - 0.5 %

VID = 0.5-0.7375V -8 - 8 mV

VID = 0.3-0.4875V -15 - 15 mV

%Error

cc_core

ISL6262IRZ

)

= -40°C to 100°C, VID = 0.75-1.5V -0.8 - 0.8 %

VID = 0.5-0.7375V -10 - 10 mV

VID = 0.3-0.4875V -18 - 18 mV RBIAS Voltage R Boot Voltage V Maximum Output Voltage V

RBIAS BOOT

CC_CORE

(max)

CC_CORE

(min)

= 147kΩ 1.45 1.47 1.49 V

RBIAS

1.188 1.2 1.212 V

VID = [0000000] - 1.5 - V

VID = [1100000] - 0.3 - V

VID Off State VID = [1111111] - 0 - V

CHANNEL FREQUENCY

Nominal Channel Frequency f

= 3.9kΩ, 2 channel operation,

FSET

= 2V

comp

-300-kHz

Adjustment Range 200 - 500 kHz

FN9199.2

May 15, 2006

ISL6262

Electrical Specifications V

= 5V, TA = -40°C to 100°C, Unless Otherwise Specified. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

AMPLIFIERS

Droop Amplifier Offset -0.3 - 0.3 mV Error Amp DC Gain A

Error Amp Gain-Bandwidth Product GBW C Error Amp Slew Rate SR C FB Input Current I

IN(FB)

= 20pF - 18 - MHz

= 20pF - 5 - V/µs

-90-dB

- 10 150 nA

ISEN

Imbalance Voltage --1mV Input Bias Current -20-nA

SOFT-START CURRENT

Soft-Start Current I Soft Geyserville Current I Soft Deeper Sleep Entry Current I Soft Deeper Sleep Exit Current I Soft Deeper Sleep Exit Current I

C4 C4EA C4EB

|SOFT - REF|>100mV ±170 ±200 ±230 µA DPRSLPVR = 3.3V -47 -41 -35 µA DPRSLPVR = 3.3V 35 41 47 µA DPRSLPVR = 0V 170 200 230 µA

-47 -41 -35 µA

GATE DRIVER DRIVING CAPABILITY

UGATE Source Resistance R UGATE Source Current I UGATE Sink Resistance R UGATE Sink Current I LGATE Source Resistance R LGATE Source Current I LGATE Sink Resistance R LGATE Sink Current I UGATE to PHASE Resistance R

SRC(UGATE)

SRC(UGATE)VUGATE_PHASE

SNK(UGATE)

SNK(UGATE)VUGATE_PHASE

SRC(LGATE)

SRC(LGATE)VLGATE

SNK(LGATE)

SNK(LGATE)VLGATE

p(UGATE)

500mA Source Current - 1 1.5 Ω

= 2.5V - 2 - A

500mA Sink Current - 1 1.5 Ω

= 2.5V - 2 - A

500mA Source Current - 1 1.5 Ω

= 2.5V - 2 - A

500mA Sink Current - 0.5 0.9 Ω

= 2.5V - 4 - A

-1.1-kΩ GATE DRIVER SWITCHING TIMING (refer to timing diagram) UGATE Turn-On Propagation Delay t

ISL6262CRZ

PDHU

= -10°C to 100°C

= 5V, Outputs Unloaded

= 5V, Outputs Unloaded 18 30 44 ns

20 30 44 ns

ISL6262IRZ

LGATE Turn-On Propagation Delay t

ISL6262CRZ

PDHL

= -10°C to 100°C

= 5V, Outputs Unloaded

= 5V, Outputs Unloaded 5 15 30 ns

71530ns

ISL6262IRZ

BOOTSTRAP DIODE

Forward Voltage V Leakage V

= 5V, Forward Bias Current = 2mA 0.43 0.58 0.72 V

DDP

= 16V - - 1 µA

POWER GOOD and PROTECTION MONITOR

PGOOD Low Voltage V PGOOD Leakage Current I

= 4mA - 0.11 0.4 V

PGOOD

= 3.3V -1 - 1 µA

GOOD

FN9199.2

May 15, 2006

ISL6262

Electrical Specifications V

= 5V, TA = -40°C to 100°C, Unless Otherwise Specified. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

PGOOD Delay t

ISL6262CRZ

pgd

= -10°C to 100°C

5.5 6.8 8.1 ms

CLK_EN# Low to PGOOD High CLK_EN# Low to PGOOD High 5.3 6.8 8.1 ms

ISL6262IRZ Overvoltage Threshold O Severe Overvoltage Threshold O

VHS

VO rising above setpoint > 1ms 160 200 240 mV

VO rising above setpoint > 0.5µs 1.675 1.7 1.725 V OCSET Reference Current I(Rbias) = 10µA 9.8 10 10.2 µA OC Threshold Offset DROOP rising above OCSET > 120µs -3.5 - 3.5 mV Current Imbalance Threshold Difference between ISEN1 and ISEN2 > 1ms - 7.5 - mV Undervoltage Threshold

VO falling below setpoint for > 1ms -365 -300 -240 mV (VDIFF-SOFT)

LOGIC INPUTS

VR_ON, DPRSLPVR and PGD_IN

--1V

Input Low VR_ON, DPRSLPVR and PGD_IN

Input High Leakage Current of VR_ON and

PGD_IN

Leakage Current of DPRSLPVR I

DAC(VID0-VID6), PSI# and DPRSTP# Input Low

DAC(VID0-VID6), PSI# and

IL_DPRSLP

IH_DPRSLP

2.3 - - V

Logic input is low -1 0 - µA

Logic input is high at 3.3V - 0 1 µA

DPRSLPVR input is low -1 0 - µA

DPRSLPVR input is high at 3.3V - 0.45 1 µA

--0.3V

0.7 - - V

DPRSTP# Input High Leakage Current of DAC(VID0-

VID6), PSI# and DPRSTP#

Logic input is low -1 0 - µA

Logic input is high at 1V - 0.45 1 µA

THERMAL MONITOR

NTC Source Current NTC = 1.3 V 53 60 68 µA Over-Temperature Threshold V(NTC) falling 1.165 1.18 1.205 V VR_TT# Low Output Resistance R

I = 20mA - 5 9 Ω

CLK_EN# OUTPUT LEVELS

CLK_EN# High Output Voltage V CLK_EN# Low Output Voltage V

OH OL

3V3 = 3.3V, I = -4mA 2.9 3.1 - V

CLK_EN#

= 4mA - 0.18 0.4 V

FN9199.2

May 15, 2006

ISL6262 Gate Driver Timing Diagram

PWM

PDHU

UGATE

ISL6262

LGATE

Functional Pin Description

PSI#

RBIAS

NTC

SOFT

PGOOD

PGD_IN

VR_TT#

OCSET

PDHL

3V3

CLK_EN#

DPRSTP#

DPRSLPVR

VR_ON

VID6

VID5

48 47 46 45 44 43 42 41 40 39 38 37

GND PAD

(BOTTOM)

VID4

VID3

VID2

VID1

VID0

BOOT1

UGATE1

PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2

PHASE2

COMP

FB2

13 14 15 16 17 18 19 20 21 22 23 24

RTN

VSEN

VDIFF

DROOP

PGOOD - Power good open-drain output. Will be pulled up

externally by a 680Ω resistor to VCCP or 1.9kΩ to 3.3V . PSI# - Low load current indicator input. When asserted low,

indicates a reduced load-current condition, and product goes into single phase operation.

PGD_IN - Digital Input. When asserted high, indicates VCCP and VCC_MCH voltages are within regulation.

UGATE2

BOOT2

DFB

VSUM

VIN

VDD

GND

ISEN2

ISEN1

RBIAS - 147K resistor to VSS sets internal current

reference. VR_TT# - Thermal overload output indicator with open-drain

output. Over temperature pull-down resistance is 10Ω. NTC - Thermistor input to VRTT# circuit and a 60µA current

source is connected internally to this pin.

FN9199.2

May 15, 2006

ISL6262

SOFT - A capacitor from this pin to GND pin sets the maximum slew rate of the output voltage. The SOFT pin is the non-inverting input of the error amplifier.

OCSET - Overcurrent set input. A resistor from this pin to VO sets DROOP voltage limit for OC trip. A 10µA current source is connected internally to this pin.

VW - A resistor from this pin to COMP programs the switching frequency (exa. 4.42kΩ ≅ 300kHz).

COMP - This pin is the output of the error amplifier. FB - This pin is the inverting input of error amplifier. FB2 - There is a switch between FB2 pin and the FB pin.

The switch is closed in single-phase operation and is opened in two phase operation. The components connecting to FB2 is to adjust the compensation in single phase operation to achieve optimum performance.

VDIFF - This pin is the output of the differential amplifier. VSEN - Remote core voltage sense input. RTN - Remote core voltage sense return. DROOP - Output of the droop amplifier. The voltage level on

this pin is the sum of Vo and the programmed droop voltage by the external resistors.

DFB - Inverting input to droop amplifier. VO - An input to the IC that reports the local output voltage.

LGATE1 - Lower-side MOSFET gate signal for phase 1. PGND1 - The return path of the lower gate driver for

phase 1. PHASE1 - The phase node of phase 1. This pin should

connect to the source of upper MOSFET.

UGATE1 - Upper MOSFET gate signal for phase 1. BOOT1 - This pin is the upper gate driver supply voltage for

phase 1. An internal boot strap diode is connected to the PVCC pin.

VID0, VID1, VID2, VID3, VID4, VID5, VID6 - VID input with VID0 is the least significant bit (LSB) and VID6 is the most significant bit (MSB).

VR_ON - Digital input enable. A high level logic signal on this pin enables the regulator.

DPRSLPVR - Deeper sleep enable signal. A high level logic indicates the micro-processor is in Deeper Sleep Mode and also indicates a slow C4 entry or exit rate with 41µA discharging or charging the SOFT cap.

DPRSTP# - Deeper sleep slow wake up signal. A low level logic signal on this pin indicates the micro-processor is in deeper sleep mode.

CLK_EN# - Digital output for system PLL clock. Goes active 10µs after PGD_IN is active and Vcore is within 10% of Boot voltage.

VSUM - This pin is connected to the summation junction of channel current sensing.

VIN - Battery supply voltage. It is used for input voltage feedforward to improve the input line transient performance.

VSS - Signal ground. Connect to local controller ground. VDD - 5V control power supply. ISEN2 - Individual current sharing sensing for channel 2. ISEN1 - Individual current sharing sensing for channel 1. N/C - Not connected. Grounding this pin to signal ground in

the practical layout. BOOT2 - This pin is the upper gate driver supply voltage for

phase 2. An internal boot strap diode is connected to the PVCC pin.

UGATE2 - Upper MOSFET gate signal for phase 2. PHASE2 - The phase node of phase 2. This pin should

connect to the source of upper MOSFET. PGND2 - The return path of the lower gate driver for

phase 2.

LGATE2 - Lower-side MOSFET gate signal for phase 2.

3V3 - 3.3V supply voltage for CLK_EN#.

PVCC - 5V power supply for gate drivers.

FN9199.2

May 15, 2006

Functional Block Diagram

ISL6262

PVCC

VDD

VIN

ISEN2

ISEN1

3V3

PGOOD

CLK_EN#

PGD_IN

6µA

54µA

PVCC

VIN

NTC

VR_TT#

1.18V

CURRENT BALANCE

PGOOD

MONITOR

AND LOGIC

FLT

FAULT AND

PGOOD

LOGIC

I_BALF

GOOD

1.2V

BOOT1

PVCC

VSOFT

VIN

CH1

CH1 CH2

CONTROL

UGATE1

FLT

PHASE

LOGIC

PHASE1

PVCC

DRIVER

LOGIC

MODULATOR

SINGLE PHASE

SOFT

LGATE1

PGND1

PVCC

ULTRA-

SONIC TIMER

VSOFT

CH2

PHASE

SEQUENCER

SINGLE PHASE

BOOT2

VIN

PHASE2

UGATE2

DRIVER

LOGIC

FLT

MODULATOR

VO VIN

PVCC

VSOFT

LGATE2

E/A

PGND2

SINGLE

PHASE

GND

COMP

FB2

FB SOFT

VDIFF

RBIAS

DPRSLPVR

0.5

10µA

DPRSTP#

DROOP

OCSET

VID0

VID1

DAC

VID2

DACOUT

VID3

VID4

VID5

REQUEST

MODE CHANGE

VID6

MODE

CONTROL

PSI#

VR_ON

FIGURE 1. SIMPLIFIED FUNCTION BLOCK DIAGRAM OF ISL6262

1 +

DFB

VSUM

DROOP

RTN

VSEN

FN9199.2

May 15, 2006

ISL6262

Typical Performance Curves 300kHz, DCR Sense, 2xIRF7821/2xIRF7832 Per Phase

100

VIN = 8.0V

90 80 70 60 50 40

EFFICIENCY (%)

30 20 10

0 5 10 15 20 25 30 35 40 45 50

VIN = 12.6V

= 19.0V

OUT

(A)

FIGURE 2. ACTIVE MODE EFFICIENCY , 2 PHASE, CCM,

PSI# = HIGH, VID = 1.15V

100

VIN = 8.0V

90 80 70 60 50 40

EFFICIENCY (%)

30 20 10

02468101214161820

VIN = 12.6V

VIN = 19.0V

OUT

(A)

FIGURE 4. ACTIVE MODE EFFICIENCY , 1 PHASE, CCM,

PSI# = LOW, VID = 1.15V

1.16

VIN = 8.0V

VIN = 12.6V

= 19.0V

01020304050

(A)

OUT

(V)

OUT

1.14

1.12

1.10

1.08

1.06

1.04

1.02

FIGURE 3. ACTIVE MODE LOAD LINE, 2 PHASE, CCM,

PSI# = HIGH, VID = 1.15V

1.16

1.15

1.14

(V)

1.13

OUT

1.12

1.11

1.10

0 4 6 8 10 20

2 12141618

VIN = 12.6V

VIN = 19.0V

OUT

VIN = 8.0V

(A)

FIGURE 5. ACTIVE MODE LOAD LINE, 1 PHASE, CCM,

PSI# = LOW, VID = 1.15V

100

EFFICIENCY (%)

0.1 1 10

VIN = 8.0V

VIN = 19.0V

VIN = 12.6V

(A)

OUT

FIGURE 6. DEEPER SLEEP MODE EFFICIENCY , 1 PHASE,

DCM MODE, VID = 0.7625V

0.765

0.76

0.755

(V)

0.75

OUT

0.745

0.74

0.735 0246810

OUT

VIN = 8.0V

VIN = 19.0V

VIN = 12.6V

(A)

FIGURE 7. DEEPER SLEEP MODE LOAD LINE, 1 PHASE,

DCM MODE, VID = 0.7625V

FN9199.2

May 15, 2006

ISL6262

Typical Performance Curves 0.36µH Filter Inductor and 4 x 330µF Output SP Caps

OUT

SOFT

VR_ON

= 15nF

VR_ON

SOFT

OUT

= 15nF

FIGURE 8. SOFT-ST ART WA VEFORM SHOWING SLEW RA TE

OF 2.5mV/µs AT VID = 1V, I

LOAD

= 10A

@ 1.4375V

OUT

@ 1.2V

OUT

PGD_IN

IMVP-6_PWRGD

CLK_EN#

FIGURE 10. SOFT-ST ART W AVEFORM SHOWING CLK_EN#

AND IMVP-6 PGOOD

IIN

LINE TRANSIENT

FIGURE 9. SOFT-ST ART WA VEFORM SHOWING SLEW RA TE

OF 2.5mV/µs AT VID = 1.4375V, I

OUT

IIN

FIGURE 11. INRUSH CURRENT AT START -UP, V

VID = 1.4375V, I

LOAD

= 10A

LOAD

IL1, IL2

= 10A

= 8V ,

OUT

FIGURE 12. 8V-20V INPUT LINE TRANSIENT RESPONSE,

= 240µF

FIGURE 13. 2 PHASE CURRENT BALANCE, FULL LOAD = 50A

FN9199.2

May 15, 2006

ISL6262

Typical Performance Curves 0.36µH Filter Inductor and 4 x 330µF Output SP Caps (Continued)

OUT

LOAD TRANSIENT

FIGURE 14. LOAD STEP-UP RESPONSE VIA CPU SOCKET

MPGA479, 35A LOAD STEP @ 200A/µs, 2 PHASE CCM

OUT

VID3

OUT

DYNAMIC VID

ACTIVE MODE

PHASE1,

PHASE2

FIGURE 15. VID3 CHANGE OF 010X000 FROM 1.V TO 1.1V AT

DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1

VID3

OUT

LOAD TRANSIENT

FIGURE 16. LOAD DUMP RESPONSE VIA CPU SOCKET

MPGA479, 35A LOAD STEP @ 200A/µs, 2 PHASE CCM

PSI#

CORE

PHASE1

DROP PHASE IN

ACTIVE MODE

PHASE2

DYNAMIC VID

ACTIVE MODE

PHASE1, PHASE2

FIGURE 17. VID3 CHANGE OF 010X000 FROM 1.1V TO 1V AT

DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1

PSI#

CORE

PHASE2

PHASE1

ADD PHASE IN ACTIVE MODE

FIGURE 18. 2-CCM TO 1-CCM UPON PSI# ASSERTION WITH

VID LSB CHANGE, AT DPRSLPVR = 0, DPRSTP# = 1, I

LOAD

= 10A

FIGURE 19. 1-CCM TO 2-CCM UPON PSI# DEASSERTION

WITH VID LSB CHANGE AT DPRSLPVR = 0, DPRSTP# = 1

FN9199.2

May 15, 2006

ISL6262

Typical Performance Curves 0.36µH Filter Inductor and 4 x 330µF Output SP Caps (Continued)

DPRSLPVR

OUT

PHASE1

PHASE2

C4 ENTRY WITH

PSI# ASSERTION

FIGURE 20. C4 ENTER WITH VID CHANGE 0011X00 FROM

1.2V TO 1.15V, I 2-CCM TO 1-DCM, PSI# TOGGLE FROM 1 TO 0

= 2A, TRANSITION OF

LOAD

WITH DPRSLPVR FROM 0 TO 1

DPRSLPVR

FAST BREAK C4 EXIT

OUT

DPRSLPVR

C4 EXIT/PHASE ADD

OUT

PHASE1

PHASE2

FIGURE 21. VID3 CHANGE OF 010X000 FROM 1.V TO 1.1V AT

DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1

DPRSLPVR

OUT

C4 ENTRY WITH PSI# = 0

PHASE1

PHASE2

FIGURE 22. FAST BREAK C4 EXIT AT LOAD = 0.1A FIGURE 23. C4 ENTRY WITH VID CHANGE OF 011X011 FROM

0.8625V TO 0.7625V, I 1-DCM

= 3A, 1-CCM TO

LOAD

OUT

PGOOD

IL1, IL2

PHASE1

OUT

FIGURE 24. OVERCURRENT PROTECTION FIGURE 25. 1.7V OVERVOL T AGE PROTECTION SHOWS

OUTPUT VOLTAGE PULLED LOW TO 0.9V AND PWM THREE-STATE

FN9199.2

May 15, 2006

ISL6262

Simplified Application Circuit for DCR Current Sensing

VIN

UGATE1

BOOT1

PHASE1

LGATE1

PGND2

ISEN1

UGATE2

BOOT2

PHASE2

LGATE2

PGND2

ISEN2

VSUM

OCSET

NTC

NETWORK

VSUM

VO'

VR_TT#

VID<0:6>

DPRSTP#

DPRSLPVR

PSI#

MCHOK

CLK_ENABLE#

VR_ON

IMVP-6_PWRGD

REMOTE

SENSE

+3.3

3V3

VDD

PVCC

RBIAS

NTC

VR_TT#

SOFT

VIDs

DPRSTP#

ISL6262

DPRSLPVR PSI#

PGD_IN

CLK_EN#

VR_ON

PGOOD VSEN

FSET

RTN

VDIFF

FB2 FB

COMP

GND

DROOPDFB

ISEN2

VSUM

ISEN1

VO'

VSUM

FIGURE 26. ISL6262 BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING

FN9199.2

May 15, 2006

ISL6262

Simplified Application Circuit for Resistive Current Sensing

VIN

UGATE1

BOOT1

PHASE1

LGATE1

PGND2

ISEN1

UGATE2

BOOT2

PHASE2

LGATE2

PGND2

ISEN2

VSUM

OCSET

VSUM

VO'

VR_TT#

VID<0:6>

DPRSTP#

DPRSLPVR

PSI#

MCHOK

CLK_ENABLE#

VR_ON

IMVP-6_PWRGD

REMOTE

SENSE

+3.3

3V3

VDD

PVCC

RBIAS

NTC

VR_TT#

SOFT

VIDs

DPRSTP#

ISL6262

DPRSLPVR PSI#

PGD_IN

CLK_EN#

VR_ON

PGOOD VSEN

FSET

RTN

VDIFF

FB2 FB

COMP

GND

DROOPDFB

ISEN2

VSUM

ISEN2

VO'

VSUM

FIGURE 27. ISL6262 BASED TWO-PHASE BUCK CONVERTER WITH RESISTIVE CURRENT SENSING

FN9199.2

May 15, 2006

Theory of Operation

The ISL6262 is a two-phase regulator implementing Intel® IMVP-6 protocol and includes embedded gate drivers for reduced system cost and board area. The regulator provides optimum steady-state and transient performance for microprocessor core applications up to 50A. System efficiency is enhanced by idling one phase at low-current and implementing automatic DCM-mode operation.

The heart of the ISL6262 is R Robust Ripple Regulator modul a to r. The R combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. The ISL6262 modulator internally synthesizes an analog of the inductor ripple current and uses hysteretic comparators on those signals to establish PWM pulse widths. Operating on these large-amplitude, noise-free synthesized signals allows the ISL6262 to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency PWM controllers. Unlike conventional hysteretic converters, the ISL6262 has an error amplifier that allows the controller to maintain a 0.5% voltage regulation accuracy throughout the VID range from 0.75V to

1.5V. The hysteresis window voltage is relative to the error

amplifier output such that load current transients results in increased switching frequency, which gives the R a faster response than conventional fixed frequency PWM controllers. Transient load current is inherently shared between active phases due to the use of a common hysteretic window voltage. Individual average phase voltages are monitored and controlled to equally share the static current among the active phases.

Start-Up Timing

With the controller's +5V VDD voltage above the POR threshold, the start-up sequence begins when VR_ON exceeds the 3.3V logic HIGH threshold. Approximately 100µs later, SOFT and VOUT begin ramping to the boot voltage of 1.2V. At start-up, the regulator always operates in a 2-phase CCM mode, regardless of control signal assertion levels. During this internal, the SOFT cap is charged by 41µA current source. If the SOFT capacitor is selected to be 20nF, the SOFT ramp will be at 2mV/s for a soft-start time of 600µs. Once VOUT is within 10% of the boot voltage and PGD_IN is HIGH for six PWM cycles (20µs for frequency = 300kHz), then CLK_EN# is pulled LOW and the SOFT cap is charged/discharged by approximate 200µA. Therefore, VOUT slews at +10mV/s to the voltage set by the VID pins. Approximately 7ms later, PGOOD is asserted HIGH. Typical start-up timing is shown in Figure 28.

Technology™, Intersil’s

modulator

regulator

ISL6262

VR_ON

100µs

SOFT & VO

PGD_IN

CLK_EN#

IMVP-6 PGOOD

FIGURE 28. SOFT-START WA VEFO RMS USING A 20nF SOFT

CAPACITOR

2mV/µs

10mV/µs

VBOOT

20µs

6.8ms

VID COMMANDED VOLTAGE

PGD_IN Latch

It should be noted that PGD_IN going low will cause the converter to latch off. This state will be cleared when VR_ON is toggled. This feature allows the converter to respond to other system voltage outages immediately.

Static Operation

After the start sequence, the output voltage will be regulated to the value set by the VID inputs per Table 1. The entire VID table is presented in the intel IMVP-6 specification. The ISL6262 will control the no-load output voltage to an accuracy of ±0.5% over the range of 0.75V to 1.5V.

TABLE 1. TRUNCATED VID TABLE FOR INTEL IMVP-6

VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOUT (V)

00000001.5000

00000011.4875

00001011.4375

00100011.2875

00111001.15

01101010.8375

01110110.7625

11000000.3000

11111110.0000

A fully-differential amplifier implements core voltage sensing for precise voltage control at the microprocessor die. The inputs to the amplifier are the VSEN and RTN pins.

As the load current increases from zero, the output voltage will droop from the VID table value by an amount proportional to current to achieve the IMVP-6 load line. The ISL6262 provides for current to be measured using either resistors in series with the channel inductors as shown in the application circuit of Figure 27, or using the intrinsic series

SPECIFICATION

FN9199.2

May 15, 2006

ISL6262

resistance of the inductors as shown in the application circuit of Figure 26. In both cases signals representing the inductor currents are summed at VSUM, which is the non-inverting input to the DROOP amplifier shown in the block diagram of Figure 1. The voltage at the DROOP pin minus the output voltage, VO´, is a high-bandwidth analog of the total inductor current. This voltage is used as an input to a differential amplifier to achieve the IMVP-6 load line, and also as the input to the overcurrent protection circuit.

When using inductor DCR current sensing, a single NTC element is used to compensate the positive temperature coefficient of the copper winding thus maintaining the loadline accuracy.

In addition to monitoring the total current (used for DROOP and overcurrent protection), the individual channel average currents are also monitored and used for balancing the load between channels. The IBAL circuit will adjust the channel pulse-widths up or down relative to the other channel to cause the voltages presented at the ISEN pins to be equal.

The ISL6262 controller can be configured for two-channel operation, with the channels operating 180 degrees apart. The channel PWM frequency is determined by the value of R

connected to pin VW as shown in Figure 26 and

FSET

Figure 27. Input and output ripple frequencies will be the channel PWM frequency multiplied by the number of active channels.

High Efficiency Operation Mode

The ISL6262 has several operating modes to optimize efficiency. The controller's operational modes are designed to work in conjunction with the Intel IMVP-6 control signals to maintain the optimal system configuration for all IMVP-6 conditions. These operating modes are established by the IMVP-6 control signal inputs such as PSI#, DPRSLPVR, and DPRSTP# as shown in Table 2. At high current levels, the system will operate with both phases fully active, responding rapidly to transients and deliver the maximum power to the load. At reduced load current levels, one of the phases may

be idled. This configuration will minimize switching losses, while still maintaining transient response capability. At the lowest current levels, the controller automatically configures the system to operate in single-phase automatic-DCM mode, thus achieving the highest possible efficiency. In this mode of operation, the lower FET will be configured to automatically detect and prevent discharge current flowing from the output capacitor through the inductors, and the switching frequency will be proportionately reduced, thus greatly reducing both conduction and switching losses.

Smooth mode transitions are facilitated by the R

Technology™, which correctly maintains the internally synthesized ripple currents throughout mode transitions. The controller is thus able to deliver the appropriate current to the load throughout mode transitions. The controller contains embedded mode-transition algorithms which robustly maintain voltage-regulation for all control signal input sequences and durations.

Mode-transition sequences will often occur in concert with VID changes; therefore the timing of the mode transitions of ISL6262 has been carefully designed to work in concert with VID changes. For example, transitions into single-phase mode will be delayed until the VID induced voltage ramp is complete, to allow the associated output capacitor charging current is shared by both inductor paths. While in singlephase automatic-DCM mode, VID changes will initiate an immediate return to two-phase CCM mode. This ensures that both inductor paths share the output capacitor charging current and are fully active for the subsequent load current increases.

The controller contains internal counters which prevent spurious control signal glitches from resulting in unwanted mode transitions. Control signals of less than two switching periods do not result in phase-idling. Signals of less than 7 switching periods do not result in implementation of automatic-DCM mode.

Intel IMVP-6

COMPLIANT LOGIC

OTHER LOGIC

COMMANDS

TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL6262

DPRSLPVR DPRSTP# PSI# PHASE OPERATION MODES EXPECTED CPU MODE

0 1 1 2-phase CCM active mode 0 1 0 1-phase CCM active mode 1 0 1 1-phase diode emulation deeper sleep mode 1 0 0 1-phase diode emulation deeper sleep mode 0 0 1 2-phase CCM 0 0 0 1-phase CCM 1 1 1 2-phase CCM 1 1 0 1-phase CCM

FN9199.2

May 15, 2006

ISL6262

While transitioning to single-phase operation, the controller smoothly transitions current from the idling-phase to the active-phase, and detects the idling-phase zero-current condition. During transitions into automatic-DCM or forcedCCM mode, the timing is carefully adjusted to eliminate output voltage excursions. When a phase is added, the current balance between phases is quickly restored.

While PSI# is high, both phases are switching. If PSI# is asserted low and either DPRSTP# or DPRSLPVR are not asserted, the controller will transition to CCM operation with only phase 1 switching, and both FET's of phase 2 will be off. The controller will thus eliminate switching losses associated with the unneeded channel.

& V

OUT

SOFT

-2.5mV/µs

2.5mV/µs

DPRSLPVR

VID #

FIGURE 29. DEEPER SLEEP TRANSITION SHOWING

DPRSLPVR'S EFFECT ON EXIT SLEW RATE

10mV/µs

When PSI#, DPRSTP#, and DPRSLPVR are all asserted, the controller will transition to single-phase DCM mode. In this mode, both FET's associated with phase 2 will be off,

and the ISL6262 will turn-off the lower FET of channel 1 whenever the channel 1 current decays to zero. As load is further reduced, the phase 1 channel switching frequency will decrease, thus maintaining high efficiency.

Dynamic Operation

Refer to Figure 29, the ISL6262 responds to changes in VID command voltage by slewing to new voltages with a dV/dt set by the SOFT capacitor and by the state of DPRSLPVR. With C

= 15nF and DPRSLPVR HIGH, the output

SOFT

voltage will move at ±2.8mV/s for large changes in voltage. For DPRSLPVR LOW, the large signal dV/dt will be ±13mV/s. As the output voltage approaches the VID command value, the dV/dt moderates to prevent overshoot.

Keeping DPRSLPVR HIGH for voltage transitions into and out of Deeper Sleep will result in low dV/dt output voltage changes with resulting minimized audio noise. For fastest recovery from Deeper Sleep to Active mode, holding DPRSLPVR LOW will result in maximum dV/dt. Therefore, the ISL6262 is IMVP-6 compliant for DPRSTP# and DPRSLPVR logic.

Intersil's R

Technology™ has intrinsic voltage feedforward. As a result, high-speed input voltage steps do not result in significant output voltage perturbations. In response to load current step increases, the ISL6262 will transiently raise the switching frequency so that response time is decreased and current is shared by two channels.

Protection

The ISL6262 provides overcurrent, overvoltage, undervoltage protection and over-temperature protection as shown in Table 3.

TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6262

FAULT DURATION PRIOR

TO PROTECTION PROTECTION ACTIONS FAULT RESET

Overcurrent fault 120µs PWM1, PWM2 three-state,

PGOOD latched low

Way-Overcurrent fault <2µs PWM1, PWM2 three-state,

Overvoltage fault (1.7V) Immediately Low-side FET on until Vcore

Overvoltage fault (+200mV) 1ms PWM1, PWM2 three-state,

Undervoltage fault (-300mV)

Unbalance fault (7.5mV)

Over-temperature fault (NTC <1.18V)

1ms PWM1, PWM2 three-state,

Immediately VR_TT# goes low N/A

PGOOD latched low

<0.85V, then PWM three-state, PGOOD latched low (OV-1.7V always)

PGOOD latched low

VR_ON toggle or VDD toggle

VDD toggle

VR_ON toggle or VDD toggle

May 15, 2006

FN9199.2

ISL6262

Overcurrent protection is tied to the voltage droop which is determined by the resistors selected as described in the “Component Selection and Application” section. After the load-line is set, the OCSET resistor can be selected to detect overcurrent at any level of droop voltage. An overcurrent fault will occur when the load current exceeds the overcurrent setpoint voltage while the regulator is in a 2-phase mode. While the regulator is in a 1-phase mode of operation, the overcurrent setpoint is automatically reduced by half. For overcurrents less than twice the OCSET level, the over-load condition must exist for 120µs in order to trip the OC fault latch. This is shown in Figure 24.

For over-loads exceeding twice the set level, the PWM outputs will immediately shut off and PGOOD will go low to maximize protection due to hard shorts.

In addition, excessive phase unbalance, for example, due to gate driver failure, will be detected in two-phase operation and the controller will be shut-down after one millisecond's detection of the excessive phase current unbalance. The phase unbalance is detected by the voltage on the ISEN pins if the difference is greater than 7.5mV.

Undervoltage protection is independent of the overcurrent limit. If the output voltage is less than the VID set value by 300mV or more, a fault will latch after one millisecond in that condition. The PWM outputs will turn off and PGOOD will go low. Note that most practical core regulators will have the overcurrent set to trip before the -300mV undervoltage limit.

There are two levels of overvoltage protection and response. For output voltage exceeding the set value by +200mV for one millisecond, a fault is declared. All of the above faults have the same action taken: PGOOD is latched low and the upper and lower power FETs are turned off so that inductor current will decay through the FET body diodes. This condition can be reset by bringing VR_ON low or by bringing VDD below 4V. When these inputs are returned to their high operating levels, a soft-start will occur.

threshold, the VR_TT# pin is pulled low indicating the need for thermal throttling to the system oversight processor. No other action is taken within the ISL6262 in response to NTC pin voltage.

Component Selection and Application

Soft-Start and Mode Change Slew Rates

The ISL6262 uses 2 slew rates for various modes of operation. The first is a slow slew rate, used to reduce inrush current during start-up. It is also used to reduce audible noise when entering or exiting Deeper Sleep Mode. A faster slew rate is used to exit out of Deeper Sleep and to enhance system performance by achieving active mode regulation more quickly. Note that the SOFT cap current is bidirectional. The current is flowing into the SOFT capacitor when the output voltage is commanded to rise, and out of the SOFT capacitor when the output voltage is commanded to fall.

Refer to Figure 30. The two slew rates are determined by commanding one of two current sources onto the SOFT pin. As can be seen in Figure 30, the SOFT pin has a capacitance to grou nd. Also, th e SOFT pin is the in put to the error amplifier and is, therefore, the commanded system voltage. Depending on the state of the system, i.e. Start-Up or Active mode, and the state of the DPRSLPVR pin, one of the two currents shown in Figure 30 will be used to charge or discharge this capacitor, thereby controlling the slew rate of the commanded voltage. These currents can be found under the SOFT-START CURRENT section of the Electrical Specification Table.

ISL6262

ERROR

AMPLIFIER

Refer to Figure 25, the second level of overvoltage protection behaves differently. If the output exceeds 1.7V, an OV fault is immediately declared, PGOOD is latched low and the low-side FETs are turned on. The low-side FETs will remain on until the output voltage is pulled down below about 0.85V at which time all FETs are turned off. If the output again rises above 1.7V, the protection process is repeated. This offers the maximum amount of protection against a shorted high-side FET while preventing output ringing below ground. The 1.7V OV is not reset with VR_ON, but requires that VDD be lowered to reset. The 1.7V OV detector is active at all times that the controller is enabled including after one of the other faults occurs so that the processor is protected against high-side FET leakage while the FETs are commanded off.

The ISL6262 has a thermal throttling feature. If the voltage on the NTC pin goes below the 1.18V over-temperature

SOFT

FIGURE 30. SOFT PIN CURRENT SOURCES FOR FAST AND

SLOW SLEW RATES

The first current, labelled I

REF

, is given in the Specification

Table as 41µA. This current is used during soft-start. The second current, I currents, labeled I

sums with ISS to get the larger of the two

in the Electrical Specification Table.

This total current is typically 200µA with a minimum of 175µA.

The IMVP-6 specification reveals the critical timing associated with regulating the output voltage. The symbol,

FN9199.2

May 15, 2006

ISL6262

SLEWRATE, as given in the IMVP-6 specification will determine the choice of the SOFT capacitor, C

SOFT

, by the

following equation:

SOFT

------------------------------------

SLEWRATE

(EQ. 1)

Using a SLEWRATE of 10mV/µs, and the typical IGV value, given in the Electrical Specification Table of 200µA, C

SOFT

200μ A10mV1μs⁄()⁄=

(EQ. 2)

A choice of 0.015µF would guarantee a SLEWRATE of 10mV/µs is met for minimum I Electrical Specification Table. This choice of C

value, given in the

SOFT

will then control the Start-Up slewrate as well. One should expect the output voltage to slew to the Boot value of 1.2V at a rate given by the following equation:

-------

-------------------

SOFT

41μ A

---------------------- -

0.015μ F

2.8mV μs⁄== =

(EQ. 3)

Selecting RBIAS

To properly bias the ISL6262, a reference current is established by placing a 147kΩ, 1% tolerance resistor from the RBIAS pin to ground. This will provide a highly accurate, 10µA current source from which OCSET reference current can be derived.

Care should be taken in layout that the resistor is placed very close to the RBIAS pin and that a good quality signal ground is connected to the opposite side of the RBIAS resistor. Do not connect any other components to this pin as this would negatively impact performance. Capacitance on this pin would create instabilities and should be avoided.

IMVP-6_PWRGD signal. This timer allows IMVP-6_PWRGD to go high approximately 6.8ms after CLK_EN# goes low.

Static Mode of Operation - Processor Die Sensing

Die sensing is the ability of the controller to regulate the core output voltage at a remotely sensed point. This allows the voltage regulator to compensate for various resistive drops in the power path and ensure that the voltage seen at the CPU die is the correct level independent of load current.

The VSEN and RTN pins of the ISL6262 are connected to Kelvin sense leads at the die of the processor through the processor socket. These signal names are Vcc_sense and Vss_sense respectively. This allows the voltage regulator to tightly control the processor voltage at the die, independent of layout inconsistencies and voltage drops. This Kelvin sense technique provides for extremely tight load line regulation.

These traces should be laid out as noise sensitive traces. For optimum load line regulation performance, the traces connecting these two pins to the Kelvin sense leads of the processor must be laid out away from rapidly rising voltage nodes, (switching nodes) and other noisy traces. To achieve optimum performance, place common mode and differential mode RC filters to analog ground on VSEN and RTN as shown in Figure 31. The filter resistors should be 10Ω so that they do not interact with the 50kΩ input resistance of the differential amplifier. The filter resistor may be inserted between Vcc_sense and VSEN pin. Another option is to place to the filter resistor between Vcc_sense and VSEN pin and between Vss_sense and RTN pin. Whether to need these RC filter really depends on the actual board layout and noise environment.

Start-Up Operation - CLK_EN# and PGOOD

The ISL6262 provides a 3.3V logic output pin for CLK_EN#. The 3V3 pin allows for a system 3.3V source to be connected to separated circuitry inside the ISL6262, solely devoted to the CLK_EN# function. The output is a 3.3V CMOS signal with 4mA sourcing and sinking capability. This implementation removes the need for an external pull-up resistor on this pin, and due to the normal level of this signal being a low, removes the leakage path from the 3.3V supply to ground through the pull-up resistor. This reduces 3.3V supply current, that would occur under normal operation with a pull-up resistor, and prolongs battery life. The 3.3V supply should be decoupled to digital ground, not to analog ground for noise immunity.

As mentioned in the “Theory of Operation” section of this datasheet, CLK_EN# is logic level high at start-up until 20µs after the system Vccp and Vcc_mch supplies are within regulation, and the Vcc-core is in regulation at the Boot level. Approximately 20µs after these voltages are within regulation, as indicated by PGD_IN going high, CLK_EN# goes low, triggering an internal timer for the

Due to the fact that the voltage feedback to the switching regulator is sensed at the processor die, there exists the potential of an overvoltage due to an open circuited feedback signal, should the regulator be operated without the processor installed. Due to this fact, we recommend the use of the Ropn1 and Ropn2 connected to Vout and ground as shown in Figure 31. These resistors will provide voltage feedback in the event that the system is powered up without a processor installed. These resistors may typically range from 20 to 100Ω.

FN9199.2

May 15, 2006

ISEN1 ISEN2

ISL6262

0.018µF

ISEN2

10µA

RTN

OPN2

DROOP

VSEN

82nF

0.018µF

OCSET

VSUM

DROOP

DFB

drp2

VO'

opn1

VCC_SENSE

VSS_SENSE

OCSET

drp1

TO V

VO'

SERIES

NTC

OUT

TO PROCESSOR SOCKET KELVIN CONNECTIONS

ISEN1

INTERNAL TO

ISL6262

VDIFF

FIGURE 31. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING

Setting the Switching Frequency - FSET

The R3 modulator scheme is not a fixed frequency PWM architecture. The switching frequency can increase during the application of a load to improve transient performance.

It also varies slightly due changes in input and output voltage and output current, but this variation is normally less than 10% in continuous conduction mode.

Refer to Figure 26, the resistor connected between the VW and COMP pins of the ISL6262 adjusts the switching window, and therefore adjusts the switching frequency. The R

resistor that sets up the switching frequency of the

FSET

converter operating in CCM can be determined using the following relationship, where R

is in kΩ and the

FSET

switching period is in µs. Place a 47pF capacitor in parallel with the frequency set resistor for better noise immunity.

FSET

kΩ()period μs()0.5–()1.56•≅

(EQ. 4)

In discontinuous conduction mode (DCM), the ISL6262 runs in period stretching mode. The switching frequency is dependent on the load current level. In general, the lighter load, the slower switching frequency. Therefore, the switching loss is much reduced for the light load operation, which is important for conserving the battery power in the portable application.

Voltage Regulator Thermal Throttling

lntel® IMVP-6 technology supports thermal throttling of the processor to prevent catastrophic thermal damage to the voltage regulator. The ISL6262 features a thermal monitor

VSUM

PAR

VO'

VSUM

PHASE1

PHASE2

ISEN1

ISEN2

VO'

+ -

Vdcr

VO'

Vdcr

+ -

DCR

RO1

which senses the voltage change across an externally placed negative temperature coefficient (NTC) thermistor.

Proper selection and placement of the NTC thermistor allows for detection of a designated temperature rise by the system.

Figure 32 shows the thermal throttling feature with hysteresis. At low temperature, SW1 is on and SW2 connects to the 1.18V side. The total current going into NTC pin is 60µA. The voltage on NTC pin is higher than threshold voltage of 1.18V and the comparator output is low. VR_TT# is pulling up high by the external resistor.

54µA

NTC

1.20V

FIGURE 32. CIRCUITRY ASSOCIATED WITH THE THERMAL

THROTTLING FEATURE IN ISL6262

6µA

SW1

SW2

1.18V INTERNAL TO

ISL6262

OUT

BULK

ESR

VR_TT#

FN9199.2

May 15, 2006

ISL6262

When temperature increases, the NTC resistor value on NTC pin decreases. Thus, the voltage on NTC pin decreases to a level lower than 1.18V. The comparator output changes polarity and turns SW1 off and connects SW2 to 1.20V. This pulls VR_TT# low and sends the signal to start thermal throttle. There is a 6µA current reduction on NTC pin and 20mV voltage increase on threshold voltage of the comparator in this state. The VR_TT# signal will be used to change the CPU operation and decrease the power consumption. When the temperature goes down, the NTC thermistor voltage will eventually go up. The NTC pin voltage increases to 1.20V, the comparator output will then be able to flip back. Such a temperature hysteresis feature of VR_TT# is illustrated in Figure 33. T

represents the higher

temperature point at which the VR_TT# goes from low to high due to the system temperature rise. T

represents the

lower temperature point at which the VR_TT# goes high from low because the system temperature decreases to the normal level.

VR_TT#

Logic_1

Using Equation 5 into Equation 8, the required nominal NTC resistor value can be obtained by:

⎛⎞

-----------------------

• ⎝⎠

To273+

•

e–

⎛⎞

-----------------------

•

⎝⎠

T1273+

(EQ. 9)

NTCTo

2.55kΩ e

----------------------------------------------------------------------------- -

⎛⎞

-----------------------

•

⎝⎠

T2273+

For some cases, the constant b is not accurate enough to approximate the NTC resistor value, the manufacturer provides the resistor ratio information at different temperature. The nominal NTC resistor value may be expressed in another way as follows:

NTC T2–

2.55kΩ

–

(EQ. 10)

NTC T1–

NTCTo

NTC T–

where is the normalized NTC resistance to its

---------------------------------------------------------------------- -

nominal value. Most datasheet of the NTC thermistor gives the normalized resistor value based on its value at 25°C.

Once the NTC thermistor resistor is determined, the series resistor can be derived by:

1.18V

--------------- -

60μ A

T1()19.67kΩ R

NTC

–=–=

NTC_T

(EQ. 11)

Logic_0

FIGURE 33. TEMPERATURE HYSTERESIS OF VR_TT#

T (°C)

Usually, the NTC thermistor's resistance can be approximated by the following formula:

NTC

T() R

NTCTo

⎛⎞

------------------- -

• ⎝⎠

T 273+

e•=

-----------------------

–

To 273+

(EQ. 5)

T is the temperature of the NTC thermistor and b is a parameter constant depending on the thermistor material. T

is the reference temperature in which the approximation

is derived. Most common temperature for T

is 25°C. For

example, there are commercial NTC thermistor products with b = 2750k, b = 2600k, b = 4500k or b = 4250k.

From the operation principle of the VR_TT# circuit explained, the NTC resistor satisfies the following equation group.

NTCT1

NTCT2

()RS+

--------------- -

60μ A

1.2V

-------------- -

54μ A

19.67kΩ==

22.22kΩ==

(EQ. 6)

(EQ. 7)

1.18V

From Equation 6 and Equation 7, the following can be derived,

NTCT2

()R

()– 2.55kΩ=

NTCT1

(EQ. 8)

Once R at T

and the actual T2 temperature can be found in:

NTC_T

2_actual

and Rs is designed, the actual NTC resistance

NTCTo

2.55kΩ R

NTC_T

-------------------------

NTCTo

NTC_T

273–=

1 273 To+()⁄+ln

-----------------------------------------------------------------------------------

⎛⎞

-- -

⎜⎟

⎝⎠

(EQ. 12)

(EQ. 13)

One example of using Equations 9, 10 and 11 to design a thermal throttling circuit with the temperature hysteresis 100°C to 105°C is illustrated as follows. Since T and T

= 100°C, if we use a Panasonic NTC with B = 4700,

= 105°C

the Equation 9 gives the required NTC nominal resistance as

NTC_To

396kΩ=

In fact, the datasheet gives the resistor ratio value at 100°C to 105°C, which is 0.03956 and 0.03322 respectively. The b value 4700K in Panasonic datasheet only covers to 85°C. Therefore, using Equation 10 is more accurate for 100°C design, the required NTC nominal resistance at 25°C is 402kΩ. The closest NTC resistor value from manufacturer is 470kΩ. So the series resistance is given by Equation 11 as follows,

19.67kΩ R

NTC_105°C

Furthermore, the NTC resistance at T

2.55kΩ R

NTC_T2

+ 18.16kΩ==

NTC_T1

19.67kΩ 15.65kΩ 4.067kΩ=–=–=

is given by Equation 12.

From the NTC datasheet, it can be concluded that the actual temperature T

is about 97°C. If using the Equation 13, T2 is

calculated to be 97.7°C. Check the NTC datasheet to decide

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ISL6262

whether Equation 9 or Equation 10 can accurately represent the NTC resistor value at the designed temperature range.

Therefore, the NTC branch is designed to have a 470k NTC and 4.02k resistor in series. The part number of the NTC thermistor is ERTJ0EV474J. It is a 0402 package. The NTC thermistor should be placed in the spot which gives the best indication of the temperature of voltage regulator circuit. The actual hysteresis temperature is about 105°C and 97°C.

Static Mode of Operation - S tatic Droop Using DCR Sensing

As previously mentioned, the ISL6262 has an internal differential amplifier which provides for very accurate voltage regulation at the die of the processor. The load line regulation is also accurate for both two-phase and singlephase operation. The process of selecting the components for the appropriate load line droop is explained here.

For DCR sensing, the process of compensation for DCR resistance variation to achieve the desired load line droop has several steps and is somewhat iterative.

The two-phase solution using DCR sensing is shown in Figure 31. There are two resistors connecting to the terminals of inductor of each phase. These are labeled RS and RO. These resistors are used to obtain the DC voltage drop across each inductor. Each inductor will have a certain level of DC current flowing through it, and this current when multiplied by the DCR of the inductor creates a small DC voltage drop across the inductor terminal. When this voltage is summed with the other channels DC voltages, the total DC load current can be derived.

through an understanding of both the DC and transient load currents. This value will be covered in the next section. However, it is important to keep in mind that the output of each of these RS resistors are tied together to create the VSUM voltage node. With both the outputs of RO and RS tied together, the simplified model for the droop circuit can be derived. This is presented in Figure 34.

Figure 34 shows the simplified model of the droop circuitry. Essentially one resistor can replace the RO resistors of each phase and one RS resistor can replace the RS resistors of each phase. The total DCR drop due to load current can be replaced by a DC source, the value of which is given by:

DCR_EQU

OUT

---------------------------------

(EQ. 14)

DCR•

For the convenience of analysis, the NTC network comprised of Rntc, Rseries and Rpar, given in Figure 31, is labelled as a single resistor Rn in Figure 34.

The first step in droop load line compensation is to adjust Rn, RO

EQV

and RS

such that sufficient droop voltage

EQV

exists even at light loads between the VSUM and VO' nodes. As a rule of thumb we start with the voltage drop across the Rn network, VN, to be 0.5-0.8 times V

DCR_EQU

. This ratio provides for a fairly reasonable amount of light load signal from which to arrive at droop.

The resultant NTC network resistor value is dependent on the temperature and given by

+()R

seriesRntc

--------------------------------------------------------------

T()

seriesRntcRpar

•

par

(EQ. 15)

RO is typically 1 to 10Ω. This resistor is used to tie the outputs of all channels together and thus create a summed average of the local CORE voltage output. RS is determined

10µA

INTERNAL TO

ISL6262

VDIFF VSEN

RTN

FIGURE 34. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING

DROOP

OCSET

VSUM

DFB

DROOP

Rdrp2

VO'

Rdrp1

For simplicity, the gain of Vn to the V

dcr_equ

G1, also dependent on the temperature of the NTC thermistor.

--------

EQV

Vdcr

EQV

EQVIOUT

---------

VSUM

VO'

Rntc Rseries+()Rpar×

--------------------------------------------------------------------

Rntc Rseries+()Rpar+

is defined by

DCR

-------------

×=

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May 15, 2006

ISL6262

T()

-------------------------------------------

DCR T() DCR

T() RS

25° C

T()

EQV

1 0.00393*(T-25)+()•=

(EQ. 16)

(EQ. 17)

Therefore, the output of the droop amplifier divided by the total load current can be expressed as follows.

DCR

droopG1

where R

droop

-------------------

T()

1 0.00393*(T-25)+()k

•••=

droopamp

(EQ. 18)

is the realized load line slope and 0.00393 is the temperature coefficient of the copper. To achieve the droop value independent from the temperature of the inductor, it is equivalently expressed by the following.

T() 1 0.00393*(T-25)+()G

≅•

1t etarg

(EQ. 19)

The non-inverting droop amplifier circuit has the gain K

droopamp

1target

expressed as:

drp2

--------------- -

drp1

is the desired gain of Vn over I

OUT

• DCR/2. Therefore, the temperature characteristics of gain of Vn is described by:

1t etarg

-------------------------------------------------------

T()

For the G

1 0.00393*(T-25)+()

= 0.76, the Rntc = 10kΩ with b = 4300,

1target

Rseries = 2610kΩ, and Rpar = 11kΩ, RS

EQV

= 1825Ω

(EQ. 20)

generates a desired G1, close to the feature specified in Equation 20. The actual G1 at 25°C is 0.763. For different G1 and NTC thermistor preference, the design file to generate the proper value of Rntc, Rseries, Rpar, and RS

is provided by Intersil.

EQV

Then, the individual resistors from each phase to the VSUM node, labeled RS1 and RS2 in Figure 31, are then given by the following equation.

Rs 2 RS

•=

EQV

(EQ. 21)

So, Rs = 3650Ω. Once we know the attenuation of the RS and RN network, we can then determine the droop amplifier gain required to achieve the load line. Setting Rdrp1 = 1k_1%, then Rdrp2 is can be found using equation

•

Rdrp2

⎛⎞

-----------------------------------------------

⎝⎠

DCR G1 25°C()•

droop

•=

1–

drp1

(EQ. 22)

Droop Impedance (Rdroop) = 0.0021 (V/A) as per the Intel IMVP-6 specification, DCR = 0.0008Ω typical for a 0.36µH inductor, Rdrp1 = 1kΩ and the attenuation gain (G1) = 0.77, Rdrp2 is then given by

•

droop

⎛⎞

Rdrp2

---------------------------------------

⎝⎠

0.0008 0.763•

1–

1kΩ 5.82kΩ≈•=

Note, we choose to ignore the RO resistors because they do not add significant error.

These designed values in Rn network are very sensitive to layout and coupling factor of the NTC to the inductor. As only one NTC is required in this application, this NTC should be placed as close to the Channel 1 inductor as possible and PCB traces sensing the inductor voltage should be go directly to the inductor pads.

Once the board has been laid out, some adjustments may be required to adjust the full load droop voltage. This is fairly easy and can be accomplished by allowing the system to achieve thermal equilibrium at full load, and then adjusting Rdrp2 to obtain the appropriate load line slope.

To see whether the NTC has compensated the temperature change of the DCR, the user can apply full load current and wait for the thermal steady state and see how much the output voltage will deviate from the initial voltage reading. A good compensation can limit the drift to 2mV. If the output voltage is decreasing with temperature increase, that ratio between the NTC thermistor value and the rest of the resistor divider network has to be increased. The user should follow the evaluation board value and layout of NTC as much as possible to minimize engineering time.

The 2.1mV/A load line should be adjusted by Rdrp2 based on maximum current, not based on small current steps like 10A, as the droop gain might vary between each 10A steps. Basically, if the max current is 40A, the required droop voltage is 84mV. The user should have 40A load current on and look for 84mV droop. If the drop voltage is less than 84mV, for example, 80mV. The new value will be calculated by:

84mV

Rdrp2_new

----------------

80mV

Rdrp1 Rdrp2+()Rdrp1–=

For the best accuracy , th e effective resistance on the DFB and VSUM pins should be identical so that the bias current of the droop amplifier does not cause an offset voltage. In the example above, the resistance on the DFB pin is Rdrp1 in parallel with Rdrop2, that is, 1K in parallel with 5.82K or 853Ω. The resistance on the VSUM pin is Rn in parallel with RS

or 5.87K in parallel with 1.825K or 1392Ω. The

EQV

mismatch in the effective resistances is 1392 - 853 = 539Ω. Do not let the mismatch get larger than 600Ω. To reduce the mismatch, multiply both Rdrp1 and Rdrp2 by the appropriate factor. The appropriate factor in the example is 1392/853 = 1.632. In summary, the predicted load line with the designed droop network parameters based on the Intersil design tool is shown in Figure 35.

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ISL6262

2.25

2.2

2.15

2.1

LOAD LINE (mV/A)

2.05 0 20406080100

INDUCTOR TEMPERATURE (°C)

FIGURE 35. LOAD LINE PERFORMANCE WITH NTC

THERMAL COMPENSATION

Dynamic Mode of Operation - Dynamic Droop Using DCR Sensing

Droop is very important for load transient performance. If the system is not compensated correctly, the output voltage could sag excessively upon load application and potentially create a system failure. The output voltage could also take a long period of time to settle to its final value. This could be problematic if a load dump were to occur during this time. This situation would cause the output voltage to rise above the no load setpoint of the converter and could potentially damage the CPU.

The L/DCR time constant of the inductor must be matched to the Rn*Cn time constant as shown in the following equation:

-------------

DCR

Solving for Cn we now have the following equation:

Note, RO was neglected. As long as the inductor time constant matches the Cn, Rn and Rs time constants as given above, the transient performance will be optimum. As in the static droop case, this process may require a slight adjustment to correct for layout inconsistencies. For the example of L = 0.36µH with 0.8mΩ DCR, Cn is calculated below.

The value of this capacitor is selected to be 330nF. As the inductors tend to have 20% to 30% tolerances, this cap generally will be tuned on the board by examining the transient voltage. If the output voltage transient has an initial dip, lower than the voltage required by the load line, and slowly increases back to the steady state, the cap is too small and vice versa. It is better to have the ca p value a litt le

•

n n

-------------

DCR

•

EQV

0.36μ H

--------------------

0.0008

EQV EQV

•=

330nF≈=

----------------------------------

---------------------------------- -

nRSEQV

----------------------------------

------------------------------------------------------------------

parallel 5.87K, 1.825K()

(EQ. 23)

(EQ. 24)C

(EQ. 25)C

bigger to cover the tolerance of the inductor to prevent the output voltage from going lower than the spec. This cap needs to be a high grade cap like X7R with low tolerance. There is another consideration in order to achieve better time constant match mentioned above. The NPO/COG (class-I) capacitors have only 5% tolerance and a very good thermal characteristics. But those caps are only available in small capacitance values. In order to use such capacitors, the resistors and thermistors surrounding the droop voltage sensing and droop amplifier has to be resized up to 10X to reduce the capacitance by 10X. But attention has to be paid in balancing the impedance of droop amplifier in this case.

Dynamic Mode of Operation - Compensation Parameters

Considering the voltage regulator as a black box with a voltage source controlled by VID and a series impedance, in order to achieve the 2.1mV/A load line, the impedance needs to be 2.1mΩ. The compensation design has to target the output impedance of the converter to be 2.1mΩ. There is a mathematical calculation file available to the user. The power stage parameters such as L and Cs are needed as the input to calculate the compensation component values. Attention has to be paid to the input resistor to the FB pin. T oo high of a resistor will cause an error to the output voltage regulation because of bias current flowing in the FB pin. It is better to keep this resistor below 3K when using this file.

Static Mode of Operation - Current Balance Using DCR or Discrete Resistor Current Sensing

Current Balance is achieved in the ISL6262 through the matching of the voltages present on the ISEN pins. The ISL6262 adjusts the duty cycles of each phase to maintain equal potentials on the ISEN pins. RL and CL around each inductor, or around each discrete current resistor, are used to create a rather large time constant such that the ISEN voltages have minimal ripple voltage and represent the DC current flowing through each channel's inductor. For optimum performance, RL is chosen to be 10kΩ and CL is selected to be 0.22µF . When discrete resistor sensing is used, a capacitor most likely needs to be placed in parallel with RL to properly compensate the current balance circuit.

ISL6262 uses RC filter to sense the average voltage on phase node and forces the average voltage on the phase node to be equal for current balance. Even though the ISL6262 forces the ISEN voltages to be almost equal, the inductor currents will not be exactly equal. Take DCR current sensing as example, two errors have to be added to find the total current imbalance. 1) Mismatch of DCR: If the DCR has a 5% tolerance then the resistors could mismatch by 10% worst case. If each phase is carrying 20A then the phas e currents mismatch by 20A*10% = 2A. 2) Mismatch of phase voltages/offset voltage of ISEN pins. The phase voltages are within 2mV of each other by current balance circuit. The error current that results is given by 2mV/DCR. If DCR = 1mΩ then the error is 2A.

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ISL6262

In the above example, the two errors add to 4A. For the two phase DC/DC, the currents would be 22A in one phase and 18A in the other phase. In the above analysis, the current balance can be calculated with 2A/20A = 10%. This is the worst case calculation, for example, the actual tolerance of two 10% DCRs is 10%*sqrt(2) = 7%.

There are provisions to correct the current imbalance due to layout or to purposely divert current to certain phase for better thermal management. Customer can put a resistor in parallel with the current sensing capacitor on the phase of interest in order to purposely increase the current in that phase.

In the case the pc board trace resistance from the inductor to the microprocessor are not the same on two phases, the current will not be balanced. On the phase that have too much trace resistance a resistor can be added in parallel with the ISEN capacitor that will correct for the poor layout.

An estimate of the value of the resistor is: Rtweak = Risen * Rdcr/(Rtrace-Rmin) where Risen is the resistance from the phase node to the

ISEN pin; usually 10kΩ. Rdcr is the DCR resistance of the inductor. Rtrace is the trace resistance from the inductor to the microprocessor on the phase that needs to be tweaked. It should be measured with a good microOhm meter. Rmin is the trace resistance from the inductor to the microprocessor on the phase with the least resistance.

For example, if the pc board trace on one phase is 0.5mΩ and on another trace is 0.3mΩ; and if the DCR is 1.2mΩ; then the tweaking resistor is Rtweak = 10kΩ * 1.2/(0.5 - 0.3) = 60 kΩ.

When choosing current sense resistor, not only the tolerance of the resistance is important, but also the TCR. And its combined tolerance at a wide temperature range should be calculated.

Droop Using Discrete Resistor Sensing - Static/ Dynamic Mode of Operation

Figure 36 shows the equivalent circuit of a discrete current sense approach. Figure 27 shows a more detailed schematic of this approach. Droop is solved the same way as the DCR sensing approach with a few slight modifications.

Now, the input to the droop amplifier is essentially the Vrsense voltage. This voltage is given by the following equation:

sense

------------------- -

•=

EQV

OUT

The gain of the droop amplifier, K

droopamp

, must be adjusted

(EQ. 26)Vrsense

for the ratio of the Rsense to droop impedance, Rdroop. We use the following equation:

droopamp

------------------- -

sense

•=

OUT

(EQ. 27)

droop

Solving for the Rdrp2 value, Rdroop = 0.0021(V/A) as per the Intel IMVP-6 specification, Rsense = 0.001Ω and Rdrp1 = 1kΩ, we obtain the following:

Rdrp2 K

droopamp

1–()R

• 3.2kΩ==

drp1

(EQ. 28)

These values are extremely sensitive to layout. Once the board has been laid out, some tweaking may be required to adjust the full load droop. This is fairly easy and can be accomplished by allowing the system to achieve thermal equilibrium at full load, and then adjusting Rdrp2 to obtain the desired droop value.

Fault Protection - Overcurrent Fault Setting

As previously described, the overcurrent protection of the ISL6262 is related to the droop voltage. Previously we have calculated that the droop voltage = ILoad * Rdroop, where Rdroop is the load line slope specified as 0.0021 (V/A) in the Intel IMVP-6 specification. Knowing this relationship, the overcurrent protection threshold can be set up as a voltage droop level. Knowing this voltage droop level, one can program in the appropriate drop across the Roc resistor. This voltage drop will be referred to as Voc. Once the droop voltage is greater than Voc, the PWM drives will turn off and PGOOD will go low.

The selection of Roc is given in equation. Assuming we desire an overcurrent trip level, Ioc, of 55A, and knowing from the Intel Specification that the load line slope, Rdroop is

0.0021 (V/A), we can then calculate for Roc as shown in equation.

IOCR

•

droop

-----------------------------------

10μ A

55 0.0021•

------------------------------

10 10

•

11.5kΩ===

6–

(EQ. 29)R

First, there is no NTC required for thermal compensation, therefore, the Rn resistor network in the previous section is not required. Secondly, there is no time constant matching required, therefore, the Cn component is not matched to the L/DCR time constant. This component does indeed provide noise immunity and therefore is populated with a 39pF capacitor.

The RS values in the previous section, RS = 1.5k_1% are sufficient for this approach.

Note, if the droop load line slope is not -0.0021 (V/A) in the application, the overcurrent setpoint will differ from predicted.

FN9199.2

May 15, 2006

INTERNAL TO

ISL6262

Rdrp2

Voc Roc

VSUM

--------

Vrsense

EQV

EQVIOUT

Rsense

----------------------

×=

10µA

DROOP

OCSET

VSUM

DFB

DROOP

VDIFF VSEN

RTN

VO'

Rdrp1

VO'

EQV

---------

FIGURE 36. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DISCRETE RESISTOR SENSING

FN9199.2

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ISL6262

Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)

0.15

NX b

E/2

0.152XB

0.10 BAMC 8

NX k

E2/2

/ /

(Ne-1)Xe

INDEX

AREA

SEATING PLANE

(DATUM A)

(DATUM B)

6 INDEX AREA

NX L

1 2 3

3 2 1

TOP VIEW

D/2

SIDE VIEW

(Nd-1)Xe

REF.

BOTTOM VIEW

0.10 C

0.08

REF.

L48.7x7

48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VKKD-2 ISSUE C)

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 -

A1 - - 0.05 -

A3 0.20 REF -

b 0.18 0.23 0.30 5, 8

D 7.00 BSC -

D2 4.15 4.30 4.45 7, 8

E 7.00 BSC -

E2 4.15 4.30 4.45 7, 8

e 0.50 BSC -

k0.25 - - -

L 0.30 0.40 0.50 8

N482

Nd 12 3

Ne 12 3

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.

NOTESMIN NOMINAL MAX

Rev. 2 5/06

NX b

SECTION "C-C"

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9199.2

May 15, 2006

Datasheet ISL6262CRZ, ISL6262IRZ Datasheet (Intersil)

Specifications and Main Features

Frequently Asked Questions

User Manual