Datasheet ISL6208A Datasheet (intersil)

®

www.BDTIC.com/Intersil

ISL6208A

Data Sheet February 15, 2006 FN9272.0

High Voltage Synchronous Rectified Buck
MOSFET Driver

The ISL6208A is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology. It is
especially suited for mobile computing applications that
require high efficiency and excellent thermal performance.
This driver, combined with an Intersil multiphase Buck PWM
controller, forms a complete single-stage core-voltage
regulator solution for advanced mobile microprocessors.

The ISL6208A features 4A typical sinking current for the
lower gate driver. This current is capable of holding the lower
MOSFET gate off during the rising edge of the Phase node.
This prevents shoot-through power loss caused by the high
dv/dt of phase voltages. The operating voltage matches the
30V breakdown voltage of the MOSFETs commonly used in
mobile computer power supplies.

The ISL6208A also features a three-state PWM input that,
working together with Intersil’s multiphase PWM controllers,
will prevent negative voltage output during CPU shutdown.
This feature eliminates a protective Schottky diode usually
seen in a microprocessor power systems.

MOSFET gates can be efficiently switched up to 2MHz using
the ISL6208A. Each driver is capable of driving a 3000pF
load with propagation delays of 15ns and transition times
under 10ns. Bootstrapping is implemented with an internal
Schottky diode. This reduces system cost and complexity,
while allowing the use of higher performance MOSFETs.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously.

A diode emulation feature is integrated in the ISL6208A to
enhance converter efficiency at light load conditions. This
feature also allows for monotonic start-up into pre-biased
outputs. When diode emulation is enabled, the driver will
allow discontinuous conduction mode by detecting when the
inductor current reaches zero and subsequently turning off
the low side MOSFET gate. Programmable dead-time
control with gate threshold monitoring is also integrated to
prevent both MOSFETs from conducting simultaneously.

Related Literature

• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for MLFP Packages”

• Technical Brief TB447 “Guidelines for Preventing Boot-to­Phase Stress on Half-Bridge MOSFET Driver ICs”

Features

• Dual MOSFET Drives for Synchronous Rectified Bridge

• Adaptive Shoot-Through Protection

- Active Gate Threshold Monitoring

- Programmable Dead-Time

•0.5Ω On-Resistance and 4A Sink Current Capability

• Supports High Switching Frequency up to 2MHz

- Fast Output Rise and Fall Time

- Low Propagation Delay

• Three-State PWM Input for Power Stage Shutdown

• Internal Bootstrap Schottky Diode

• Low Bias Supply Current (5V, 100µA)

• Diode Emulation for Efficiency and Pre-Biased Startup

• VCC POR (Power-On-Reset) Feature Integrated

• Pin-to-pin Compatible with ISL6207, ISL6208, ISL6209

• QFN Package:

- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Supplies for Intel® and AMD® Mobile Microprocessors

• High Frequency, Low Profile DC/DC Converters

• High Current Low Output Voltage DC/DC Converters

• High Input Voltage DC/DC Converters

Ordering Information

TEMP.

PART

PART NUMBER

ISL6208ACBZ
(Note)

ISL6208ACBZ-T
(Note)

ISL6208ACRZ
(Note)

ISL6208ACRZ-T
(Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

MARKING

ISL6208ACBZ -10 to 100 8 Ld SOIC

ISL6208ACBZ 8 Ld SOIC Tape and Reel

08AZ -10 to 100 8 Ld 3x3 QFN

08AZ 8 Ld 3x3 QFN Tape and Reel

RANGE

(°C) PACKAGE

(Pb-Free)

(Pb-Free)

(Pb-Free)

(Pb-Free)

PKG.

DWG.

#

M8.15

L8.3x3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006. All Rights Reserved

Pinouts

www.BDTIC.com/Intersil

UGATE

BOOT

PWM

GND

Block Diagram

ISL6208ACB

(8 LD SOIC)

TOP VIEW

1

2

3

4

8

7

6

5

PHASE

FCCM

VCC

LGATE

ISL6208A

BOOT

PWM

ISL6208ACR

(8 LD 3x3 QFN)

TOP VIEW

UGATE

PHASE

7

8

1

2

43

GND

LGATE

6

6

5

FCCM

VCC

Timing Diagram

PWM

UGATE

t

PDHU

VCC

FCCM

PWM

t

RU

t

PDLU

10K

SHOOT-

THROUGH

CONTROL

LOGIC

PROTECTION

THERMAL PAD (FOR QFN PACKAGE ONLY)

FIGURE 1. BLOCK DIAGRAM

2.5V

t

FU

1V

t

PTS

VCC

t

RU

t

TSSHD

BOOT

UGATE

PHASE

LGATE

GND

t

FU

LGATE

1V

t

t

PDLL

t

FL

t

PDHL

RL

t

TSSHD

t

FL

2

t

PTS

February 15, 2006

FN9272.0

ISL6208A

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

Input Voltage (V
BOOT Voltage (V
BOOT To PHASE Voltage (V

PHASE Voltage (Note 1) . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V

UGATE Voltage . . . . . . . . . . . . . . . . V

LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -40°C to 125°C

, V

FCCM

BOOT-GND

V

PHASE

GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V

). . . . . . . . . . . . . -0.3V to VCC + 0.3V

PWM

). . . . . . . . . . . . . . . . . . . . . -0.3V to 33V

BOOT-PHASE

GND -8V (<20ns Pulse Width, 10µJ)

- 5V (<20ns Pulse Width, 10µJ) to V

) . . . . . . -0.3V to 7V (DC)

-0.3V to 9V (<10ns)

- 0.3V (DC) to V

PHASE

BOOT
BOOT

Thermal Resistance (Typical Notes 2, 3, 4) θ

SOIC Package (Note 2) . . . . . . . . . . . . 110 n/a

QFN Package (Notes 3, 4). . . . . . . . . . 80 15

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

Recommended Operating Conditions

Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-10°C to 100°C

Maximum Operating Junction Temperature. . . . . . . . . . . . . . 125°C

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. The Phase Voltage is capable of withstanding -7V DC when the BOOT pin is at GND.
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. θ

JA

3. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

4. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

(°C/W) θJC (°C/W)

JA

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Bias Supply Current I

POR Vcc Rising - 3.30 3.90 V

POR Hysteresis - 400 - mV

BOOTSTRAP DIODE

Forward Voltage V

PWM INPUT

Input Current I

PWM Three-State Rising Threshold V

PWM Three-State Falling Threshold V

Three-State Shutdown Holdoff Time t

UG/LG Three-state Propagation Delay t

FCCM INPUT

FCCM Threshold -2.5- V

FCCM Transient Delay R

SWITCHING TIME

UGATE Rise Time (Note 5) t

LGATE Rise Time (Note 5) t

UGATE Fall Time (Note 5) t

VCC

PWM

TSSHD

PTS

RU

RL

FU

PWM pin floating, V

Vcc Falling 2.40 2.90 - V

V

F

= 5V, forward bias current = 2mA 0.45 0.60 0.65 V

VCC

V

= 5V, V

PWM

V

PWM

VCC

VCC

V

VCC

= 0Ω -70-ns

SET

V

VCC

V

VCC

V

VCC

FCCM

= 0V, V

FCCM

= 5V 0.70 1.00 1.30 V

= 5V 3.5 3.8 4.1 V

= 5V, temperature = 25°C - 70 - ns

= 5V, 3nF Load - 8.0 - ns

= 5V, 3nF Load - 8.0 - ns

= 5V, 3nF Load - 8.0 - ns

= 5V - 100 - µA

FCCM

= 5V - 250 - µA

= 5V - -250 - µA

-20-ns

3

FN9272.0

February 15, 2006

ISL6208A

www.BDTIC.com/Intersil

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

LGATE Fall Time (Note 5) t

UGATE Turn-Off Propagation Delay t

LGATE Turn-Off Propagation Delay t

UGATE Turn-On Propagation Delay t

LGATE Turn-On Propagation Delay t

UGATE Turn-On Propagation Delay t

LGATE Turn-On Propagation Delay t

Minimum LG On TIME in DCM (Note 5) t

FL

PDLU

PDLL

PDHU

PDHL

PDHU

PDHL

LGMIN

OUTPUT

Upper Drive Source Resistance (Note 5) R

Upper Driver Source Current (Note 5) I

U

Upper Drive Sink Resistance (Note 5) R

Upper Driver Sink Current (Note 5) I

U

Lower Drive Source Resistance (Note 5) R

Lower Driver Source Current (Note 5) I

L

Lower Drive Sink Resistance (Note 5) R

Lower Driver Sink Current (Note 5) I

L

NOTE:

5. Guaranteed by Characterization. Not 100% Tested in Production.

V

= 5V, 3nF Load - 4.0 - ns

VCC

V

= 5V, Outputs Unloaded - 20 - ns

VCC

V

= 5V, Outputs Unloaded - 27 - ns

VCC

V

= 5V, Outputs Unloaded; R

VCC

V

= 5V, Outputs Unloaded; R

VCC

V

= 5V, Outputs Unloaded; R

VCC

V

= 5V, Outputs Unloaded; R

VCC

= 0Ω -26-ns

SET

= 0Ω -26-ns

SET

= 80kΩ -41-ns

SET

= 80kΩ -33-ns

SET

- 400 - ns

500mA Source Current - 1 2.5 Ω

U

V

UGATE-PHASE

500mA Sink Current - 1 2.5 Ω

U

V

UGATE-PHASE

500mA Source Current - 1 2.5 Ω

L

V

LGATE

500mA Sink Current - 0.4 1.0 Ω

L

V

LGATE

= 2.5V - 2.00 - A

= 2.5V - 2.00 - A

= 2.5V - 2.00 - A

= 2.5V - 4.00 - A

Typical Application with 2-Phase Converter

+5V

+5V

VCC

FCCM

PWM

+5V

FCCM

PWM

PGOOD

VID

+5V

FB

VSEN

CONTROL

FS

COMP

VCC

PWM1

PWM2

FCCM

MAIN

ISEN1

ISEN2

DACOUT

GND

DRIVE

ISL6208A

THERMAL
PAD

VCC

DRIVE

ISL6208A

THERMAL
PAD

BOOT

UGATE

PHASE

LGATE

BOOT

UGATE

PHASE

LGATE

V

BAT

+V

CORE

V

BAT

4

FN9272.0

February 15, 2006

ISL6208A

www.BDTIC.com/Intersil

Functional Pin Description

UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)

The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.

BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)

BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.

PWM (Pin 3 for SOIC-8, Pin 2 for QFN)

The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation (see
the three-state PWM Input section under DESCRIPTION for
further details). Connect this pin to the PWM output of the
controller.

GND (Pin 4 for SOIC-8, Pin 3 for QFN)

GND is the ground pin for the IC.

LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)

LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.

VCC (Pin 6 for SOIC-8, Pin 5 for QFN)

Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.

FCCM (Pin 7 for SOIC-8, Pin 6 for QFN)

The FCCM pin enables or disables Diode Emulation. When
FCCM is LOW, diode emulation is allowed. Otherwise,
continuous conduction mode is forced. See the Diode
Emulation section under DESCRIPTION for more detail.
This pin can also be used to program additional switching
dead-time by placing a resistor in series with the input. See
the Programmable Dead-Time section for more detail.

PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)

Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.

Description

Theory of Operation

Designed for speed, the ISL6208A dual MOSFET driver
controls both high-side and low-side N-Channel FETs from
one externally provided PWM signal.

A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t
[t

] are provided in the Electrical Specifications section.

FL

Adaptive shoot-through circuitry monitors the LGATE
voltage. When LGATE has fallen below 1V, UGATE is
allowed to turn ON. This prevents both the lower and upper
MOSFETs from conducting simultaneously, or shoot­through.

A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
gate begins to fall [t
voltage is monitored, and the lower gate is allowed to rise

after the upper MOSFET gate-to-source voltage drops below

1V. The lower gate then rises [t
MOSFET.

This driver is optimized for converters with large step down
compared to the upper MOSFET because the lower
MOSFET conducts for a much longer time in a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement.

The 0.5Ω on-resistance and 4A sink current capability
enable the lower gate driver to absorb the current injected to
the lower gate through the drain-to-gate capacitor of the
lower MOSFET and prevent a shoot through caused by the
high dv/dt of the phase node.

], the lower gate begins to fall. Typical fall times

PDLL

] is encountered before the upper

PDLU

]. The upper MOSFET gate-to-source

FU

], turning on the lower

RL

5

FN9272.0

February 15, 2006

ISL6208A

www.BDTIC.com/Intersil

Typical Performance Waveforms

FIGURE 2. LOAD TRANSIENT (0 - 30A, 3-PHASE) FIGURE 3. LOAD TRANSIENT (30 - 0A, 3-PHASE)

FIGURE 4. DCM TO CCM TRANSITION AT NO LOAD FIGURE 5. CCM TO DCM TRANSITION AT NO LOAD

FIGURE 6. PRE-BIASED STARTUP IN CCM MODE FIGURE 7. PRE-BIASED STARTUP IN DCM MODE

6

February 15, 2006

FN9272.0

ISL6208A

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Diode Emulation

Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6208A will detect the zero current crossing of the output
inductor and turn off LGATE. This ensures that
discontinuous conduction mode (DCM) is achieved. Diode
emulation is asynchronous to the PWM signal. Therefore,
the ISL6208A will respond to the FCCM input immediately
after it changes state. Refer to the waveforms on page 6.

NOTE: Intersil does not recommend DCM mode use with r
current sensing topologies. The turn-OFF of the low side MOSFET
can cause gross current measurement inaccuracies.

DS(ON)

Three-State PWM Input

A unique feature of the ISL6208A and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the output drivers are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.

Adaptive Shoot-Through Protection

Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to turn on.

GATE A

1V

1V

FCCM = VCC or GND

Adaptive Shoot-Through Protection

FCCM = RESISTOR to VCC or GND

GATE A

Adaptive Protection with Delay

t

= 5n - 50ns

delay

FIGURE 8. PROGRAMMABLE DEAD-TIME

GATE B

GATE B

During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the upper MOSFET gate-to-source voltage during
UGATE turn-off. Once the upper MOSFET gate-to-source
voltage has dropped below a threshold of 1V, the LGATE is
allowed to rise.

In addition to gate threshold monitoring, a programmable
delay between MOSFET switching can be accomplished by
placing a resistor in series with the FCCM input. This delay
allows for maximum design flexibility over MOSFET
selection. The delay can be programmed from 5ns to 50ns
above the adaptive shoot-through protection and is obtained
from the absolute value of the current flowing into the FCCM
pin. If no resistor is used, the minimum 5ns delay is used.
Gate threshold monitoring is not affected by the addition or
removal of the additional dead-time. Refer to Figure 8 and
Figure 9 for more detail.

50

45

40

35

30

25

DEAD-TIME (ns)

20

15

10

5

0

0 167 667333 500 833 1000

FIGURE 9. ISL6208A PROGRAMMABLE DEAD-TIME vs

DELAY RESISTOR

R

DELAY

t

DELAY

(kΩ)

The equation governing the dead-time seen in Figure 9 is
expressed as:

T

DELAY ns()

7

0.045 R

×[]5ns+=

DELAY kΩ()

FN9272.0

February 15, 2006

ISL6208A

www.BDTIC.com/Intersil

The equation can be rewritten to solve for R

DELAY

as

follows:

R

DELAY

kΩ()

T

DELAY ns()

------------------------------------------------------=

5ns–()

0.045

Internal Bootstrap Diode

This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage rating
above the maximum battery voltage plus 5V. The bootstrap
capacitor can be chosen from the following equation:

Q

GATE

C

BOOT

where Q
charge the gate of the upper MOSFET. The ∆V
defined as the allowable droop in the rail of the upper drive.

As an example, suppose an upper MOSFET has a gate
charge, Q
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125µF is required.
The next larger standard value capacitance is 0.15µF. A
good quality ceramic capacitor is recommended.

------------------------

≥

∆V

BOOT

is the amount of gate charge required to fully

GATE

, of 25nC at 5V and also assume the droop in

GATE

2.0

1.8

1.6

1.4

(µF)

1.2

1.0

0.8

BOOT_CAP

C

0.6

0.4

0.2
20nC

0.0

FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

Q

GATE

50

n

C

VOLTAGE

= 100nC

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
∆V

BOOT_CAP

(V)

BOOT

(EQ. 1)

term is

frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:

Pfsw1.5VUQUVLQ

where f

sw

and V

represent the upper and lower gate rail voltage. QU

L

and Q

is the upper and lower gate charge determined by

L

+()I

L

V

+=

VCC

CC

(EQ. 2)

is the switching frequency of the PWM signal. VU

MOSFET selection and any external capacitance added to
the gate pins. The lV

CC VCC

product is the quiescent power

of the driver and is typically negligible.

1000

POWER (mW)

QU=100nC

=200nC

Q

900

800

700

600

500

400

300

200

100

L

0

0 200 400 600 800 1000 1200 1400 1600 1800 2000

FIGURE 11. POWER DISSIPATION vs FREQUENCY

QU=50nC

=100nC

Q

L

FREQUENCY (kHz)

QU=50nC

Q

=50nC

L

QU=20nC

Q

=50nC

L

Power Dissipation

Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125°C. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired

8

FN9272.0

February 15, 2006

ISL6208A

www.BDTIC.com/Intersil

Quad Flat No-Lead Plastic Package (QFN)

L8.3x3

8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VEEC ISSUE C)

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 -

A1 - - 0.05 -

A2 - - 1.00 9

A3 0.20 REF 9

b 0.23 0.28 0.38 5, 8

D 3.00 BSC -

D1 2.75 BSC 9

D2 0.25 1.10 1.25 7, 8

E 3.00 BSC -

E1 2.75 BSC 9

E2 0.25 1.10 1.25 7, 8

e 0.65 BSC -

k0.25 - -

L 0.35 0.60 0.75 8

L1 - - 0.15 10

N82

Nd 2 3

Ne 2 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.

10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

NOTESMIN NOMINAL MAX

Rev. 1 10/02

9

FN9272.0

February 15, 2006

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

ISL6208A

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6

N8 87

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

10

FN9272.0

February 15, 2006