Datasheet ISL5740 Datasheet (Intersil)

TM

ISL5740

PRELIMINARY

Data Sheet June 2000 File Number 4821.2

3V Dual 10-Bit, 20/40/60MSPS A/D
Converter with Internal Voltage Reference

The ISL5740 is a monolithic, dual 10-bit analog-to-digital
converter fabricated in an advanced CMOS process. It is
designed for high speed applications where integration,
bandwidth and accuracy are essential. The ISL5740
features a 9-stage pipeline architecture. The fully pipelined
architecture and an innovative input stage enable the
ISL5740 to accept a variety of input configurations, single­ended or fully differential. Only one external clock is
necessary to drivebothconverters and an internal band-gap
voltage reference is provided. This allows the system
designer to realize an increased level of system integration
resulting in decreased cost and power dissipation.

The ISL5740 has excellent dynamic performance while
consuming less than 280mW power at 60MSPS. The A/D
only requires a single +3.0V power supply. Data output
latches are provided which present valid data to the output
bus with a latency of 5 clock cycles.

The ISL5740 is offered in 20MSPS, 40MSPS and 60MSPS
sampling rates.

Ordering Information

TEMP.

PART

NUMBER

RANGE

(oC) PACKAGE PKG. NO.

ISL5740/2IN -40 to 85 48 Ld LQFP Q48.7x7 20
ISL5740/3IN -40 to 85 48 Ld LQFP Q48.7x7 30
ISL5740/4IN -40 to 85 48 Ld LQFP Q48.7x7 40
ISL5740/6IN -40 to 85 48 Ld LQFP Q48.7x7 60
ISL5740 EVAL 25 Evaluation Platform

SAMPLIN

G RATE

(MSPS)

Features

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . .20/40/60MSPS

• 9.1 Bits at f

= 10MHz

IN

• Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . .280mW

• Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6mW

• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 400MHz

• SFDR at f

= 10MHz. . . . . . . . . . . . . . . . . . . . . . . . .70dB

IN

• Excellent Channel-to-Channel Isolation. . . . . . . . . . .75dB

• On-Chip Sample and Hold Amplifiers

• Internal Bandgap Voltage Reference . . . . . . . . . . . . 1.25V

• Single Supply Voltage Operation . . . . . . . . . .+2.7V - 3.6V

• TTL/CMOS(3V) Digital Inputs CMOS Digital Outputs

• Offset Binary or Two’s Complement Digital Data Output
Format

• Dual 10-Bit A/D Converters on a Monolithic Chip

• Pin Compatible Upgrade to AD9288

Pinout

• Wireless Local Loop

• PSK and QAM I&Q Demodulators

• Medical Imaging and Instrumentation

• Wireless Communications Systems

• Battery Powered Instruments

Pinout

CC

CC

AV

I CLK

DV

GND

ID9

ID8

ID7

ID6

ID5

ID4

ID3

ID2

GND

I

+

IN

-

I

IN

DFS

IV

RIN

V

ROUT

QV

RIN

S1
S2

QIN­QIN+
GND

3-1

1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1
2

3
4
5
6

7
8
9
10
11

12

13 14 15 16

CC

AV

Q CLK

DV

CC

GND

QD9

QD8

QD7

QD6

QD5

QD4

373839404142434445464748

2423222120191817

QD3

36
35
34
33
32
31
30
29
28
27
26
25

QD2

ID1
ID0
GND
DV

GND
AV

AV
GND

DV
GND
QD0
QD1

CC

CC
CC

CC

Functional Block Diagram

-

I/Q

IN

I/Q

+

IN

S/H

STAGE 1

ISL5740

CLOCK

I/QCLK

2-BIT

FLASH

+

-

∑

X2

STAGE 8

2-BIT

FLASH

+

∑

-

2-BIT

DAC

2-BIT

DAC

DIGITAL DELAY

AND

DIGITAL ERROR

CORRECTION

I/QD9 (MSB)

I/QD8

I/QD7

I/QD6

I/QD5

I/QD4

I/QD3

I/QD2

I/QD1

I/QD0 (LSB)

V

I/QV

ROUT

RIN

X2

REFERENCE

3-2

2-BIT

FLASH

STAGE 9

AV

CC

AGND DV

CC

DGND

I OR Q CHANNEL

MODE

DATA FORMAT

S1/S2
DFS

Typical Application Schematic

ISL5740

ISL5740

I

+

IN

- (3) IIN-

I

IN

QIN+

QIN-

0.1µF

(2) I

+

IN

(11) QIN+

(10) QIN-

(5) IV

RIN

(6) QV

RIN

(7) V

ROUT

ID1 (36)
ID2 (37)
ID3 (38)
ID4 (39)
ID5 (40)
ID6 (41)
ID7 (42)
ID8 (43)

(MSB) ID9 (44)

(LSB) QD0 (26)

QD1 (25)
QD2 (24)
QD3 (23)
QD4 (22)
QD5 (21)
QD6 (20)
QD7 (19)
QD8 (18)

(MSB) QD9 (17)

ICLK (47)

QCLK (14)

ID0(LSB) ID0 (35)
ID1
ID2

ID3
ID4
ID5
ID6
ID7
ID8
ID9

QD0
QD1
QD2

QD3
QD4
QD5
QD6
QD7
QD8
QD9

CLOCK

+3V

10µF

S1 (8)
S2 (9)

DFS (4)

AGND

(13,30,31,48) AV

(12,29,32) AGND

DGND

+

0.1µF

BNC

CC

DVCC(15, 28, 33, 46)

DGND (16, 27, 34, 45)

10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE

S1
S2
DFS

0.1µF10µF

+

3V

3-3

ISL5740

Pin Descriptions

PIN NO. NAME DESCRIPTION

1A
2I
3I

GND

IN+
IN-

4 DFS Data Format Select (Low for Offset

5IV
6V

ROUT

7QV
8 S1 Mode Select Pin 1 (See Table)

9 S2 Mode Select Pin 2 (See Table)
10 Q
11 Q
12 A

GND

13 AV
14 QCLK Q-Channel Clock Input
15 DV
16 D

GND

17 QD9 Q-Channel, Data Bit 9 Output (MSB)
18 QD8 Q-Channel, Data Bit 8 Output
19 QD7 Q-Channel, Data Bit 7 Output
20 QD6 Q-Channel, Data Bit 6 Output
21 QD5 Q-Channel, Data Bit 5 Output
22 QD4 Q-Channel, Data Bit 4 Output
23 QD3 Q-Channel, Data Bit 3 Output

Analog Ground
I-Channel Positive Analog Input
I-Channel Negative Analog Input

Binary and High for Twos Complement
Output Format)

I-Channel Voltage Reference Input

RIN

+1.25V Reference Voltage Output
(Decouple with 0.1µF Capacitor)

Q-Channel Voltage Reference Input

RIN

Q-Channel Negative Analog Input

IN-

Q-Channel Positive Analog Input

IN+

Analog Ground
Analog Supply

CC

Digital Supply

CC

Digital Ground

Pin Descriptions (Continued)

PIN NO. NAME DESCRIPTION

24 QD2 Q-Channel, Data Bit 2 Output
25 QD1 Q-Channel, Data Bit 1 Output
26 QD0 Q-Channel, Data Bit 0 Output (LSB)
27 D

GND

28 DV
29 A

GND

30 AV
31 AV
32 A

GND

33 DV
34 D

GND

35 ID0 I-Channel, Data Bit 0 Output (LSB)
36 ID1 I-Channel, Data Bit 1 Output
37 ID2 I-Channel, Data Bit 2 Output
38 ID3 I-Channel, Data Bit 3 Output
39 ID4 I-Channel, Data Bit 4 Output
40 ID5 I-Channel, Data Bit 5 Output
41 ID6 I-Channel, Data Bit 6 Output
42 ID7 I-Channel, Data Bit 7 Output
43 ID8 I-Channel, Data Bit 8 Output
44 ID9 I-Channel, Data Bit 9 Output (MSB)
45 D

GND

46 DV
47 ICLK I-Channel Clock Input
48 AV

CC

CC
CC

CC

CC

CC

Digital Ground
Digital Supply
Analog Ground
Analog Supply
Analog Supply
Analog Ground
Digital Supply
Digital Ground

Digital Ground
Digital Supply

Analog Supply

3-4

ISL5740

Absolute Maximum Ratings T

Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .4V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V

Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV

Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV

Operating Conditions

Temperature Range

ISL5740IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications AV

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ACCURACY

Resolution 10 - - Bits
Integral Linearity Error, INL fIN = 10MHz - 2 1 LSB
Differential Linearity Error, DNL

(Guaranteed No Missing Codes)
Offset Error, V
Full Scale Error, FSE fIN = DC -3 1 3 %f
Gain Matching Full Scale (Peak-to-Peak) - ±1.5 6 %f

DYNAMIC CHARACTERISTICS

Minimum Conversion Rate No Missing Codes - 1 - MSPS
Maximum Conversion Rate No Missing Codes 60 - - MSPS
Effective Number of Bits, ENOB fIN = 10MHz 9.1 - - Bits
Signal to Noise and Distortion Ratio, SINAD fIN = 10MHz 56.8 - - dB

--------------------------------------------------------------=

RMS Noise + Distortion

OS

RMS Signal

= 25oC Thermal Information

A

Thermal Resistance (Typical, Note 1) θJA (oC/W)

ISL5740IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

CC
CC

= DVCC = +3.0V; I/QV

CC

C

= 10pF; TA = 25oC; Differential Analog Input, Unless Otherwise Specified

L

fIN = 10MHz - ±0.4 ±1.0 LSB

fIN = DC -36 12 +36 LSB

= 1.25V; fS = 60MSPS at 50% Duty Cycle;

RIN

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(Lead Tips Only)

S
S

Signal to Noise Ratio, SNR f

RMS Signal

-------------------------------=

RMS Noise

Total Harmonic Distortion, THD fIN = 10MHz -70 - - dBc
2nd Harmonic Distortion fIN = 10MHz - - - dBc
3rd Harmonic Distortion fIN = 10MHz - - - dBc
Spurious Free Dynamic Range, SFDR fIN = 10MHz 70 - - dBc
Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz - - - dBc
I/Q Channel Crosstalk - -75 - dBc
I/Q Channel Offset Match - 10 - LSB
I/Q Channel Full Scale Error Match - 10 - LSB
Transient Response (Note 2) - 1 - Cycle
Over-Voltage Recovery 0.2V Overdrive (Note 2) - 1 - Cycle

= 10MHz 57 - - dB

IN

3-5

ISL5740

Electrical Specifications AV

= DVCC = +3.0V; I/QV

CC

= 1.25V; fS = 60MSPS at 50% Duty Cycle;

RIN

CL= 10pF; TA = 25oC; Differential Analog Input, Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT

Maximum Peak-to-Peak Differential Analog Input

- ±0.5 - V

Range (I/QIN+ - I/QIN-)
Maximum Peak-to-Peak Single-Ended

- 1.0 - V

Analog Input Range
Analog Input Resistance, R
Analog Input Capacitance, C
Analog Input Bias Current, IB+ or IB-V

IN+

IN+

or R

or C

IN-

IN-

V

, V

= V

IN+

IN-

V

, V

IN+

IN-

, V

IN+

IN-

, DC - 1 - MΩ

REF

= V

, DC - 10 - pF

REF

= V

REF

, DC

-10 - 10 µA

(Notes 2, 3)

Differential Analog Input Bias Current
I

= (IB+- IB-)

BDIFF

(Notes 2, 3) -0.5 - 0.5 µA

Full Power Input Bandwidth, FPBW (Note 2) - 400 - MHz
Analog Input Common Mode Voltage Range

Differential Mode (Note 2) 0.25 - AVCC-0.25 V

(VIN++ VIN-) / 2

INTERNAL VOLTAGE REFERENCE

Reference Output Voltage, V
Reference Output Current, I

(Loaded) - 1.25 - V

ROUT

ROUT

-1 - mA

Reference Temperature Coefficient - 200 - ppm/oC

REFERENCE VOLTAGE INPUT

Reference Voltage Input, V

RIN

Total Reference Resistance, R
Reference Current, I

RIN

RIN

With V
With V

= 1.25V - - - MΩ

RIN

= 1.25V - - - mA

RIN

- 1.25 - V

SAMPLING CLOCK INPUT

Input Logic High Voltage, V
Input Logic Low Voltage, V
Input Logic High Current, I
Input Logic Low Current, I
Input Capacitance, C

IN

IH

IL

IH

IL

CLK 2.0 - - V
CLK - - 0.8 V
CLK, VIH= 5V -1 - 1 µA
CLK, VIL= 0V -1 - 1 µA
CLK - - - pF

DIGITAL OUTPUTS

Output Logic High Voltage, V
Output Logic Low Voltage, V
Output Capacitance, C

OUT

OH

OL

IOH= 100µA 2.45 2.98 - V
IOL= 100µA - 0.001 0.5 V

-7 - pF

TIMING CHARACTERISTICS

Aperture Delay, t

AP

-- - ns
Aperture Delay Match - 100 - ps
Aperture Jitter, t

AJ

Data Output Hold, t
Data Output Delay, t
Data Latency, t

LAT

H

OD

For a Valid Sample (Note 2) - 7 - Cycles

-5 -ps

RMS

-3 - ns

- 4.5 - ns

Power-Up Initialization Data Invalid Time (Note 2) - - - Cycles
Sample Clock Pulse Width (Low) (Note 2) 7.5 8.3 - ns

3-6

ISL5740

Electrical Specifications AV

= DVCC = +3.0V; I/QV

CC

= 1.25V; fS = 60MSPS at 50% Duty Cycle;

RIN

CL= 10pF; TA = 25oC; Differential Analog Input, Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Sample Clock Pulse Width (High) (Note 2) 7.5 8.3 - ns
Sample Clock Duty Cycle Variation - ±5- %

POWER SUPPLY CHARACTERISTICS

Analog Supply Voltage, AV
Digital Supply Voltage, DV
Supply Current Total, I

CCT

Analog Supply Current IA
Digital Supply Current ID

CC

Power Dissipation Total P
Offset Error Sensitivity, ∆V

CC

T

CC

CC1

OS

and DV

CC2

(Note 2) 2.7 3.0 3.6 V
(Note 2) 2.7 3.0 3.6 V

- - 93.3 mA

- - 68.3 mA

- - 25 mA

- - 280 mW

AVCCor DVCC = 3V ±5% - ±0.5 - LSB

Gain Error Sensitivity, ∆FSE AVCC or DVCC= 3V ±5% - ±0.5 - LSB

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. With the clock low and DC input.

3-7

Timing Waveforms

ANALOG

INPUT

ISL5740

CLOCK

INPUT

S

N - 1HN - 1SN

HNS

N + 1HN + 1SN + 2

INPUT

S/H

1ST

STAGE

2ND

STAGE

9TH

STAGE

DAT A

OUTPUT

B2,

N - 2

B1,

B9,

N - 1

N - 5

B2,

D

N - 1

N - 6

B9,

B1,

N

N - 4

B2,

D

N

N - 5

B1,

N + 1

t

LAT

NOTES:

4. SN: N-th sampling period.

5. HN: N-th holding period.

6. BM, N: M-th stage digital output corresponding to N-th sampled input.

7. DN: Final data output corresponding to N-th sampled input.

FIGURE 1. ISL5740 INTERNAL CIRCUIT TIMING

S

N + 5HN + 5SN + 6HN + 6SN + 7HN + 7SN + 8HN + 8

B1,

B9,

N + 4

N

B2,

D

N + 4

N - 1

B1,

B9,

N + 5

N + 1

B2,

D

N + 5

N

B1,

B9,

N + 6

N + 2

B2,

D

N + 6

N + 1

B1,

B9,

N + 7

N + 3

D

N + 2

ANALOG

INPUT

CLOCK

INPUT

DAT A

OUTPUT

3-8

1.5V

t

AP

t

AJ

1.5V

t

OD

t

H

DATA N-1 DATA N

2.4V

0.5V

FIGURE 2. ISL5740 INPUT TO OUTPUT TIMING

ISL5740

TABLE 1. A/D CODE TABLE

OFFSET BINARY OUTPUT CODE

DIFFERENTIAL INPUT

CODE CENTER

DESCRIPTION

+Full Scale (+fS) -1/4LSB 0.499756V 1 1 11111111

1

+f

- 1

/4LSB 0.498779V 1 1 11111110

S

+3/4LSB 732.422µV 1000000000

-1/4LSB -244.141µV 0111111111

-fS + 13/4LSB -0.498291V 0 0 00000001

-Full Scale (-fS) +3/4LSB -0.499268V 0 0 00000000

NOTE:

8. The voltages listed above represent the ideal center of each output code shown with V

VOLTAGE

(I/QIN+ - I/QIN-)

MSB LSB

I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0

= +1.25V.

REFIN

Detailed Description

Theory of Operation

The ISL5740 is a dual 10-bit fully differentialsampling pipeline
A/D converter with digital error correction logic. Figure 15
depicts the circuit for the front end differential-in-differential­out sample-and-hold (S/H) amplifiers. The switches are
controlled by an internal sampling clock which is a non­overlapping two phase signal, Φ
master sampling clock. During the sampling phase, Φ
input signal is applied to the sampling capacitors, C
same time the holding capacitors, C
analog ground. At the falling edge of Φ
sampled on the bottom plates of the sampling capacitors. In
the next clock phase, Φ

, the two bottom plates of the

2

sampling capacitors are connected together and the holding
capacitors are switched to the op amp output nodes. The
charge then redistributes between C
sample-and-hold cycle. The front end sample-and-hold output
is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and­hold function but will also convert a single-ended input to a
fully-differential output for the con verter core. During the
sampling phase, the I/Q
switch and C

. The relatively small values of these

S

IN

components result in a typical full power input bandwidth of
400MHz for the conv erter .

and Φ2, derived from the

1

, are discharged to

H

the input signal is

1

and CHcompleting one

S

, the

1

. At the

S

pins see only the on-resistance ofa

Φ

1

Φ

1

C

I/Q

IN+

I/Q

IN-

Φ

FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD

S

Φ

2

C

S

1

Φ

1

C

H

+

-

+

-

C

H

Φ

1

V

OUT+

V

OUT-

Φ

1

As illustrated in the Functional Block Diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a two­bit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.

The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.

3-9

Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus following the 6th cycle of the clock after the

ISL5740

analog sample is taken (see the timing diagram in Figure 1).
This time delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital output data is provided in offset
binary format (see Table 1, A/D Code Table).

Internal Reference Voltage Output, V

ROUT

The ISL5740 is equipped with an internal 1.25V bandgap
referencevoltage generator, therefore, no external reference
voltage is required. V

should be connected to V

ROUT

RIN

when using the internal reference voltage. An external, user­supplied, 0.1µF capacitor may be connected from the V

ROUT

output pin to filter any stray board noise.

Reference Voltage Inputs, I/Q V

REFIN

The ISL5740 is designed to accept a 1.25V reference
voltage source at the V
channels. Typicaloperation of the converter requires V
be set at 1.25V. The ISL5740 is tested with V
to V

yielding a fully differential analog input voltage

ROUT

input pins for the I and Q

RIN

connected

RIN

RIN

range of ±0.5V.
The user does have the option of supplying an external 1.25V

reference voltage. As a result of the high input impedance
presented at the V

input pin, MΩ typically, the external

RIN

reference voltage being used is only required to source small
amount of reference input current.

In order to minimize overall conver ter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, V

RIN

.

Analog Input, Differential Connection

The analog input of the ISL5740 is a differential input that
can be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 16 and Figure 17) will deliver
the best performance from the converter.

V

IN

R

R

-V

IN

I/QIN+

I/QV

I/QIN-

ISL5740

RIN

significantly with the value of the analog input common
mode voltage.

Forthe AC coupled differential input (Figure 16) and with V
connected to V

-V

input signals are 0.5V

IN

out of phase with V
scale when the I/Q
I/Q

- input is at I/Q

IN

, full scale is achieved when the VIN and

ROUT

. The converter will be at positive full

IN

+ input is at I/Q

IN

VRIN

, with -VIN being 180 degrees

P-P

+ 0.25V and the

VRIN

- 0.25V (I/QIN+ - I/QIN- = +0.5V).

RIN

Conversely, the converter will be at negative full scale when
the I/Q
I/Q

+ input is equal to I/Q

IN

+ 0.25V (I/QIN+ - I/QIN- = -0.5V).

VRIN

- 0.25V and I/QIN- is at

VRIN

The analog input can be DC coupled (Figure 17) as long as
the inputs are within the analog input common mode voltage
range (0.25V ≤ VDC ≤ 2.75V).

The resistors, R, in Figure 17 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,

to

connected from I/Q

+ to I/QIN- will help filter any high

IN

frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.

V

IN

V

DC

R

-V

IN

V

DC

FIGURE 5. DC COUPLED DIFFERENTIAL INPUT

R

I/QIN+

I/QV

I/QIN-

ISL5740

RIN

C

Analog Input, Single-Ended Connection

The configuration shown in Figure 18 may be used with a
single ended AC coupled input.

V

IN

R

V

DC

I/QIN+

ISL5740

FIGURE 4. AC COUPLED DIFFERENTIAL INPUT

Since the ISL5740 is powered by a single +3V analog
supply, the analog input is limited to be between ground and
+3V. For the differential input connection this implies the
analog input common mode voltage can range from 0.25V to

2.75V. The performance of the ADC does not change

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FIGURE 6. AC COUPLED SINGLE ENDED INPUT

Again, with V
sinewave, then I/QIN+ is a 1.0V
positive voltage equal to V
positive full scale when I/Q

connected to V

RIN

ROUT

sinewave riding on a

P-P

. The converter will be at

DC

+ is at VDC + 0.5V (I/QIN+ -

IN

I/QIN-

, if VIN is a 1V

P-P

- = +0.5V) and will be at negative full scale when I/QIN+

I/Q

IN

is equal to V

- 0.5V (I/QIN+ - I/QIN- = -0.5V). Sufficient

DC

headroom must be provided such that the input voltage
never goes above +3V or below AGND. In this case, V

DC

could range between 0.5V and 2.5V without a significant
change in ADC performance. The simplest way to produce
VDC is to use the I/Q

bias source, I/QVDC, output of

VRIN

the ISL5740.
The single ended analog input can be DC coupled

(Figure 19) as long as the input is within the analog input
common mode voltage range.

V

IN

V

DC

R

V

DC

FIGURE 7. DC COUPLED SINGLE ENDED INPUT

I/QIN+

C

ISL5740

I/QIN-

The resistor, R, in Figure 19 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from I/Q

+ to I/QIN- will help filter any high

IN

frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.

A single ended source may give better overall system
performance if it is first converted to differential before
driving the ISL5740.

Operational Mode

The ISL5740 contains severaloperational modes including a
normal two channel operation, placing one or both channels
in standby and delaying the Q channel data 1/2 clock cycle.
The operational mode is selected via the S1 and S2 pins and
is asynchronous to either clock. When either channel is
placed in standby, the output data is stalled and not high
impedance. When recovering from standby, valid data is
available after 20 clock cycles.

ISL5740

OPERATIONAL MODES

S1 S2 MODE

0 0 Standby I and Q Channels.
0 1 I channel operates normally with Q Channel in

standby mode.

1 0 I and Q Channels operating with I/Q output data in

phase.

1 1 Iand Q Channels operating with Q data 180 degrees

out of phase.

Sampling Clock Requirements

The ISL5740 sampling clock input provides a standard high­speed interface to external TTL/CMOS logic families.

In order to ensure rated performance of the ISL5740, the
duty cycle of the clock should be held at 50% ±5%. It must
also have low jitter and operate at standard TTL/CMOS
levels.

Performance of the ISL5740 will only be guaranteed at
conversion rates above 1MSPS (Typ). This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1MSPS must be performed
before valid data is available.

Supply and Ground Considerations

The ISL5740 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the ISL5740 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply can be isolated by a ferrite
bead from the digital supply.

Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.

The delay mode can be used to set the Q channel 180
degrees out phase of the I channel if the same clock is
driving both channels. If separate, inverted clocks are used
forthe I and Q channels,this featurecan be used to align the
data.

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ISL5740

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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