Page 1
ISL5640
ADVANCE INFORMATION
Data Sheet June 2000
3V Dual 8-Bit, 20/40/60MSPS A/D
Converter with Internal Voltage Reference
The ISL5640 is a monolithic, dual 8-bit analog-to-digital
converter fabricated in an advanced CMOS process. It is
designed for high speed applications where integration,
bandwidth and accuracy are essential. The ISL5640
features a 9-stage pipeline architecture. The fully pipelined
architecture and an innovative input stage enable the
ISL5640 to accept a variety of input configurations, singleended or fully differential. Only one external clock is
necessary to drivebothconverters and an internal band-gap
voltage reference is provided. This allows the system
designer to realize an increased level of system integration
resulting in decreased cost and power dissipation.
The ISL5640 has excellent dynamic performance while
consuming less than 100mW power at 40MSPS. The A/D
only requires a single +3.0V power supply. Data output
latches are provided which present valid data to the output
bus with a latency of 5 clock cycles.
File Number 4657.3
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .40MSPS
• 7.4 Bits at f
• Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 100mW
• Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . <1mW
• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz
• SFDR at f
• Excellent Channel-to-Channel Isolation. . . . . . . . . >75dB
• On-Chip Sample and Hold Amplifiers
• Internal Bandgap Voltage Reference . . . . . . . . . . . . 1.25V
• Single Supply Voltage Operation . . . . . . . . . . . . . . . +3.0V
• Offset Binary or Two’s Complement Output Format
• Dual 8-Bit A/D Converters on a Monolithic Chip
• Pin Compatible Upgrade to AD9288
= 1MHz
IN
= 1MHz. . . . . . . . . . . . . . . . . . . . . . . . . .55dB
IN
The ISL5640 is offered in 20MSPS, 30MSPS, 40MSPS and
60MSPS sampling rates.
Ordering Information
TEMP.
PART
NUMBER
RANGE
(oC) PACKAGE PKG. NO.
ISL5640/2IN -40 to 85 48 Ld LQFP Q48.7x7 20
ISL5640/3IN -40 to 85 48 Ld LQFP Q48.7x7 30
ISL5640/4IN -40 to 85 48 Ld LQFP Q48.7x7 40
ISL5640/6IN -40 to 85 48 Ld LQFP Q48.7x7 60
ISL5640 EVAL 25 Evaluation Platform
SAMPLING
RATE
(MSPS)
Applications
• Wireless Local Loop
• PSK and QAM I&Q Demodulators
• Medical Imaging
• High Speed Data Acquisition
Pinout
48 LEAD LQFP
TOP VIEW
CC
CC
IV
V
ROUT
QV
GND
I
IN
I
IN
DFS
RIN
RIN
S1
S2
Q
IN
QIN+
GND
DV
I CLK
AV
1
+
-
-
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16
GND
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
373839404142434445464748
36
35
34
33
32
31
30
29
28
27
26
25
2423222120191817
N/C
N/C
GND
DV
GND
AV
AV
GND
DV
GND
N/C
N/C
CC
CC
CC
CC
3-1
CC
CC
AV
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
DV
Q CLK
GND
QD5
QD7
QD6
QD4
QD3
QD2
QD1
QD0
| Copyright © Intersil Corporation 2000
Page 2
Functional Block Diagram
-
I/Q
IN
I/Q
+
IN
S/H
STAGE 1
ISL5640
CLOCK
I/QCLK
2-BIT
FLASH
+
-
∑
X2
STAGE 8
2-BIT
FLASH
+
∑
-
2-BIT
DAC
2-BIT
DAC
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
I/QD7 (MSB)
I/QD6
I/QD5
I/QD4
I/QD3
I/QD2
I/QD1
I/QD0 (LSB)
V
I/QV
ROUT
RIN
X2
REFERENCE
3-2
2-BIT
FLASH
STAGE 9
AV
CC
AGND DV
CC
DGND
I OR Q CHANNEL
MODE
DATA FORMAT
S1/S2
DFS
Page 3
Typical Application Schematic
ISL5640
ISL5640
+
I
IN
- (3) IIN-
I
IN
QIN+
QIN-
0.1µF
(2) I
+
IN
(11) QIN+
(10) QIN-
(5) IV
RIN
(6) QV
RIN
(7) V
ROUT
ID1 (38)
ID2 (39)
ID3 (40)
ID4 (31)
ID5 (42)
ID6 (43)
(MSB) ID7 (44)
(LSB) QD0 (24)
QD1 (23)
QD2 (22)
QD3 (21)
QD4 (20)
QD5 (19)
QD6 (18)
(MSB) QD7 (17)
ICLK (47)
QCLK (14)
ID0(LSB) ID0 (37)
ID1
ID2
ID3
ID4
ID5
ID6
ID7
QD0
QD1
QD2
QD3
QD4
QD5
QD6
QD7
CLOCK
+3V
10µF
S1 (8)
S2 (9)
DFS (4)
AGND
(13,30,31,48) AV
(12,29,32) AGND
DGND
+
0.1µF
BNC
CC
DVCC(15, 28, 33, 46)
DGND (16, 27, 34, 45)
10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
S1
S2
DFS
0.1µF10µF
+
3V
3-3
Page 4
ISL5640
Pin Descriptions
PIN NO. NAME DESCRIPTION
1A
2I
3I
GND
IN+
IN-
4 DFS Data Format Select (Low for Offset
5IV
6V
RIN
ROUT
7QV
8 S1 Mode Select Pin 1 (See Table)
9 S2 Mode Select Pin 2 (See Table)
10 Q
11 Q
12 A
IN+
GND
13 AV
14 QCLK Q-Channel Clock Input
15 DV
16 D
GND
17 QD7 Q-Channel, Data Bit 7 Output (MSB)
18 QD6 Q-Channel, Data Bit 6 Output
19 QD5 Q-Channel, Data Bit 5 Output
20 QD4 Q-Channel, Data Bit 4 Output
21 QD3 Q-Channel, Data Bit 3 Output
22 QD2 Q-Channel, Data Bit 2 Output
23 QD1 Q-Channel, Data Bit 1 Output
Analog Ground
I-Channel Positive Analog Input
I-Channel Negative Analog Input
Binary and High for Twos Complement
Output Format)
I-Channel Voltage Reference Input
+1.25V Reference Voltage Output
(Decouple with 0.1µF Capacitor)
Q-Channel Voltage Reference Input
RIN
Q-Channel Negative Analog Input
IN-
Q-Channel Positive Analog Input
Analog Ground
Analog Supply
CC
Digital Supply
CC
Digital Ground
Pin Descriptions (Continued)
PIN NO. NAME DESCRIPTION
24 QD0 Q-Channel, Data Bit 0 Output (LSB)
25 N/C No Connect
26 N/C No Connect
27 D
GND
28 DV
29 A
GND
30 AV
31 AV
32 A
GND
33 DV
34 D
GND
35 N/C No Connect
36 N/C No Connect
37 ID0 I-Channel, Data Bit 0 Output
38 ID1 I-Channel, Data Bit 1 Output
39 ID2 I-Channel, Data Bit 2 Output
40 ID3 I-Channel, Data Bit 3 Output
41 ID4 I-Channel, Data Bit 4 Output
42 ID5 I-Channel, Data Bit 5 Output
43 ID6 I-Channel, Data Bit 6 Output
44 ID7 I-Channel, Data Bit 7 Output (MSB)
45 D
GND
46 DV
47 ICLK I-Channel Clock Input
48 AV
CC
CC
CC
CC
CC
CC
Digital Ground
Digital Supply
Analog Ground
Analog Supply
Analog Supply
Analog Ground
Digital Supply
Digital Ground
Digital Ground
Digital Supply
Analog Supply
3-4
Page 5
ISL5640
Absolute Maximum Ratings T
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .4V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV
= 25oC Thermal Information
A
Thermal Resistance (Typical, Note 1) θJA (oC/W)
ISL5640IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
CC
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
(Lead Tips Only)
Temperature Range
ISL5640IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications A
VDD=DVDD
C
= 10pF; TA = 25oC; Unless Otherwise Specified
L
= +3.3V; VIN= 1.50V; fS= 40MSPS at 50% Duty Cycle;
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ACCURACY
Resolution 8 - - Bits
Integral Linearity Error, INL fIN = 1MHz - 0.5 - LSB
Differential Linearity Error, DNL
fIN = 1MHz - ±0.2 ±1.0 LSB
(Guaranteed No Missing Codes)
Offset Error, V
OS
fIN = DC -10 - +10 LSB
Full Scale Error, FSE fIN = DC - 1 - LSB
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate No Missing Codes - - - MSPS
Maximum Conversion Rate No Missing Codes 40 - - MSPS
Effective Number of Bits, ENOB fIN = 1MHz - 7.5 - Bits
Signal to Noise and Distortion Ratio, SINAD fIN = 1MHz - 46 - dB
RMS Signal
--------------------------------------------------------------=
RMS Noise + Distortion
Signal to Noise Ratio, SNR f
RMS Signal
-------------------------------=
RMS Noise
= 10MHz - 47 - dB
IN
Total Harmonic Distortion, THD fIN = 10MHz - -53 - dBc
2nd Harmonic Distortion fIN = 10MHz - -54 - dBc
3rd Harmonic Distortion fIN = 10MHz - -70 - dBc
Spurious Free Dynamic Range, SFDR fIN = 10MHz - 54 - dBc
Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz - - - dBc
I/Q Channel Crosstalk - - - dBc
I/Q Channel Offset Match - - - LSB
I/Q Channel Full Scale Error Match - - - LSB
Transient Response (Note 2) - - - Cycle
Over-Voltage Recovery 0.2V Overdrive (Note 2) - - - Cycle
ANALOG INPUT
Maximum Peak-to-Peak Single-Ended
- 1.0 - V
Analog Input Range
Analog Input Resistance, R
Analog Input Capacitance, C
INA
INA
or R
or C
INB
INB
V
, V
= V
INA
INB
V
, V
INA
INB
, DC - - - MΩ
REF
= 1.5V, DC - - - pF
3-5
Page 6
ISL5640
Electrical Specifications A
VDD=DVDD
= +3.3V; VIN= 1.50V; fS= 40MSPS at 50% Duty Cycle;
CL= 10pF; TA = 25oC; Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Analog Input Bias Current, IBA or IBBV
INA/VINB
= ART/BRT, ARB/BRB, DC
---µA
(Notes 2, 3)
Full Power Input Bandwidth, FPBW fS= 40MHz, (Note 2) - 250 - MHz
REFERENCE VOLTAGE INPUT
Reference Voltage Input Range - - - V
Total Reference Resistance, R
Reference Current, I
RIN
RIN
- 300 - Ω
---mA
SAMPLING CLOCK INPUT
Input Logic High Voltage, V
Input Logic Low Voltage, V
Input Logic High Current, I
Input Logic Low Current, I
Input Capacitance, C
IN
IH
IL
IH
IL
CLK 2.0 - - V
CLK - - 0.8 V
CLK, VIH= 3.3V - - - µA
CLK, VIL= 0V - - - µA
CLK - - - pF
DIGITAL OUTPUTS
Output Logic High Voltage, V
Output Logic Low Voltage, V
Output Logic High Voltage, V
Output Logic Low Voltage, V
Output Capacitance, C
OUT
OH
OL
OH
OL
IOH= 100µA; D
IOL= 1.5mA; D
IOH= 100µA; D
IOL= 100µA; D
= 3.3V - - - V
VDD
= 3.3V - - - V
VDD
= 3.0V - - - V
VDD
= 3.0V - - - V
VDD
---pF
TIMING CHARACTERISTICS
Aperture Delay, t
Aperture Jitter, t
AP
AJ
Data Output Hold, t
Data Output Delay, t
Data Latency, t
LAT
H
OD
For a Valid Sample (Note 2) - 5 - Cycles
-4- ns
-5-ps
RMS
- 10.7 - ns
- 11.7 - ns
Power-Up Initialization Data Invalid Time (Note 2) - - - Cycles
Sample Clock Pulse Width (Low) (Note 2) 11.25 12.5 - ns
Sample Clock Pulse Width (High) (Note 2) 11.25 12.5 - ns
Sample Clock Duty Cycle Variation - ±5- %
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, A
Digital Supply Voltage, D
Supply Current, I
DD
VDD
VDD
(Note 2) 3.0 3.3 3.6 V
(Note 2) 3.0 3.3 3.6 V
fS= 40MSPS - 30.3 - mA
Power Dissipation - 100 110 mW
Offset Error Sensitivity, ∆V
OS
Gain Error Sensitivity, ∆FSE A
A
VDD
VDD
or D
or D
= 3.3V ±5% - ±0.125 - LSB
VDD
= 3.3V ±5% - ±0.15 - LSB
VDD
NOTES:
1. Parameter guaranteed by design or characterization and not production tested.
2. With the clock low and DC input.
3-6
Page 7
Timing Waveforms
ANALOG
INPUT
ISL5640
CLOCK
INPUT
S
N - 1HN - 1SN
HNS
N + 1HN + 1SN + 2
INPUT
S/H
1ST
STAGE
2ND
STAGE
9TH
STAGE
DAT A
OUTPUT
B2,
N - 2
B1,
B9,
N - 1
N - 5
B2,
D
N - 1
N - 6
B9,
B1,
N
N - 4
B2,
D
N
N - 5
B1,
N + 1
t
LAT
NOTES:
3. SN: N-th sampling period.
4. HN: N-th holding period.
5. BM, N: M-th stage digital output corresponding to N-th sampled input.
6. DN: Final data output corresponding to N-th sampled input.
FIGURE 1. ISL5640 INTERNAL CIRCUIT TIMING
S
N + 5HN + 5SN + 6HN + 6SN + 7HN + 7SN + 8HN + 8
B1,
B9,
N + 4
N
B2,
D
N + 4
N - 1
B1,
B9,
N + 5
N + 1
B2,
D
N + 5
N
B1,
B9,
N + 6
N + 2
B2,
D
N + 6
N + 1
B1,
B9,
N + 7
N + 3
D
N + 2
ANALOG
INPUT
CLOCK
INPUT
DAT A
OUTPUT
3-7
1.5V
t
AP
t
AJ
1.5V
t
OD
t
H
DATA N-1 DATA N
2.4V
0.5V
FIGURE 2. ISL5640 INPUT TO OUTPUT TIMING
Page 8
ISL5640
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
DIFFERENTIAL INPUT
CODE CENTER
DESCRIPTION
+Full Scale (+fS) -1/4LSB 0.499756V 1 1 11111111
1
+f
- 1
/4LSB 0.498779V 1 1 11111110
S
+3/4LSB 732.422µV 1000000000
-1/4LSB -244.141µV 0111111111
-fS + 13/4LSB -0.498291V 0 0 00000001
-Full Scale (-fS) +3/4LSB -0.499268V 0 0 00000000
NOTE:
7. The voltages listed above represent the ideal center of each output code shown with V
VOLTAGE
(I/QIN+ - I/QIN-)
MSB LSB
I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0
= +1.25V.
REFIN
Detailed Description
Theory of Operation
The ISL5640 is a dual 8-bit fully differential sampling pipeline
A/D converter with digital error correction logic. Figure 15
depicts the circuit for the front end differential-in-differentialout sample-and-hold (S/H) amplifiers. The switches are
controlled by an internal sampling clock which is a nonoverlapping two phase signal, Φ
master sampling clock. During the sampling phase, Φ
input signal is applied to the sampling capacitors, C
same time the holding capacitors, C
analog ground. At the falling edge of Φ
sampled on the bottom plates of the sampling capacitors. In
the next clock phase, Φ
, the two bottom plates of the
2
sampling capacitors are connected together and the holding
capacitors are switched to the op amp output nodes. The
charge then redistributes between C
sample-and-hold cycle. The front end sample-and-hold output
is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-andhold function but will also convert a single-ended input to a
fully-differential output for the con verter core. During the
sampling phase, the I/Q
switch and C
. The relatively small values of these
S
IN
components result in a typical full power input bandwidth of
400MHz for the conv erter .
and Φ2, derived from the
1
, are discharged to
H
the input signal is
1
and CHcompleting one
S
, the
1
. At the
S
pins see only the on-resistance ofa
Φ
1
Φ
1
C
I/Q
IN+
I/Q
IN-
Φ
FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD
S
Φ
2
C
S
1
Φ
1
C
H
+
-
+
-
C
H
Φ
1
V
OUT+
V
OUT-
Φ
1
As illustrated in the Functional Block Diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a twobit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
3-8
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus following the 6th cycle of the clock after the
Page 9
ISL5640
analog sample is taken (see the timing diagram in Figure 1).
This time delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital output data is provided in offset
binary format (see Table 1, A/D Code Table).
Internal Reference Voltage Output, V
ROUT
The ISL5640 is equipped with an internal 1.25V bandgap
referencevoltage generator, therefore, no external reference
voltage is required. V
should be connected to V
ROUT
RIN
when using the internal reference voltage. An external, usersupplied, 0.1µF capacitor may be connected from the V
ROUT
output pin to filter any stray board noise.
Reference Voltage Inputs, I/Q V
REFIN
The ISL5640 is designed to accept a 1.25V reference
voltage source at the V
channels. Typicaloperation of the converter requires V
be set at 1.25V. The ISL5640 is tested with V
to V
yielding a fully differential analog input voltage
ROUT
input pins for the I and Q
RIN
connected
RIN
RIN
range of ±0.5V.
The user does have the option of supplying an external 1.25V
reference voltage. As a result of the high input impedance
presented at the V
input pin, MΩ typically, the external
RIN
reference voltage being used is only required to source small
amount of reference input current.
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, V
RIN
.
Analog Input, Differential Connection
The analog input of the ISL5640 is a differential input that
can be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 16 and Figure 17) will deliver
the best performance from the converter.
V
IN
R
R
-V
IN
I/QIN+
I/QV
I/QIN-
ISL5640
RIN
significantly with the value of the analog input common
mode voltage.
Forthe AC coupled differential input (Figure 16) and with V
connected to V
-V
input signals are 0.5V
IN
out of phase with V
scale when the I/Q
I/Q
- input is at I/Q
IN
, full scale is achieved when the VIN and
ROUT
. The converter will be at positive full
IN
+ input is at I/Q
IN
VRIN
, with -VIN being 180 degrees
P-P
+ 0.25V and the
VRIN
- 0.25V (I/QIN+ - I/QIN- = +0.5V).
RIN
Conversely, the converter will be at negative full scale when
the I/Q
I/Q
+ input is equal to I/Q
IN
+ 0.25V (I/QIN+ - I/QIN- = -0.5V).
VRIN
- 0.25V and I/QIN- is at
VRIN
The analog input can be DC coupled (Figure 17) as long as
the inputs are within the analog input common mode voltage
range (0.25V ≤ VDC ≤ 2.75V).
The resistors, R, in Figure 17 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
to
connected from I/Q
+ to I/QIN- will help filter any high
IN
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
V
IN
V
DC
R
-V
IN
V
DC
FIGURE 5. DC COUPLED DIFFERENTIAL INPUT
R
I/QIN+
I/QV
I/QIN-
ISL5640
RIN
C
Analog Input, Single-Ended Connection
The configuration shown in Figure 18 may be used with a
single ended AC coupled input.
V
IN
R
V
DC
I/QIN+
ISL5640
FIGURE 4. AC COUPLED DIFFERENTIAL INPUT
Since the ISL5640 is powered by a single +3V analog
supply, the analog input is limited to be between ground and
+3V. For the differential input connection this implies the
analog input common mode voltage can range from 0.25V to
2.75V. The performance of the ADC does not change
3-9
FIGURE 6. AC COUPLED SINGLE ENDED INPUT
Again, with V
sinewave, then I/QIN+ is a 1.0V
positive voltage equal to V
positive full scale when I/Q
connected to V
RIN
ROUT
sinewave riding on a
P-P
. The converter will be at
DC
+ is at VDC + 0.5V (I/QIN+ -
IN
I/QIN-
, if VIN is a 1V
P-P
Page 10
- = +0.5V) and will be at negative full scale when I/QIN+
I/Q
IN
is equal to V
- 0.5V (I/QIN+ - I/QIN- = -0.5V). Sufficient
DC
headroom must be provided such that the input voltage
never goes above +3V or below AGND. In this case, V
DC
could range between 0.5V and 2.5V without a significant
change in ADC performance. The simplest way to produce
VDC is to use the I/Q
bias source, I/QVDC, output of
VRIN
the ISL5640.
The single ended analog input can be DC coupled
(Figure 19) as long as the input is within the analog input
common mode voltage range.
V
IN
V
DC
R
V
DC
FIGURE 7. DC COUPLED SINGLE ENDED INPUT
I/QIN+
C
ISL5640
I/QIN-
The resistor, R, in Figure 19 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from I/Q
+ to I/QIN- will help filter any high
IN
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the ISL5640.
Operational Mode
The ISL5640 contains severaloperational modes including a
normal two channel operation, placing one or both channels
in standby and delaying the Q channel data 1/2 clock cycle.
The operational mode is selected via the S1 and S2 pins and
is asynchronous to either clock. When either channel is
placed in standby, the output data is stalled and not high
impedance. When recovering from standby, valid data is
available after 20 clock cycles.
ISL5640
OPERATIONAL MODES
S1 S2 MODE
0 0 Standby I and Q Channels.
0 1 I channel operates normally with Q Channel in
standby mode.
1 0 I and Q Channels operating with I/Q output data in
phase.
1 1 Iand Q Channels operating with Q data 180 degrees
out of phase.
Sampling Clock Requirements
The ISL5640 sampling clock input provides a standard highspeed interface to external TTL/CMOS logic families.
In order to ensure rated performance of the ISL5640, the
duty cycle of the clock should be held at 50% ±5%. It must
also have low jitter and operate at standard TTL/CMOS
levels.
Performance of the ISL5640 will only be guaranteed at
conversion rates above 1MSPS (Typ). This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1MSPS must be performed
before valid data is available.
Supply and Ground Considerations
The ISL5640 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the ISL5640 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply can be isolated by a ferrite
bead from the digital supply.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
The delay mode can be used to set the Q channel 180
degrees out phase of the I channel if the same clock is
driving both channels. If separate, inverted clocks are used
forthe I and Q channels,this featurecan be used to align the
data.
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ISL5640
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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3-11
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