Datasheet ISL4270E Datasheet (intersil)

Page 1

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ISL4270E

Data Sheet August 2004

QFN Packaged, +/-15kV ESD Protected, +3V to +5.5V, 300nA, 250kbps, RS-232 Transceivers with Enhanced Automatic Powerdown and a Separate Logic Supply

The Intersil ISL4270E is a 3.0V to 5.5V powered RS-232 transceiver which meets ElA/TIA-232 and V.28/V.24 specifications, even at V

±15kV ESD protection (IEC61000-4-2 Air Gap and Human

Body Model) on transmitter outputs and receiver inputs (RS-232 pins). Targeted applications are PDAs, Palmtops, and notebook and laptop computers where the low operational, and even lower standby power consumption is critical. Efficient on-chip charge pumps, coupled with manual and enhanced automatic powerdown functions, reduce the standby supply current to a 300nA trickle. Tiny 5mm x 5mm Quad Flat No-Lead (QFN) packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 250kbps are guaranteed at worst case load conditions.

The ISL4270E features a V output levels and input thresholds to values compatible with the V

powering the external logic (e.g., a UART).

This device includes an enhanced automatic powerdown function which powers down the on-chip power-supply and driver circuits. This occurs when all receiver and transmitter inputs detect no signal transitions for a period of 30 seconds. It power back up, automatically, whenever it senses a transition on any transmitter or receiver input.

Table 1 summarizes the features of the ISL4270E, while Application Note AN9863 summarizes the features of each device comprising the 3V RS-232 family.

= 3.0V. Additionally, it provides

pin that adjusts the logic pin

FN6041.1

Features

• Available in Near Chip Scale QFN (5mmx5mm) Package

•V

Supply Pin for Compatibility with Mixed Voltage

Systems

• ESD Protection for RS-232 I/O Pins to

±15kV (IEC61000)

• Manual and Enhanced Automatic Powerdown Features

• Meets EIA/TIA-232 and V.28/V.2 4 Specifications at 3V

• On-Chip Charge Pumps Require Only Four External

0.1µF Capacitors

• Receivers Stay Active in Powerdown

• Very Low Supply Current . . . . . . . . . . . . . . . . . . . . 300µA

• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps

• Wide Power Supply Range. . . . . . . . Single +3V to +5.5V

• Low Supply Current in Powerdown State. . . . . . . . 300nA

• Pb-Free Available (RoHS Compliant)

Applications

• Any System Requiring RS-232 Communication Ports

- Battery Powered, Hand-Held, and Portable Equipment

- Laptop Computers, Notebooks, Palmtops

- Digital Cameras

- PDA’s and PDA Cradles

- Cellular/Mobile Phones

Ordering Information

TEMP.

PART NO.

ISL4270EIR -40 to 85 32 Ld QFN L32.5x5 ISL4270EIRZ

(See Note)

*Add “-T” suffix to part number for tape and reel packaging.

RANGE (oC) PACKAGE

-40 to 85 32 Ld QFN (Pb-free)

PKG. DWG.

L32.5x5

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020C.

TABLE 1. SUMMARY OF FEATURES

PART

NUMBER

ISL4270E 3 3 250 NO YES YES YES

NO. OF

Tx.

NO. OF

Rx.

DATA RATE

(kbps)

Rx. ENABLE FUNCTION?

1-888-INTERSIL or 321-724-7143

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

LOGIC

SUPPLY PIN?

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

MANUAL

POWER- DOWN?

ENHANCED AUTOMATIC

POWERDOWN FUNCTION?

Page 2

Pinout

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ISL4270E

ISL4270E (QFN)

TOP VIEW

FORCEOFF

GND

2728293031 252632

OUT

C2+

C2-

INVALID

C1-

V+

V-

C1+

11 12 13 14 159 10

OUTR2OUT

FORCEON

Pin Descriptions

PIN FUNCTION

V+ Internally generated positive transmitter supply (+5.5V).

V- Internally generated negative transmitter supply (-5.5V).

GND Ground connection.

C1+ External capacitor (voltage doubler) is connected to this lead.

C1- External capacitor (voltage doubler) is connected to this lead.

C2+ External capacitor (voltage inverter) is connected to this lead.

C2- External capacitor (voltage inverter) is connected to this lead. T

OUT

INVALID Active low output that indicates if no valid RS-232 levels are present on any receiver input. Swings between GND and VL.

FORCEOFF

FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active (FORCEOFF

System power supply input (3.0V to 5.5V).

TTL/CMOS compatible transmit ter I nput s . The switching point is a function of the VL voltage.

±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs. ±15kV ESD Protected, RS-232 compatible receiver in puts.

TTL/CMOS level receiver outputs. Swings between GND and VL. Logic-Level Supply. All TTL/CMOS inputs and outputs are powered by this supply.

Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2). The switching point is a function of the V

voltage.

must be high). The

switching point is a function of the V

voltage.

Page 3

Typical Operating Circuit

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ISL4270E

TTL/CMOS

LOGIC LEVELS

+3.3V

0.1µF

OUT

0.1µF

C1+

C1-

C2+

C2-

V+

V-

5kΩ

0.1µF

OUT

RS-232 LEVELS

LOGIC V

0.1µF

TO POWER

CONTROL LOGIC

FORCEON

FORCEOFF

INVALID

GND

Page 4

ISL4270E

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Absolute Maximum Ratings Thermal Information

VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V

to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V

Input Voltages

, FORCEON, FORCEOFF . . . . . . . . . . . . . . . . . . -0.3V to 6V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V

Output Voltages

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V

OUT

, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VL +0.3V)

OUT

Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous

OUT

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379, and Tech Brief TB389.

Thermal Resistance (Typical, Note 1)

32 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 32

Moisture Sensitivity (see Technical Brief TB363)

QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1

Maximum Junction Temperature (Plastic Package) . . . . . . . 150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300

(oC/W)

C to 150oC

Operating Conditions

Temperature Range

ISL4270EIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40

C to 85oC

Electrical Specifications Test Conditions: V

Typicals are at T

PARAMETER TEST CONDITIONS

DC CHARACTERISTICS

Supply Current, Automatic Powerdown

Supply Current, Powerdown FORCEOFF Supply Current,

Automatic Powerdown Disabled

LOGIC AND TRANSMITTER INPUTS

Input Logic Threshold Low T

Input Logic Threshold High T

Transmitter Input Hysteresis 25 - 0.5 - V Input Leakage Current T

RECEIVER OUTPUTS

Output Voltage Low I Output Voltage High I

RECEIVER INPUTS

Input Voltage Range Full -25 - 25 V Input Threshold Low V

Input Threshold High V

Input Hysteresis 25 - 0.5 - V Input Resistance 25357kΩ

All R

Open, FORCEON = GND, FORCEOFF =V

All Outputs Unloaded, FORCEON = FORCEOFF

= 3.15V

, FORCEON, FORCEOFF VL = 3.3V or 5V Full - - 0.8 V

, FORCEON, FORCEOFF VL = 5V Full 2.4 - - V

, FORCEON, FORCEOFF Full - ±0.01 ±1.0 µA

= 1.6mA Full - - 0.4 V

OUT

= -1.0mA Full VL - 0.6 VL - 0.1 - V

OUT

= VL = 5.0V 25 0.8 1.5 - V

= VL = 3.3V 25 0.6 1.2 - V

= VL = 5.0V 25 - 1.8 2.4 V

= VL = 3.3V 25 - 1.5 2.4 V

= 3V to 5.5V, C1 - C4 = 0.1µF, VL = VCC; Unless Otherwise Specified.

= 25oC, VCC = VL = 3.3V

TEMP

C) MIN TYP MAX UNITS

(

=GND 25 - 0.3 5 µA

=VCC,

= 2.5V Full - - 0.6 V

= 3.3V Full 2.0 - - V

= 2.5V Full 1.4 - - V

= 1.8V 25 - 0.9 - V

25 - 0.3 5 µA

25 - 0.3 1 mA

Page 5

ISL4270E

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Electrical Specifications Test Conditions: V

Typicals are at T

PARAMETER TEST CONDITIONS

TRANSMITTER OUTPUTS

Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V Output Resistance V Output Short-Circuit Current V Output Leakage Current V

ENHANCED AUTOMATIC POWERDOWN (FORCEON = GND, FORCEOFF Receiver Input Thresholds to

INVALID Receiver Input Thresholds to

INVALID INVALID INVALID Receiver Positive or Negative

Threshold to INVALID (t

Receiver Positive or Negative Threshold to INVALID (t

Receiver or Transmitter Edge to Transmitters Enabled Delay (t

Receiver or Transmitter Edge to Transmitters Disabled Delay (t

TIMING CHARACTERISTICS

Maximum Data Rate R Receiver Propagation Delay Receiver Input to Receiver

Time to Exit Powerdown T Transmitter Skew t Receiver Skew t Transition Region Slew Rate V

ESD PERFORMANCE

RS-232 Pins (T

NOTES:

High

Low Output Voltage Low I Output Voltage High I

High Delay

)

INVH

Low Delay

)

INVL

AUTOPWDN

2. An “edge” is defined as a transition through the transmitter or receiver input thresholds.

)

, RIN) Human Body Model 25 - ±15 - kV

OUT

= V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω

= 0V Full - ±35 ±60 mA

OUT

= ±12V, VCC= 0V or 3V to 5.5V

OUT

Automatic Powerdown or FORCEOFF

See F i g u re 4 Full -2.7 - 2.7 V

See Figure 4 Full -0.3 - 0.3 V

= 1.6mA Full - - 0.4 V

OUT

= -1.0mA Full VL - 0.6 - - V

OUT

See Figure 7 25 - 1 - µs

See Figure 7 25 - 30 - µs

Note 2, See Figure 7 25 - 100 - µs

)

Note 2, See Figure 7 Full 15 30 60 sec

=3kΩ, CL= 1000pF, One Transmitter Switching Full 250 500 - kbps

Output, C

| V

X PHL PHL

Measured From 3V to -3V or -3V to 3V

IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV IEC61000-4-2 Contact Discharge 25 - ±8-kV

= 150pF

| ≥ 3.7V 25 - 100 - µs

OUT

- t

PLH

- t

PLH

=3.3V,

=3kΩ to 7kΩ,

= 3V to 5.5V, C1 - C4 = 0.1µF, VL = VCC; Unless Otherwise Specified.

= 25oC, VCC = VL = 3.3V (Continued)

TEMP

(

C) MIN TYP MAX UNITS

Full - - ±25 µA

=GND

= VCC)

PHL

PLH

= 150pF to 1000pF 25 6 18 30 V/µs

= 150pF to 2500pF 25 4 13 30 V/µs

25 - 0.15 - µs 25 - 0.15 - µs

25 - 100 - ns 25 - 50 - ns

Page 6

ISL4270E

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Detailed Description

The ISL4270E operates from a single +3V to +5.5V supply, guarantees a 250kbps minimum data rate, requires only four small external 0.1µF capacitors, features low power consumption, and meets all ElA RS-232C and V.28 specifications. The circuit is divided into three sections: The charge pump, the transmitters, and the receivers.

Charge-Pump

Intersil’s new ISL4270E utilizes regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to generate ±5.5V transmitter supplies from a V low as 3.0V. This allows these devices to maintain RS-232 compliant output levels over the ±10% tolerance range of

3.3V powered systems. The efficient on-chip power supplies require only four small, external 0.1µF capacitors for the voltage doubler and inverter functions over the full V range; other capacitor combinations can be used as shown in Table 3. The charge pumps operate discontinuously (i.e., they turn off as soon as the V+ and V- supplies are pumped up to the nominal values), resulting in significant power savings.

Transmitters

The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-232 output levels. Coupled with the on-chip ±5.5V supplies, these transmitters deliver true RS-232 levels over a wide range of single supply system voltages.

All transmitter outputs disable and assume a high impedance state when the device enters the powerdown mode (see Table 2). These outputs may be driven to ±12V when disabled.

All devices guarantee a 250kbps data rate for full load conditions (3kΩ and 1000pF), V

≥ 3.0V, with one

transmitter operating at full speed. Under more typical conditions of V

≥ 3.3V, RL=3kΩ, and CL= 250pF, one

transmitter easily operates at 1.25Mbps. The transmitter input threshold is set by the voltage applied

to the V

supply pin. Transmitter inputs float if left

unconnected (there are no pull-up resistors), and may cause I

increases. Connect unused inputs to GND for the best

performance.

Receivers

The ISL4270E contains standard inverting receivers that convert RS-232 signals to CMOS output levels and accept inputs up to ±25V while presenting the required 3kΩ to 7kΩ input impedance (see Figure 1) even if the power is off (V

= 0V). The receivers’ Schmitt trigger input stage uses

hysteresis to increase noise immunity and decrease errors due to slow input signal transitions. Receiver outputs swing

supply as

from GND to V

, and do not tristate in powerdown (see

Table 2).

XIN

-25V ≤ V

≤ +25V

RIN

GND

FIGURE 1. RECEIVER CONNECTIONS

5kΩ

XOUT

GND ≤ V

ROUT

≤ V

Low Power Operation

This 3V device requires a nominal supply current of 0.3mA, even at V

= 5.5V, during normal operation (not in

powerdown mode). This is considerably less than the 11mA current required by comparable 5V RS-232 devices, allowing users to reduce system power simply by replacing the old style device with the ISL4270E in new designs.

Po werdown Functionality

The already low current requirement drops significantly when the device enters powerdown mode. In powerdown, supply current drops to 1µA, because the on-chip charge pump turns off (V+ collapses to V and the transmitter outputs tristate. This micro-power mode makes these devices ideal for battery powered and portable applications.

Software Controlled (Manual) Powerdown

This device allows the user to force the IC into the low pow er , standby state, and utilizes a two pin approach where the FORCEON and FORCEOFF mode. For always enabled operation, FORCEON and FORCEOFF active and powerdown modes, under logic or software control, only the FORCEOFF FORCEON state isn’t critical, as FORCEOFF over FORCEON. Nev ertheless, if strictly manual control over powerdown is desired, the user must strap FORCEON high to disable the enhanced automatic powerdown circuitry.

Connecting FORCEOFF the enhanced automatic powerdown feature, enabling them to function as a manual SHUTDOWN

With any of the above control schemes, the time required to exit powerdown, and resume transmission is only 100µs.

When using both manual and enhanced automatic powerdown (FORCEON = 0), the ISL4270E won’t power up from manual powerdown until both FORCEOFF FORCEON are driven high, or until a transition occurs on a receiver or transmitter input. Figure 3 illustrates a circuit for ensuring that the ISL4270E powers up as soon as FORCEOFF Powerdown signal forces the device to power up, and the ISL4270E returns to enhanced automatic powerdown

are both strapped high. To switch between

and FORCEON together disables

switches high. The rising edge of the Master

, V- collapses to GND),

inputs determine the IC’s

input need be driven. The

dominates

input (see Figure 2).

and

Page 7

ISL4270E

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TABLE 2. POWERDOWN LOGIC TRUTH TABLE

RCVR OR XMTR

EDGE WITHIN 30

SEC?

NO H H Active Active NO L Normal Operation (Enhanced

NO H H Active Active YES H YES H L Active Active NO L Normal Operation (Enhanced YES H L Active Active YES H

NO H L High-Z Active NO L Powerdown Due to Enhanced

NO H L High-Z Active YES H

X L X High-Z Active NO L Manual Powerdown X L X High-Z Active YES H

INVALID

NOTES:

3. Input is connected to INVALID

DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN) X NOTE 3 NOTE 3 Active Active YES H Normal Operation X NOTE 3 NOTE 3 High-Z Active NO L Forced Auto Powerdown

FORCEOFF

INPUT

FORCEON

INPUT

Output.

TRANSMITTER

OUTPUTS

RECEIVER

OUTPUTS

RS-232 LEVEL

PRESENT AT

RECEIVER INPUT?

INVALID

OUTPUT MODE OF OPERATION

Auto Powerdown Disabled)

Auto Powerdown Enabled)

Auto Powerdown Logic

FORCEOFF

PWR MGT

LOGIC

CPU

FIGURE 2. CONNECTIONS FOR MANUAL POWERDOWN

INVALID

I/O CHIP POWER SUPPLY

I/O

UART

, FORCEON

ISL4270E

mode an RC time constant after this rising edge. The time constant isn’t critical, because the ISL4270E remains powered up for 30 seconds after the FORCEON falling edge, even if there are no signal transitions. This gives slow-towake systems (e.g., a mouse) plenty of time to start transmitting, and as long as it starts transmitting within 30 seconds both systems remain enabled.

POWER

MANAGEMENT

UNIT

FIGURE 3. CIRCUIT TO ENSURE IMMEDIA TE PO WER UP

WHEN EXITING FORCED POWERDOWN

MASTER POWERDOWN LINE

0.1µF

FORCEOFF FORCEON

ISL4270E

1MΩ

VL Logic Supply Input

Unlike other RS-232 interface devices where the CMOS outputs swing between 0 and V separate logic supply input (V V

) that sets VOH for the receiver and INVALID outputs.

Connecting V

to a host logic supply lower than VCC,

prevents the ISL4270E outputs from forward biasing the input diodes of a logic device powered by that lower supply. Connecting V

to a logic supply greater than VCC ensures

that the receiver and INVALID even with the CMOS input V devices. Note that the V with V

= 5V and VCC= 3.3V (see Figure 16). VL also

supply current increases to 100µA

powers the transmitter and logic inputs, thereby setting their switching thresholds to levels compatible with the logic supply. This separate logic supply pin allows a great deal of flexibility in interfacing to systems with different logic supplies. If logic translation isn’t required, connect V ISL4270E V

INVALID Output

The INVALID output always indicates (see Table 2) whether or not 30µs have elapsed with invalid RS-232 signals (see

, the ISL4270E features a

; 1.8V to 5V, regardless of

output levels are compatible

of AC, HC, and CD4000

to the

Page 8

ISL4270E

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Figures 4 and 7) persisting on all of the receiver inputs, giving the user an easy way to determine when the interface block should power down. Invalid receiver levels occur whenever the driving peripheral’s outputs are shut off (powered down) or when the RS-232 interface cable is disconnected. In the case of a disconnected interface cable where all the receiver inpu ts are fl oa ti n g (but pulled to GND by the internal receiver pull down resistors), the INVALID logic detects the invalid levels and drives the output low . The power management logic then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the receiver inputs, INVALID

switches high, and the power management logic wakes up the interface block. INVALID

can also be used to indicate the DTR or RING INDICATOR signal, as long as the other receiver inputs are floating, or driven to GND (as in the case of a powered down driver).

INVALID level on a receiver input. INVALID

switches high 1µs after detecting a valid RS-232

operates in all modes (forced or automatic powerdown, or forced on), so it is also useful for systems employing manual powerdown circuitry.

2.7V

0.3V

-0.3V

-2.7V

FIGURE 4. DEFINITION OF VALID RS-232 RECEIVER LEVELS

VALID RS-232 LEVEL - INVALID

INDETERMINATE

INVALID LEVEL - INVALID

INDETERMINATE

VALID RS-232 LEVEL - INVALID

= 0

= 1

Figure 5 illustrates the enhanced powerdown control logic. Note that once the ISL4270E enters powerdown (manually or automatically), the 30 second timer remains timed out (set), keeping the ISL4270E powered down until FORCEON transitions high, or until a transition occurs on a receiver or transmitter input.

As stated previously, the INVALID

output switches low whenever invalid levels have persisted on all of the receiver inputs for more than 30µs (see Figure 7), but this has no direct effect on the state of the ISL4270E (see the next sections for methods of utilizing INVALID

to power down the

device). The time to recover from automatic powerdown mode is

typically 100µs.

FORCEOFF

T_IN

R_IN

FIGURE 5. ENHANCED AUTOMATIC POWERDOWN LOGIC

EDGE

DETECT

EDGE

DETECT

FORCEON

30s

TIMER

AUTOPWDN

Emulating Standard Automatic Powerdown

If enhanced automatic powerdown isn’t desired, the user can implement the standard automatic powerdown feature (mimics the function on the ICL3221E/23E/43E) by connecting the INVALID FORCEOFF

inputs, as shown in Figure 6. After 30µs of

output to the FORCEON and

Enhanced Automatic Powerdown

Even greater power savings is available by using the enhanced automatic powerdown function. When the enhanced powerdown logic determines that no transitions have occurred on any of the transmitter nor receiver inputs for 30 seconds, the charge pump and transmitters powerdown, thereby reducing supply current to 1µA. The ISL4270E automatically powers back up whenever it detects a transition on one of these inputs. This automatic

CPU

powerdown feature provides additional system power savings without changes to the existing operating system.

Enhanced automatic powerdown operates when the FORCEON input is low, and the FORCEOFF

input is high.

FIGURE 6. CONNECTIONS FOR AUTOMATIC POWERDOWN

Tying FORCEON high disables automatic powerdown, but manual powerdown is always available via the overriding FORCEOFF automatic powerdown functionality.

input. Table 2 summarizes the enhanced

invalid receiver levels, INVALID ISL4270E into a forced powerdown condition. INVALID switches high as soon as a receiver input senses a valid

INVALID

ISL4270E

I/O

UART

WHEN NO VALID RECEIVER SIGNALS ARE PRESENT

FORCEOFF

FORCEON

switches low and drives the

Page 9

ISL4270E

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RECEIVER

INPUTS

TRANSMITTER

INPUTS

TRANSMITTER

OUTPUTS

INVALID

OUTPUT

V+

INVL

V-

FIGURE 7. ENHANCED AUTOMATIC POWERDOWN AND INVALID TIMING DIAGRAMS

INVH

AUTOPWDN

RS-232 level, forcing the ISL4270E to power on. See the “INVALID

DRIVING FORCEON AND FORCEOFF” section of Table 2 for an operational summary. This operational mode is perfect for handheld devices that communicate with another computer via a detachable cable. Detaching the cable allows the internal receiver pull-down resistors to pull the inputs to GND (an invalid RS-232 level), causing the 30µs timer to time-out and drive the IC into powerdown. Reconnecting the cable restores valid levels, causing the IC to power back up.

Hybrid Automatic Powerdown Options

For devices which communicate only through a detachable cable, connecting INVALID

to FORCEOFF (with FORCEON = 0) may be a desirable configuration. While the cable is attached INVALID

and FORCEOFF remain high, so the enhanced automatic powerdown logic powers down the RS-232 device whenever there is 30 seconds of inactivity on the receiver and transmitter inputs. Detaching the cable allows the receiver inputs to drop to an invalid level (GND), so INVALID

switches low and forces the RS-232 device to power down. The ISL4270E remains powered down until the cable is reconnected (INV ALID

= FORCEOFF = 1) and a transition occurs on a receiver or transmitter input (see Figure 5). For immediate power up when the cable is reattached, connect FORCEON to FORCEOFF

through a

network similar to that shown in Figure 3.

Capacitor Selection

The ISL4270E charge pumps require only 0.1µF capacitors for the full operational voltage range. Table 3 lists other acceptable capacitor values for various supply voltage ranges. Do not use values smaller than those listed in Table 3. Increasing the capacitor values (by a factor of 2)

INVALID

}

REGION

AUTOPWDN

reduces ripple on the transmitter outputs and slightly reduces power consumption.

TABLE 3. REQUIRED CAPACITOR VALUES

(V)

3.0 to 3.6 0.1 0.1

4.5 to 5.5 0.047 0.33

3.0 to 5.5 0.22 1

(µF)

, C3, C

(µF)

When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-.

Po wer Supply Decoupling

In most circumstances a 0.1µF bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple V capacitor of the same value as the charge-pump capacitor C

to ground with a

Connect the bypass capacitor as close as possible to the IC.

Transmitter Outputs when Exiting Powerdown

Figure 8 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two transmitter outputs properly go to opposite RS-232 levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with 3kΩ in parallel with 2500pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately 3V.

Page 10

ISL4270E

www.BDTIC.com/Intersil

5V/DIV

2V/DIV

FORCEOFF

VCC = +3.3V C1 - C4 = 0.1µF

TIME (20µs/DIV.)

FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING

POWERDOWN

High Data Rates

The ISL4270E maintains the RS-232 ±5V minimum transmitter output voltages even at high data rates. Figure 9 details a transmitter loopback test circuit, and Figure 10 illustrates the loopback test result at 120kbps. For this test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF, at 120kbps. Figure 11 shows the loopback results for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static transmitters were also loaded with an RS-232 receiver.

0.1µF

5V/DIV.

OUT

5V/DIV.

OUT

VCC = +3.3V C1 - C4 = 0.1µF

5µs/DIV.

FIGURE 10. LOOPBACK TEST AT 120kbps

VCC = +3.3V C1 - C4 = 0.1µF

2µs/DIV.

OUT

V+

V-

1000pF

C1+

C1-

C2+

C2-

OUT

FORCEON

FORCEOFF

ISL4270E

FIGURE 9. TRANSMITTER LOOPBACK TEST CIRCUIT

FIGURE 11. LOOPBACK TEST AT 250kbps

Interconnection with 3V and 5V Logic

Standard 3.3V powered RS-232 devices interface well with 3V and 5V powered TTL compatible logic families (e.g., ACT and HCT), but the logic outputs (e.g., R the V

level of 5V po wered CMOS families like HC, AC, and

CD4000. The ISL4270E V By connecting V

to the same supply (1.8V to 5V) powering

supply pin solves this problem.

) fail to reach

OUTS

the logic device, the ISL4270E logic outputs will swing from GND to the logic V

±15kV ESD Protection

All pins on the 3V interface devices include ESD protection structures, but the ISL4270E incorporates advanced structures which allow the RS-232 pins (transmitter outputs and receiver inputs) to survive ESD events up to ±15kV. The RS-232 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect

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ISL4270E

www.BDTIC.com/Intersil

without allowing any latchup mechanism to activate, and don’t interfere with RS-232 signals as large as ±25V.

Human Body Model (HBM) Testing

As the name implies, this test method emulates the ESD event delivered to an IC during human handling. The tester delivers the charge through a 1.5kΩ current limiting resistor, making the test less severe than the IEC61000 test which utilizes a 330Ω limiting resistor. The HBM method determines an ICs ability to withstand the ESD transients typically present during handling and manufacturing. Due to the random nature of these events, each pin is tested with respect to all other pins. The RS-232 pins on “E” family devices can withstand HBM ESD events to ±15kV.

IEC61000-4-2 Testing

The IEC61000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD ev ent are those that are e xposed to the outside world (the RS-232 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting

Typical Performance Curves V

6.0

4.0

= VL = 3.3V, TA = 25oC

OUT

resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The e xtra ESD protection built into this device’s RS-232 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-232 port.

AIR-GAP DISCHARGE TEST METHOD

For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The “E” device RS-232 pins withstand ±15kV air-gap discharges.

CONTACT DISCHARGE TEST METHOD

During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing de vices at voltages higher than ±8kV. All “E” family devices survive ±8kV contact discharges on the RS-232 pins.

2.0 1 TRANSMITTER AT 250kbps OTHER TRANSMITTERS AT 30kbps

-2.0

-4.0

TRANSMITTER OUTPUT VOLTAGE (V)

-6.0

FIGURE 12. TRANSMITTER OUTPUT VOL TAGE vs LO AD

1000 2000 3000 4000 50000

LOAD CAPACITANCE (pF)

CAPACITANCE

OUT

SLEW RATE (V/µs)

0 1000 2000 3000 4000 5000

FIGURE 13. SLEW RATE vs LOAD CAPACITANCE

+SLEW

-SLEW

LOAD CAPACITANCE (pF)

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ISL4270E

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Typical Performance Curves V

SUPPLY CURRENT (mA)

1000

2000

LOAD CAPACITANCE (pF)

250kbps

3000

= VL = 3.3V, TA = 25oC (Continued)

120kbps

20kbps

4000

FIGURE 14. SUPPL Y CURRENT vs LOAD CAPACIT ANCE

WHEN TRANSMITTING DATA

10m

NO LOAD ALL OUTPUTS STATIC

= 3.3V

100µ

5000

3.5

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V)

NO LOAD ALL OUTPUTS STATIC

FIGURE 15. SUPPLY CURRENT vs SUPPLY VOLTAGE

10µ

(A)

1µ

100n

10n

FIGURE 16. V

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP)

GND

TRANSISTOR COUNT

ISL4270E: 1063

PROCESS

Si Gate CMOS

VL ≤ V

CCVL

2.0 3.0 3.5 4.0 4.5 5.0 5.5 6.02.5 6.5 7.0

> V

VL (V)

SUPPLY CURRENT vs VL VOLTAGE

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ISL4270E

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Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)

L32.5x5

32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 A1 - - 0.05 A2 - - 1.00 9 A3 0.20 REF 9

b 0.18 0.23 0.30 5,8

D 5.00 BSC -

D1 4.75 BSC 9 D2 2.95 3.10 3.25 7,8

E 5.00 BSC E1 4.75 BSC 9 E2 2.95 3.10 3.25 7,8

e 0.50 BSC -

k0.25 - - -

L 0.30 0.40 0.50 8 L1 - - 0.15 10

N322

Nd 8 3 Ne 8 8 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation.

10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.

NOTESMIN NOMINAL MAX

Rev. 1 10/02

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted b y implica tion or ot herw ise un der any patent or patent rights of Intersil or its subsidiaries.

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