Page 1
®
www.BDTIC.com/Intersil
ISL4260E
Data Sheet August 2004
QFN Packaged, ±15kV ESD Protected, +3V
to +5.5V, 150nA, 250kbps, RS-232
Transmitters/Receivers with Separate
Logic Supply
The ISL4260E contains 3.0V to 5.5V powered RS-232
transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at V
applications are PDAs, Palmtops , and cell phones where the
low operational, and even lower standb y, power consumption
is critical. Efficient on-chip charge pumps, coupled with a
manual powerdown function reduces the standby supply
current to a 150nA trickle. Tiny 5mm x 5mm Quad Flat No-
Lead (QFN) packaging, and the use of small, low value
capacitors ensure board space savings as well. Data rates
greater than 250kbps are guaranteed at worst case load
conditions.
The ISL4260E features a V
pin that adjusts the logic pin
L
(see Pin Descriptions table) output levels and input
thresholds to values compatible with the V
external logic (e.g., a UART).
The single pin powerdown function (SHDN
the receiver and transmitter outputs, while shutting down the
charge pump to minimize supply current drain.
Table 1 summarizes the features of the ISL4260E, while
Application Note AN9863 summarizes the features of each
device comprising the 3V RS-232 family.
= 3.0V. Targeted
CC
powering the
CC
= 0) disables all
FN6035.1
Features
• Available in Near Chip Scale QFN (5mmx5mm) Package
•V
Pin for Compatibility with Mixed Voltage Systems
L
• ESD Protection for RS-232 I/O Pins to
• Single SHDN
Pin Disables Transmitters and Receivers
±15kV (IEC61000)
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• On-Chip Charge Pumps Require Only Four External
0.1µF Capacitors
• Receiver Hysteresis For Improved Noise Immunity
• Very Low Supply Current . . . . . . . . . . . . . . . . . . . . 300µA
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Wide Power Supply Range. . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . .150nA
• Pb-free available
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Digital Cameras
- PDAs and PDA Cradles
- Cellular/Mobile Phones
Ordering Information
PART
NUMBER
ISL4260EIR -40 to 85 32 Lead QFN L32.5x5
ISL4260EIRZ
(See Note)
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
PART
NUMBER
ISL4260E 3 2 250 NO YES YES NO
TEMP.
o
RANGE (
-40 to 85 32 Lead QFN
NO. OF
C) PACKAGE PKG. NO.
(Pb-free)
NO. OF
Tx.
DATA RATE
Rx.
1
(kbps)
L32.5x5
TABLE 1. SUMMARY OF FEATURES
Rx. ENABLE
FUNCTION?
1-888-INTERSIL or 321-724-7143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
LOGIC
V
L
SUPPLY PIN?
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
MANUAL
POWER- DOWN?
Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved
POWERDOWN FUNCTION?
AUTOMATIC
Page 2
Pinout
www.BDTIC.com/Intersil
ISL4260E
ISL4260E (QFN)
TOP VIEW
NC
C1-
V+
C1+
NC
1
C2+
2
C2-
3
V-
4
T1
5
IN
T2
6
IN
NC
7
NC
8
11 12 13 14 159 10
IN
NC
T3
NC
OUTR1OUT
R2
Pin Descriptions
PIN FUNCTION
V
CC
V+ Internally generated positive transmitter supply (+5.5V).
V- Internally generated negative transmitter supply (-5.5V).
GND Ground connection.
C1+ External capacitor (voltage doubler) is connected to this lead.
C1- External capacitor (voltage doubler) is connected to this lead.
C2+ External capacitor (voltage inverter) is connected to this lead.
C2- External capacitor (voltage inverter) is connected to this lead.
T
T
OUT
R
R
OUT
V
SHDN
NC No Connection
System power supply input (3.0V to 5.5V).
TTL/CMOS compatible transmit ter I nput s . The switching point is a function of the VL voltage.
IN
±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs.
±15kV ESD Protected, RS-232 compatible receiver in puts.
IN
TTL/CMOS level receiver outputs. Swings between GND and VL.
Logic-Level Supply. All TTL/CMOS inputs and outputs are powered by this supply.
L
Active low TTL/C MOS input to tri-state receiver and tr ansmitter outputs and to shut down the on-board power supply to place de vice
in low power mode. The switching point is a function of the V
SHDN
voltage.
L
CC
V
2728293031 252632
NC
GND
L
V
NC
NC
24
T1
OUT
23
T2
OUT
22
T3
OUT
21
NC
20
R1
IN
19
R2
IN
18
NC
17
16
NC
2
Page 3
Typical Operating Circuit
www.BDTIC.com/Intersil
ISL4260E
+3.3V to +5V
TTL/CMOS
LOGIC LEVELS
LOGIC V
C
0.1µF
C
0.1µF
T1
T2
T3
R1
OUT
R2
OUT
CC
0.1µF
+
0.1µF
29
1
2
IN
IN
IN
C1+
+
31
C1-
2
C2+
+
3
C2-
5
6
10
13
12
V
15
L
+
V
CC
R
R
GND
27
30
C
3
V+
V-
T
1
T
2
T
3
1
5kΩ
2
5kΩ
SHDN
26
+
0.1µF
4
C
4
0.1µF
+
23
T1
OUT
22
T2
OUT
OUT
IN
IN
RS-232
LEVELS
21
T3
19
R1
18
R2
28
V
CC
3
Page 4
ISL4260E
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V
L
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
, SHDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
T
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
R
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
T
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VL +0.3V)
R
OUT
Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
T
OUT
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
1. θ
JA
Tech Brief TB379, and Tech Brief TB389.
Thermal Resistance (Typical, Note 1)
32 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 32
Moisture Sensitivity (see Technical Brief TB363)
QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Junction Temperature (Plastic Package) . . . . . . . 150
Maximum Storage Temperature Range. . . . . . . . . . -65
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
Operating Conditions
Temperature Range
ISL4260EIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
θ
(oC/W)
JA
o
C to 150oC
o
C to 85oC
o
o
C
C
Electrical Specifications Test Conditions: V
Typicals are at T
PARAMETER TEST CONDITIONS
DC CHARACTERISTICS
Supply Current, Powerdown SHDN
Supply Current All Outputs Unloaded, SHDN
LOGIC AND TRANSMITTER INPUTS
Input Logic Threshold Low T
Input Logic Threshold High TIN, SHDN VL = 5V Full 2.4 - - V
Transmitter Input Hysteresis 25 - 0.5 - V
Input Leakage Current T
RECEIVER OUTPUTS
Output Leakage Current V
Output Voltage Low I
Output Voltage High I
RECEIVER INPUTS
Input Voltage Range Full -25 - 25 V
Input Threshold Low V
Input Threshold High V
Input Hysteresis 25 - 0.5 - V
Input Resistance 25 3 5 7 kΩ
= GND, All Inputs at VCC or GND 25 - 0.15 1 µA
, SHDN VL = 3.3V or 5V Full - - 0.8 V
IN
, SHDN Full - ±0.01 ±1 µA
IN
= 0V or 3V to 5.5V, SHDN =GND Full - ±0.05 ±10 µA
CC
= 1.6mA Full - - 0.4 V
OUT
= -1.0mA Full VL - 0.6 VL - 0.1 - V
OUT
= 5.0V 25 0.8 1.5 - V
L
= 3.3V 25 0.6 1.2 - V
V
L
= 5.0V 25 - 1.8 2.4 V
L
= 3.3V 25 - 1.5 2.4 V
V
L
= 3V to 5.5V, C1 - C4 = 0.1µF, VL = VCC; Unless Otherwise Specified.
CC
= 25oC, VCC = VL = 3.3V
A
TEMP
o
C) MIN TYP MAX UNITS
(
=VCC, VCC = 3.15V 25 - 0.3 1 mA
= 2.5V Full - - 0.6 V
V
L
= 3.3V Full 2.0 - - V
V
L
= 2.5V Full 1.4 - - V
V
L
= 1.8V 25 - 0.9 - V
V
L
4
Page 5
ISL4260E
www.BDTIC.com/Intersil
Electrical Specifications Test Conditions: V
Typicals are at T
PARAMETER TEST CONDITIONS
TRANSMITTER OUTPUTS
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V
Output Resistance V
Output Short-Circuit Current Shorted to GND Full - - ±60 mA
Output Leakage Current V
TIMING CHARACTERISTICS
Maximum Data Rate R
Receiver Propagation Delay Receiver Input to Receiver
Receiver Output Enable Time 25 - 200 - ns
Receiver Output Disable Time 25 - 200 - ns
Transmitter Output Enable Time From SHDN
Transmitter Skew t
Receiver Skew t
Transition Region Slew Rate R
ESD PERFORMANCE
RS-232 Pins (T
NOTE:
2. Transmitter skew is measured at the transmitter zero crossing points.
, RIN) Human Body Model 25 - ±15 - kV
OUT
= V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω
CC
= ±12V, VCC= 0V or 3V to 5.5V, SHDN =GND Full - - ±25 µA
OUT
=3kΩ, CL= 1000pF, One Transmitter Switching Full 250 500 - kbps
L
Output, C
PHL
PHL
L
Measured From 3V to -3V or
-3V to 3V, V
IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV
IEC61000-4-2 Contact Discharge 25 - ±8-kV
= 150pF
L
- t
PLH
- t
PLH
=3kΩ to 7kΩ,
= 3V to 5.5V, C1 - C4 = 0.1µF, VL = VCC; Unless Otherwise Specified.
CC
= 25oC, VCC = VL = 3.3V (Continued)
A
TEMP
o
(
C) MIN TYP MAX UNITS
t
PHL
t
PLH
Rising Edge to T
(Note 2) 25 - 100 - ns
= 3.3V
CC
= ±3.7V 25 - 100 - µs
OUT
= 150pF to 1000pF 25 6 18 30 V/µs
C
L
= 150pF to 2500pF 25 4 13 30 V/µs
C
L
25 - 0.15 - µs
25 - 0.15 - µs
25 - 50 - ns
Detailed Description
The ISL4260E operates from a single +3V to +5.5V supply,
guarantees a 250kbps minimum data rate, requires only four
small external 0.1µF capacitors, features low power
consumption, and meets all ElA RS-232C and V.28
specifications. The circuit is divided into three sections: The
charge pump, the transmitters, and the receivers.
Charge-Pump
Intersil’s new ISL4260E utilizes regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a V
low as 3.0V. This allows these devices to maintain RS-232
compliant output levels over the ±10% tolerance range of
3.3V powered systems. The efficient on-chip power supplies
require only four small, external 0.1µF capacitors for the
voltage doubler and inverter functions over the full V
range; other capacitor combinations can be used as shown
in Table 3. The charge pumps operate discontinuously (i.e.,
they turn off as soon as the V+ and V- supplies are pumped
5
supply as
CC
CC
up to the nominal values), resulting in significant power
savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies, thes e
transmitters deliver true RS-232 levels over a wide range of
single supply system voltages.
All transmitter outputs disable and assume a high
impedance state when the device enters the powerdown
mode (see Table 2). These outputs may be driven to ±12V
when disabled.
All devices guarantee a 250kbps data rate for full load
conditions (3kΩ and 1000pF), V
transmitter operating at full speed. Under more typical
conditions of V
≥ 3.3V, RL=3kΩ, and CL= 250pF, one
CC
transmitter easily operates at 1.25Mbps.
The transmitter input threshold is set by the voltage applied
to the V
pin. Transmitter inputs float if left unconnected
L
≥ 3.0V, with one
CC
Page 6
ISL4260E
www.BDTIC.com/Intersil
(there are no pull-up resistors), and may cause I
CC
increases. Connect unused inputs to GND for the best
performance.
TABLE 2. POWERDOWN TRUTH TABLE
SHDN
INPUT
TRANSMITTER
OUTPUTS
L High-Z High-Z Manual Powerdown
H Active Active Normal Operation
RECEIVER
OUTPUTS MODE OF OPERATION
Receivers
The ISL4260E contains standard inverting receivers that
convert RS-232 signals to CMOS output levels and accept
inputs up to ±25V while presenting the required 3kΩ to 7kΩ
input impedance (see Figure 1) even if the power is off
(V
= 0V). The receivers’ Schmitt trigger input stage uses
CC
hysteresis to increase noise immunity and decrease errors
due to slow input signal transitions. Receiver outputs swing
from GND to V
-25V ≤ V
, and tristate in powerdown.
L
V
L
R
XIN
≤ +25V
RIN
GND
FIGURE 1. RECEIVER CONNECTIONS
5kΩ
R
XOUT
GND ≤ V
ROUT
≤ V
L
Low Power Operation
This 3V device requires a nominal supply current of 0.3mA,
even at V
= 5.5V, during normal operation (not in
CC
powerdown mode). This is considerably less than the 11mA
current required by comparable 5V RS-232 devices, allo wing
users to reduce system power simply by replacing the old
style device with the ISL4260E in new designs.
Po werdown Functionality
The already low current requirement drops significantly
when the device ente rs powerdown mode. In powerdown,
supply current drops to 150nA, because the on-chip charge
pump turns off (V+ collapses to V
and the transmitter and receiver outputs tristate. This micropower mode makes these devices ideal for battery powered
and portable applications.
Software Controlled (Manual) Powerdown
The ISL4260E may be forced into its low power, standby
state via a simple shutdown (SHDN
Driving this pin high enables normal operation, while driving
it low forces the IC into its powerdown state. The time
required to exit powerdown, and resume transmission is less
than 100µs. Connect SHDN
function isn’t needed.
to VCC if the powerdown
, V- collapses to GND),
CC
) pin (see Figure 2).
SHDN
PWR
MGT
LOGIC
CPU
FIGURE 2. CONNECTIONS FOR MANUAL POWERDOWN
I/O CHIP
POWER SUPPLY
V
CC
I/O
UART
V
ISL4260E
L
VL Logic Supply Input
Unlike other RS-232 interface devices where the CMOS
outputs swing between 0 and V
separate logic supply input (V
V
) that sets VOH for the receiver outputs. Connecting VL
CC
to a host logic supply lower than V
, the ISL4260E features a
CC
; 1.8V to 5V, regardless of
L
, prevents the
CC
ISL4260E outputs from forward biasing the input diodes of a
logic device powered by that lower supply. Connecting V
a logic supply greater than V
ensures that the receiver
CC
output levels are compatible even with the CMOS input V
of AC, HC, and CD4000 devices. Note that the V
current increases to 100µA with V
(see Figure 11). V
also powers the transmitter and logic
L
= 5V and VCC=3.3V
L
supply
L
to
L
IH
inputs, thereby setting their switching thresholds to levels
compatible with the logic supply. This separate logic supp ly
pin allows a great deal of flexibility in interfacing to systems
with different logic supplies. If logic translation isn’t required,
connect V
to the ISL4260E VCC.
L
Capacitor Selection
The ISL4260E charge pumps only require 0.1µF capacitors
for the full operational voltage range. Table 3 lists other
acceptable capacitor v a l u es for various supply voltage
ranges. Do not use values smaller than those listed in
Table 3. Increasing the capacitor values (by a factor of 2)
reduces ripple on the transmitter outputs and slightly
reduces power consumption.
TABLE 3. REQUIRED CAPACITOR VALUES
V
CC
(V)
3.0 to 3.6 0.1 0.1
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.22 1
C
(µF)
1
C
2
, C3, C
(µF)
4
6
Page 7
ISL4260E
www.BDTIC.com/Intersil
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
Po wer Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple V
capacitor of the same value as the charge-p ump capacitor C
to ground with a
CC
1
Connect the bypass capacitor as close as possible to the IC.
Transmitter Outputs when Exiting
Powerdown
Figure 3 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.
V
CC
0.1µF
+
C
1
+
C
2
.
V
CC
C1+
C1-
C2+
C2-
T
IN
R
OUT
SHDN
+
V
CC
ISL4260E
V
L
T
OUT
V+
V-
R
IN
5k
+
C
3
C
4
+
1000pF
FIGURE 4. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV.
T1
IN
5V/DIV
2V/DIV
SHDN
T1
T2
VCC = +3.3V
C1 - C4 = 0.1µF
TIME (20µs/DIV.)
FIGURE 3. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
High Data Rates
The ISL4260E maintains the RS-232 ±5V minimum
transmitter output voltages even at high data rates. Figure 4
details a transmitter loopback test circuit, and Figure 5
illustrates the loopback test result at 120kbps. For this test,
all transmitters were simultaneously driving RS-232 loads in
parallel with 1000pF, at 120kbps. Figure 6 shows the
loopback results for a single transmitter driving 1000pF and
an RS-232 load at 250kbps. The static transmitters were
also loaded with an RS-232 receiver.
T1
OUT
R1
OUT
5V/DIV.
T1
T1
OUT
R1
OUT
VCC = +3.3V
C1 - C4 = 0.1µF
5µs/DIV.
FIGURE 5. LOOPBACK TEST AT 120kbps
IN
VCC = +3.3V
C1 - C4 = 0.1µF
2µs/DIV.
FIGURE 6. LOOPBACK TEST AT 250kbps
7
Page 8
ISL4260E
www.BDTIC.com/Intersil
Interconnection with 3V and 5V Logic
Standard 3.3V powered RS-232 devices interface well with
3V and 5V powered TTL compatible logic families (e.g., ACT
and HCT), but the logic outputs (e.g., R
the V
level of 5V pow ered CMOS families like HC, AC, and
IH
CD4000. The ISL4260E V
By connecting V
to the same supply (1.8V to 5V) powering
L
supply pin solves this problem.
L
) fail to reach
OUTS
the logic device, the ISL4260E logic outputs will swing from
GND to the logic V
CC
.
±15kV ESD Protection
All pins on the 3V interface devices include ESD protection
structures, but the ISL4260E incorporates advanced
structures which allow the RS-232 pins (transmitter outputs
and receiver inputs) to survive ESD events up to ±15kV. The
RS-232 pins are particularly vulnerable to ESD damage
because they typically connect to an exposed port on the
exterior of the finished product. Simply touching the port
pins, or connecting a cable, can cause an ESD event that
might destroy unprotected ICs. These ne w ESD structures
protect the device whether or not it is powered up, protect
without allowing any latchup mechanism to activate, and
don’t interfere with RS-232 signals as large as ±25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5kΩ current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device’s RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing de vices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
Typical Performance Curves V
6.0
4.0
2.0
1 TRANSMITTER AT 250kbps
OTHER TRANSMITTERS AT 30kbps
0
-2.0
-4.0
TRANSMITTER OUTPUT VOLTAGE (V)
-6.0
FIGURE 7. TRANSMITTER OUTPUT VOL TAGE vs LOAD
1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
CAPACITANCE
= 3.3V, TA = 25oC
CC
8
V
V
OUT
OUT
30
+
25
20
15
SLEW RATE (V/µs)
-
10
5
0 1000 2000 3000 4000 5000
FIGURE 8. SLEW RATE vs LOAD CAPACITANCE
+SLEW
-SLEW
LOAD CAPACITANCE (pF)
Page 9
ISL4260E
www.BDTIC.com/Intersil
Typical Performance Curves V
45
40
250kbps
35
30
25
20
SUPPLY CURRENT (mA)
15
10
0
1000
2000
LOAD CAPACITANCE (pF)
3000
= 3.3V, TA = 25oC (Continued)
CC
120kbps
20kbps
4000
FIGURE 9. SUPPL Y CURRENT vs LO AD CAPACIT ANCE
WHEN TRANSMITTING DATA
10m
NO LOAD
ALL OUTPUTS STATIC
1m
V
CC
= 3.3V
5000
3.5
3.0
2.5
2.0
1.5
1.0
SUPPLY CURRENT (mA)
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
NO LOAD
ALL OUTPUTS STATIC
FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE
100µ
10µ
(A)
L
I
1µ
100n
10n
1n
FIGURE 11. V
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP)
GND
TRANSISTOR COUNT
422
PROCESS
Si Gate CMOS
VL ≤ V
CCVL
2.0 3.0 3.5 4.0 4.5 5.0 5.5 6.02.5 6.5 7.0
> V
CC
VL (V)
SUPPLY CURRENT vs VL VOLTAGE
L
9
Page 10
ISL4260E
www.BDTIC.com/Intersil
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C
MILLIMETERS
SYMBOL
A 0.80 0.90 1.00 A1 - - 0.05 A2 - - 1.00 9
A3 0.20 REF 9
b 0.18 0.23 0.30 5,8
D 5.00 BSC -
D1 4.75 BSC 9
D2 2.95 3.10 3.25 7,8
E 5.00 BSC E1 4.75 BSC 9
E2 2.95 3.10 3.25 7,8
e 0.50 BSC -
k0.25 - - -
L 0.30 0.40 0.50 8
L1 - - 0.15 10
N322
Nd 8 3
Ne 8 8 3
P- -0.609
θ --129
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
NOTESMIN NOMINAL MAX
Rev. 1 10/02
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted b y implica tion or ot herw ise un der any patent or patent rights of Intersil or its subsidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
Loading...