Datasheet ISL22313 Datasheet (intersil)

Page 1

ISL22313

Single Digitally Controlled Potentiometer (XDCP™)

Data Sheet July 17, 2007

Low Noise, Low Power, I2C® Bus, 256 Taps

The ISL22313 integrates a single digitally controlled potentiometer (DCP), control logic and non-volatile memory on a monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the

C bus interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR control the position of the wiper. At power up the device recalls the contents of the DCP’s IVR to the WR.

The ISL22313 also has 14 general purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information.

The ISL22313 features a dual supply, that is beneficial for applications requiring a bipolar range for DCP terminals between V- and VCC.

The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.

Pinout

ISL22313

(10 LD MSOP)

TOP VIEW

SDA

V-

VCCSCL

GND

FN6421.0

Features

• 256 resistor taps

•I

C serial interface

- Two address pins, up to four devices per bus

• Non-volatile EEPROM storage of wiper position

• 14 General Purpose non-volatile registers

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T≤+55

• Wiper resistance: 70Ω typical @ 1mA

• Standby current <2.5µA max

• Shutdown current <2.5µA max

• Dual power supply

- VCC = 2.25V to 5.5V

- V- = -2.25V to -5.5V

• DCP terminal voltage from V- to VCC

•10kΩ, 50kΩ or 100kΩ total resistance

• Extended industrial temperature range: -40 to +125

• 10 Lead MSOP

• Pb-free plus anneal product (RoHS compliant)

°C

Ordering Information

PART

NUMBER

(Notes 1, 2)

ISL22313TFU10Z 313TZ 100 -40 to +125 10 Ld MSOP M10.118 ISL22313UFU10Z 313UZ 50 -40 to +125 10 Ld MSOP M10.118 ISL22313WFU10Z 313WZ 10 -40 to +125 10 Ld MSOP M10.118

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

PART

MARKING

RESISTANCE

OPTION

(kΩ)

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

TEMP.

RANGE

(°C)

| Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PACKAGE

(Pb-Free) PKG. DWG. #

Page 2

Block Diagram

ISL22313

SCL

SDA

A1 A0

I2C

INTERFACE

POWER UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

NON-VOLATILE

REGISTERS

GND

VOLATILE

AND

WIPER

CONTROL

CIRCUITRY

Pin Descriptions

MSOP PIN SYMBOL DESCRIPTION

1 SCL Open drain I2C interface clock input 2 SDA Open drain Serial data I/O for the I 3 A1 Device address input for the I 4 A0 Device address input for the I2C interface 5 V- Negative supply pin 6 GND Device ground pin 7 RL “Low” terminal of DCP 8 RW “Wiper” terminal of DCP 9 RH “High” terminal of DCP

10 VCC Power supply pin

C interface

V-

C interface

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Page 3

ISL22313

Absolute Maximum Ratings Thermal Information

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-6V to 0.3V

+0.3

Voltage at any DCP Pin with

respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V

IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A at +125°C

ESD

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTE:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. θ

Analog Specifications Over recommended operating conditions unless otherwise stated. Limits are established by characterization.

Thermal Resistance (Typical, Note 3) θ

(°C/W)

10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature Range (Full Industrial) . . . . . . . . . . . .-40°C to +125°C

Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V

V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.25V to -5.5V

Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

SYMBOL PARAMETER TEST CONDITIONS

TOTAL

RH to RL resistance W option 10 kΩ

U option 50 kΩ

T option 100 kΩ RH to RL resistance tolerance -20 +20 % End-to-End Temperature Coefficient W option ±150 ppm/°C

U, T option ±50 ppm/°C

, V

H/CL/CW

DCP terminal voltage VRH and VRL to GND V- V

Wiper resistance RH - floating, VRL = V-, force IW current to

the wiper, I

= (VCC - VRL)/R

Potentiometer capacitance See Macro Model below. 10/10/25 pF

(Note 16)

LkgDCP

VOLTAGE DIVIDER MODE (V- @ RL; V

INL

Leakage on DCP pins Voltage at pin from GND to V

@ RH; measured at RW, unloaded)

Integral non-linearity W option -1.5 ±0.5 1.5 LSB

(Note 9)

U, T option -1.0 ±0.2 1.0

DNL

Differential non-linearity W option -1.0 ±0.4 1.0 LSB

(Note 8)

U, T option -0.5 ±0.15 0.5

ZSerror (Note 6)

FSerror (Note 7)

(Notes 10, 16)

Zero-scale error W option 0 1 5 LSB

U, T option 0 0.5 2 Full-scale error W option -5 -1 0 LSB

U, T option -2 -1 0 Ratiometric temperature coefficient DCP register set to 80 hex ±4 ppm/°C

TOTAL

MIN

(Note 18)

TYP

(Note 4)

MAX

(Note 18) UNIT

70 250 Ω

0.1 1 µA

(Note 5)

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ISL22313

Analog Specifications Over recommended operating conditions unless otherwise stated. Limits are established by characterization.

(Continued)

MIN

SYMBOL PARAMETER TEST CONDITIONS

cutoff

(Note 16)

-3dB cut off frequency Wiper at midpoint (80hex) W option (10k) 1000 kHz

Wiper at midpoint (80hex) U option (50k) 250 kHz

(Note 18)

Wiper at midpoint (80hex) T option (100k) 120 kHz

RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)

RINL

Integral non-linearity W option -3 ±1.5 3 MI

(Note 14)

U, T option -1 ±0.3 1 MI

RDNL

Differential non-linearity W option -1.5 ±0.4 1.5 MI

(Note 13)

U, T option -0.5 ±0.15 0.5 MI

Roffset

Offset W option 0 1 5 MI

(Note 12)

U, T option 0 0.5 2 MI

(Notes 15, 16)

Resistance temperature coefficient DCP register set between 32 hex and FF hex ±50 ppm/°C

TYP

(Note 4)

MAX

(Note 18) UNIT

(Note 11)

Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by

characterization.

SYMBOL PARAMETER TEST CONDITIONS

CC1

VCC Supply Current (volatile write/read)

= +5.5V, V- = -5.5V, f

SDA = Open; (for I

= 400kHz;

SCL

C, active, read and write

states) V

= +2.25V, V- = -2.25V, f

SDA = Open; (for I

C, active, read and write

SCL

states)

V-1

V- Supply Current (volatile write/read) V- = -5.5V, V

SDA = Open; (for I

= +5.5V, f

SCL

C, active, read and write

= 400kHz;

states) V- = -2.25V, V

SDA = Open; (for I

= +2.25V, f

C, active, read and write

SCL

states)

CC2

VCC Supply Current (non-volatile write/read)

= +5.5V, V- = -5.5V, f

SDA = Open; (for I

= 400kHz;

SCL

C, active, read and write

states) V

= +2.25V, V- = -2.25V, f

SDA = Open; (for I

C, active, read and write

SCL

states)

V-2

V- Supply Current (non-volatile write/read)

V- = -5.5V, V SDA = Open; (for I

= +5.5V, f

= 400kHz;

SCL

C, active, read and write

states)

V- Supply Current (non-volatile write/read)

V- = -2.25V, V SDA = Open; (for I

= +2.25V, f

C, active, read and write

SCL

states)

= 400kHz;

MIN

(Note 18)

-1 -0.18 mA

-0.4 -0.06 mA

-2 -1.2 mA

-0.7 -0.4 mA

TYP

(Note 4)

MAX

(Note 18) UNIT

0.07 0.15 mA

0.02 0.05 mA

12mA

0.3 0.7 mA

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Page 5

ISL22313

Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by

characterization. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

VCC Current (standby) V

= +5.5V, V- = -5.5V @ +85°C, I2C

interface in standby state

= +5.5V, V- = -5.5V @ +125°C, I2C

interface in standby state

= +2.25V, V- = -2.25V @ +85°C, I2C

interface in standby state

= +2.25V, V- = -2.25V @ +125°C, I2C

interface in standby state

V-SB

V- Current (standby) V- = -5.5V, V

= +5.5V @ +85°C, I2C

interface in standby state V- = -5.5V, V

interface in standby state V- = -2.25V, V

interface in standby state

VCC Current (shutdown) V

= +5.5V, V- = -5.5V @ +85°C, I2C

= +5.5V @ +125°C, I2C

= +2.25V @ +85°C, I2C

= +2.25V @ +125°C, I2C

interface in standby state

= +5.5V, V- = -5.5V @ +125°C, I2C

interface in standby state

= +2.25V, V- = -2.25V @ +85°C, I2C

interface in standby state

= +2.25V, V- = -2.25V @ +125°C, I2C

interface in standby state

V-SB

V- Current (standby) V- = -5.5V, V

interface in standby state V- = -5.5V, V

interface in standby state V- = -2.25V, V

= +5.5V @ +85°C, I2C

= +5.5V @ +125°C, I2C

= +2.25V @ +85°C, I2C

interface in standby state V- = -2.25V, V

= +2.25V @ +125°C, I2C

interface in standby state

LkgDig

DCP

(Note 16)

ShdnRec

(Note 16)

Leakage current, at pins A0, A1, SDA, and SCL

DCP wiper response time SCL falling edge of last bit of DCP data byte

DCP recall time from shutdown mode SCL falling edge of last bit of ACR data byte

Vpor Power-on recall voltage Minimum V

VCC Ramp V

ramp rate 0.2 V/ms

Power-up delay VCC above Vpor, to DCP Initial Value

Voltage at pin from GND to V

to wiper new position

to wiper stored position and RH connection

at which memory recall occurs 1.9 2.1 V

EEPROM SPECIFICATION

EEPROM Endurance 1,000,000 Cycles EEPROM Retention Temperature T ≤ +55°C50 Years

(Note 17)

Non-volatile Write cycle time 12 20 ms

C Interface

MIN

(Note 18)

-2.5 -0.7 µA

-4 -3 µA

-1.5 -0.3 µA

-3 -1 µA

-2.5 -0.7 µA

-4 -3 µA

-1.5 -0.3 µA

-3 -1 µA

-1 1 µA

TYP

(Note 4)

MAX

(Note 18) UNIT

0.2 1.5 µA

12.5µA

0.1 1 µA

0.5 2 µA

0.2 1.5 µA

12.5µA

0.1 1 µA

0.5 2 µA

1.5 µs

5ms

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Page 6

ISL22313

Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by

characterization. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

SERIAL INTERFACE SPECS

A1, A0, SDA, and SCL input buffer

LOW voltage

A1, A0, SDA, and SCL input buffer

HIGH voltage

Hysteresis

SDA and SCL input buffer hysteresis 0.05*V

(Note 16)

Cpin

(Note 16)

SCL

(Note 16)

BUF

(Note 16)

SDA output buffer LOW voltage, sinking 4mA

A1, A0, SDA, and SCL pin capacitance

SCL frequency 400 kHz Pulse width suppression time at SDA

and SCL inputs SCL falling edge to SDA output data

valid Time the bus must be free before the

start of a new transmission

Any pulse narrower than the max spec is suppressed

SCL falling edge crossing 30% of V SDA exits the 30% to 70% of V

SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of V during the following START condition

LOW

HIGH

SU:STA

HD:STA

SU:DAT

Clock LOW time Measured at the 30% of VCC crossing 1300 ns Clock HIGH time Measured at the 70% of VCC crossing 600 ns START condition setup time SCL rising edge to SDA falling edge; both

crossing 70% of V

START condition hold time From SDA falling edge crossing 30% of VCC

to SCL falling edge crossing 70% of V

Input data setup time From SDA exiting the 30% to 70% of VCC

window, to SCL rising edge crossing 30% of V

HD:DAT

Input data hold time From SCL rising edge crossing 70% of VCC

to SDA entering the 30% to 70% of V window

SU:STO

HD:STO

(Note 16)

STOP condition setup time From SCL rising edge crossing 70% of VCC,

to SDA rising edge crossing 30% of V

STOP condition hold time for read, or volatile only write

Output data hold time From SCL falling edge crossing 30% of V

From SDA rising edge to SCL falling edge; both crossing 70% of V

until SDA enters the 30% to 70% of V window

SDA and SCL rise time From 30% to 70% of V

(Note 16)

SDA and SCL fall time From 70% to 30% of V

(Note 16)

Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF

(Note 16)

Rpu

(Note 16)

SDA and SCL bus pull-up resistor off-chip

Maximum is determined by t For Cb = 400pF, max is about 2kΩ~2.5kΩ For Cb = 40pF, max is about 15kΩ~20kΩ

and t

, until

window

MIN

(Note 18)

-0.3 0.3*V

0.7*V

00.4V

1300 ns

600 ns

100 ns

0ns

600 ns

1300 ns

0ns

20 +

0.1 * Cb 20 +

0.1 * Cb

1kΩ

TYP

(Note 4)

MAX

(Note 18) UNIT

VCC+0.

10 pF

50 ns

900 ns

250 ns

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July 17, 2007

Page 7

ISL22313

Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by

characterization. (Continued)

MIN

SYMBOL PARAMETER TEST CONDITIONS

SU:A

HD:A

A1 and A0 setup time Before START condition 600 ns A1 and A0 hold time After STOP condition 600 ns

(Note 18)

NOTES:

4. Typical values are for T

5. LSB: [V(R incremental voltage when changing from one tap to an adjacent tap.

– V(RW)0]/255. V(RW)

W)255

6. ZS error = V(RW)

7. FS error = [V(RW)

8. DNL = [V(RW)

9. INL = [V(RW)

10. for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper

11. MI =

|RW

– V(RW)

– i • LSB – V(RW)0]/LSB for i = 1 to 255

Max V RW()

()Min V RW()

----------------------------------------------------------------------------------------------

()Min V RW()

Max V RW()

– RW

255

= +25°C and 3.3V supply voltage.

and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the

255

/LSB.

– VCC]/LSB.

255

]/LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

()–

()+[]2⁄

|/255. MI is a minimum increment. RW

---------------- -

×=

165°C

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

and RW0 are the measured resistances for the DCP register set to FF hex and

255

00 hex respectively.

12. Roffset = RW Roffset = RW

13. RDNL = (RW

14. RINL = [RW

15. for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is

/MI, when measuring between RW and RL.

/MI, when measuring between RW and RH.

255

– RW

– (MI • i) – RW0]/MI, for i = 16 to 255.

Max Ri()Min Ri()–[]

--------------------------------------------------------------- -

Max Ri()Min Ri()+[]2⁄

)/MI -1, for i = 16 to 255.

i-1

---------------- -

×=

165°C

the minimum value of the resistance over the temperature range.

16. Limits should be considered typical and are not production tested.

is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile

17. t

write cycle.

18. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.

TYP

(Note 4)

MAX

(Note 18) UNIT

DCP Macro Model

10pF

SDA vs SCL Timing

SCL

SU:STA

(INPUT TIMING)

(OUTPUT TIMING)

SDA

TOTAL

25pF

HD:STA

10pF

SU:DAT

HIGH

LOW

HD:DAT

SU:STO

BUF

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July 17, 2007

Page 8

A0 and A1 Pin Timing

START

ISL22313

STOP

SCL

SDA

SU:A

A0, A1

Typical Performance Curves

WIPER RESISTANCE (Ω)

0 50 100 150 200 250

TAP POSITION (DECIMAL)

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

[ I(RW) = V

CC/RTOTAL

T = +125ºC

T = +25ºC

T = -40ºC

] FOR 10kΩ (W)

CLK 1

HD:A

2.0

1.5

1.0 I

0.5

-0.5

-1.0

STANDBY CURRENT (µA)

-1.5

-2.0

-40 0 40 80 120 TEMPERATURE (°C)

FIGURE 2. STANDBY I

V-

AND IV- vs TEMPERATURE

0.50

T = +25ºC

VCC = 2.25V

0.25

DNL (LSB)

-0.25

VCC = 5.5V

-0.50 0 50 100 150 200 250

TAP POSITION (DECIMAL)

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

0.50 VCC = 5.5V

0.25

INL (LSB)

-0.25

VCC = 2.25V

-0.50 0 50 100 150 200 250

TAP POSITION (DECIMAL)

T = +25ºC

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

July 17, 2007

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Page 9

Typical Performance Curves (Continued)

2.0 10k

ISL22313

1.6

1.2

0.8

ZS ERROR (LSB)

VCC = 2.25V VCC = 5.5V

0.4

-40 0 40 80 120 TEMPERATURE (ºC)

50k

FIGURE 5. ZS ERROR vs TEMPERATURE

0.5

T = +25ºC

0.25

RDNL (MI)

-0.25

-0.50 0 50 100 150 200 250

VCC = 5.5V

VCC = 2.25V

TAP POSITION (DECIMAL)

FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR

10kΩ (W)

-1 VCC = 2.25V

-2

-3

FS ERROR (LSB)

10k

-4

-5

-40 0 40 80 120 TEMPERATURE (ºC)

50k

VCC = 5.5V

FIGURE 6. FS ERROR vs TEMPERATURE

2.0 T = +25ºC

1.5

1.0

0.5

RINL (MI)

VCC = 5.5V

-0.5 0 50 100 150 200 250

VCC = 2.25V

TAP POSITION (DECIMAL)

FIGURE 8. INL vs TAP POSITION IN RHEOST AT MODE FOR

10kΩ (W)

1.60

1.20

0.80

CHANGE (%)

0.40

TOTAL

0.00

-0.40

-40 0 40 80 120 TEMPERATURE (ºC)

FIGURE 9. END TO END R

2.25V

% CHANGE vs

TOTAL

5.5V

TEMPERATURE

50k

10k

200

160

10k

120

TCv (ppm/ºC)

16 66 116 166

TAP POSITION (DECIMAL)

216 266

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

50k

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July 17, 2007

Page 10

Typical Performance Curves (Continued)

ISL22313

500

10k

16 66 116 166 216

TAP POSITION (D ECIMAL)

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm

SCL

TCr (ppm/ºC)

400

300

200

100

50k

INPUT

WIPER AT MID POINT (POSITION 80h) R

= 10kΩ

TOTAL

FIGURE 12. FREQUENCY RESPONSE (1MHz)

OUTPUT

WIPER

FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h

Pin Description

Potentiometers Pins

RH and RL

The high (RH) and low (RL) terminals of the ISL22313 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 255 decimal, the wiper will be closest to RH, and with the WR set to 0, the wiper is closest to RL.

RW is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register.

WIPER UNLOADED,

MOVEMENT FROM 0h to FFh

FIGURE 14. LARGE SIGNAL SETTLING TIME

Bus Interface Pins

Serial Data Input/Output (SDA)

The SDA is a bidirectional serial data input/output pin for I interface. It receives device address, operation code, wiper address and data from an I

C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock.

SDA requires an external pull-up resistor, since it is an ope n drain input/output.

Serial Clock (SCL)

This input is the serial clock of the I

C serial interface. SCL requires an external pull-up resistor, since it is an open drain input.

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Page 11

ISL22313

Device Address (A1, A0)

The address inputs are used to set the least significant 2 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL22313. A maximum of four ISL22313 devices may occupy the I

C serial bus (see Table 3).

Principles of Operation

The ISL22313 is an integrated circuit incorporating one DCP with its associated registers, non-volatile memory and an I serial interface providing direct communication between a host and the potentiometer and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper.

The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions.

When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is restored, the contents of the IVR are recalled and loaded into the WR to set the wiper to the initial value.

DCP Description

The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR[7:0]= 00h), its wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR register of a DCP contains all ones (WR[7:0]= FFh), its wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically.

While the ISL22313 is being powered up, the WR is reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WR will be reloaded with the value stored in a non-volatile Initial Value Register (IVR).

The WR and IVR can be read or written to directly using the

C serial interface as described in the following sections.

Memory Description

The ISL22313 contains one non-volatile 8-bit Initial Value Register (IVR), fourteen General Purpose non-volatile 8-bit registers and two volatile 8-bit registers: Wiper Register (WR) and Access Control Register (ACR). Memory map of ISL22313 is in Table 1. The non-volatile register (IVR) at address 0, contains initial wiper position and volatile register (WR) contains current wiper position.

TABLE 1. MEMORY MAP

ADDRESS

(hex) NON-VOLATILE VOLATILE

10 N/A ACR

FReserved

E General Purpose N/A D General Purpose N/A C General Purpose N/A

B General Purpose N/A

A General Purpose N/A

9 General Purpose N/A

8 General Purpose N/A

7 General Purpose N/A

6 General Purpose N/A

5 General Purpose N/A

4 General Purpose N/A

3 General Purpose N/A

2 General Purpose N/A

1 General Purpose N/A

0IVR WR

The non-volatile IVR and volatile WR registers are accessible with the same address.

The Access Control Register (ACR) contains information and control bits described below in Table 2.

The VOL bit (ACR[7]) determines whether the access to wiper registers WR or initial value registers IVR.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

BIT # 7 6 5

NAME VOL SHDN WIP

If VOL bit is 0, the non-volatile IVR register is accessible. If VOL bit is 1, only the volatile WR is accessible. Note: Value is written to IVR register also is written to the WR. The default value of this bit is 0.

The SHDN

bit (ACR[6]) disables or enables Shutdown mode. When t h i s b it is 0 , i.e. DCP is forced to end-to-end open circuit and RW is shorted to RL as shown on Figure 15. Default value of the SHDN

43210 00000

bit is 1.

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FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE

The WIP bit (ACR[5]) is a read-only bit. It indicates that nonvolatile write operation is in progress. It is impossible to write to the WR or ACR while WIP bit is 1.

I2C Serial Interface

The ISL22313 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL22313 operates as a slave device in all applications.

All communication over the I

C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 16). On power-up of the ISL22313, the SDA pin is in the input mode.

ISL22313

All I

C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22313 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 16). A START condition is ignored during the powerup of the device.

All I

C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 16). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode.

An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 17).

The ISL22313 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22313 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 10100 as the five MSBs, and the following two bits matching the logic values present at pins A1 and A0. The LSB is the Read/Write

bit. Its value is “1” for a Read operation and “0” for a Write operation (see Table 3).

TABLE 3. IDENTIFICATION BYTE FORMAT

LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY

SCL

SDA

10100A1A0R/W

(MSB) (LSB)

START DATA DATA STOP

FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS

STABLE CHANGE

DATA

STABLE

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SCL FROM

MASTER

ISL22313

81 9

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

SIGNALS FROM

SIGNAL AT SDA

SIGNALS FROM

HIGH IMPEDANCE

START ACK

FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER

WRITE

THE MASTER

THE SLAVE

T A

IDENTIFICATION

R T

BYTE

10100

ADDRESS

BYTE

A0A1

0000

A C K

FIGURE 18. BYTE WRITE SEQUENCE

DATA BYTE

HIGH IMPEDANCE

T O P

A C K

SIGNALS

FROM THE

MASTER

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

S T A

IDENTIFICATION

BYTE WITH

R/W

10100

= 0

A C K

ADDRESS

BYTE

0000A0A1 A0A1

A C K

FIGURE 19. READ SEQUENCE

Write Operation

A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22313 responds with an ACK. At this time, the device enters its standby state (see Figure 18).

The non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next non-volatile write. Thus, non-volatile registers must be written individually.

S T A

IDENTIFICATION

BYTE WITH

R/W

S T

= 1

0101

A C K

FIRST READ

DATA BYTE

LAST READ DATA BYTE

Read Operation

A Read operation consist of a three byte instruction followed by one or more Data Bytes (see Figure 19). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W Address Byte, a second START, and a second Identification byte with the R/W

bit set to “1”. After each of the three bytes, the ISL22313 responds with an ACK. Then the ISL22313 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The Data Bytes are from the registers indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and

bit set to “0”, an

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increments by one during transmission of each Data Byte. After reaching the memory location 0Fh, the pointer “rolls over” to 00h, and the device continues to output data for each ACK received.The master terminates the read operation issuing a NACK (ACK

) and a STOP condition

following the last bit of the last Data Byte (see Figure 19).

Applications Information

When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients (or overshoot/undershoot) resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break within an extremely short period of time (<50ns). Two such code transitions are EFh to F0h, and 0Fh to 10h. Note that all switching transients will settle well within the settling time as stated in the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus this may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery.

ISL22313

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ISL22313

Mini Small Outline Plastic Packages (MSOP)

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

TOP VIEW

NOTES:

1. These package dimensions are within allowable dimensions of JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING PLANE

0.20 (0.008) C

- H -

4X θ

END VIEW

-B-

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.007 0.011 0.18 0.27 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.020 BSC 0.50 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N10 107

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

Rev. 0 12/02

NOTESMIN MAX MIN MAX

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.

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