Datasheet IS93C46-3P, IS93C46-3GRI, IS93C46-3GR, IS93C46-3GI, IS93C46-3PI Datasheet (ISSI)

®

IS93C46-3

1,024-BIT SERIAL ELECTRICALLY
ERASABLE PROM

FEATURES

• State-of-the-art architecture
— Non-volatile data storage
— Low voltage operation:

3.0V (Vcc = 2.7V to 6.0V)
— Full TTL compatible inputs and outputs
— Auto increment for efficient data dump

• Low voltage read operation
— Down to 2.7V

• Hardware and software write protection
— Defaults to write-disabled state at power-up
— Software instructions for write-enable/disable

2

• Advanced low voltage CMOS E
technology

• Versatile, easy-to-use Interface
— Self-timed programming cycle
— Automatic erase-before-write
— Programming status indicator
— Word and chip erasable
— Stop SK anytime for power savings

• Durable and reliable
— 10-year data retention after 100K write cycles
— 100,000 write cycles
— Unlimited read cycles

PROM

OVERVIEW

The IS93C46-3 is a low cost 1,024-bit, non-volatile, serial
E2PROM. It is fabricated using ISSI’s advanced CMOS
E2PROM technology. The IS93C46-3 provides efficient
non-volatile read/write memory arranged as 64 registers
of 16 bits each. Seven 9-bit instructions control the
operation of the device, which includes read, write, and
mode enable functions. The data out pin (DOUT) indicates
the status of the device during in the self-timed non­volatile programming cycle.

The self-timed write cycle includes an automatic erase­before-write capability. To protect against inadvertent
writes, the WRITE instruction is accepted only while the
chip is in the write enabled state. Data is written in 16 bits
per write instruction into the selected register. If Chip
Select (CS) is brought HIGH after initiation of the write
cycle, the Data Output (DOUT) pin will indicate the READY/
BUSY status of the chip.

APPLICATIONS

The IS93C46-3 is ideal for high-volume applications
requiring low power and low density storage. This device
uses a low cost, space saving 8-pin package. Candidate
applications include robotics, alarm devices, electronic
locks, meters and instrumentation settings.

ISSI

MARCH 2001

FUNCTIONAL BLOCK DIAGRAM

DATA

REGISTER

D

IN

CS

SK

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. G

04/26/01

INSTRUCTION

REGISTER

(9 BITS)

INSTRUCTION

DECODE,

CONTROL,

AND

CLOCK

GENERATION

(16 BITS)

ADDRESS

REGISTER

WRITE

ENABLE

DUMMY

BIT

R/W

AMPS

1 OF 64

DECODER

HIGH VOLTAGE

GENERATOR

EEPROM

(64 X 16)

ARRAY

D

OUT

1

IS93C46-3

®

ISSI

PIN CONFIGURATION

8-Pin DIP

8

VCC

7

NC

6

NC

5

GND

D

CS
SK

D

OUT

1
2
3

IN

4

PIN DESCRIPTIONS

CS Chip Select
SK Serial Data Clock
DIN Serial Data Input
DOUT Serial Data Output
NC Not Connected
Vcc Power
GND Ground

PIN CONFIGURATION

8-Pin JEDEC Small Outline “G”

8

NC

VCC

CS

SK

1
2
3
4

NC

7

GND

6

D

OUT

5

D

IN

PIN CONFIGURATION

8-Pin JEDEC Small Outline “GR”

8

VCC

7

NC

6

NC

5

GND

D

CS
SK

D

OUT

1
2
3

IN

4

ENDURANCE AND DATA RETENTION

The IS93C46-3 is designed for applications requiring up to
100,000 programming cycles (WRITE, WRALL, ERASE
and ERAL). It provides 10 years of secure data retention,
without power after the execution of 100,000 programming
cycles.

DEVICE OPERATION

The IS93C46-3 is controlled by seven 9-bit instructions.
Instructions are clocked in (serially) on the DIN pin. Each
instruction begins with a logical “1” (the start bit). This is
followed by the opcode (2 bits), the address field (6 bits),
and data, if appropriate. The clock signal (SK) may be
halted at any time and the IS93C46-3 will remain in its last
state. This allows full static flexibility and maximum
power conservation.

Read (READ)

The READ instruction is the only instruction that outputs
serial data on the DOUT pin. After the read instruction and
address have been decoded, data is transferred from the
selected memory register into a 16-bit serial shift register.
(Please note that one logical “0” bit precedes the actual
16-bit output data string.) The output on DOUT changes
during the low-to-high transitions of SK (see Figure 3).

Low Voltage Read

The IS93C46-3 has been designed to ensure that data
read operations are reliable in low voltage environments.
The IS93C46-3 is guaranteed to provide accurate data
during read operations with Vcc as low as 2.7V.

Auto Increment Read Operations

In the interest of memory transfer operation applications,
the IS93C46-3 has been designed to output a continuous
stream of memory content in response to a single read
operation instruction. To utilize this function, the system
asserts a read instruction specifying a start location
address. Once the 16 bits of the addressed word have
been clocked out, the data in consecutively higher address
locations (the address “000000” is assumed as the ad­dress of “111111") is output. The address will wrap around
continuously with CS HIGH until the chip select (CS)
control pin is brought
data dumps to be executed with a minimum of firmware
overhead.

Write Enable (WEN)

The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL, ERASE,
and ERAL) can be done. When Vcc is applied, this device

LOW

. This allows for single instruction

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. G

04/26/01

IS93C46-3

®

ISSI

powers up in the write disabled state. The device then
remains in a write disabled state until a WEN instruction
is executed. Thereafter, the device remains enabled until
a WDS instruction is executed or until Vcc is removed.
(NOTE: Neither the WEN nor the WDS instruction has any
effect on the READ instruction.) (See Figure 4.)

Write (WRITE)

The WRITE instruction includes 16 bits of data to be
written into the specified register. After the last data bit
has been applied to DIN, and before the next rising edge of
SK, CS must be brought LOW. The falling edge of CS
initiates the self-timed programming cycle.

After a minimum wait of 250 ns (5V operation) from the
falling edge of CS (tCS), if CS is brought HIGH, DOUT will
indicate the READY/BUSY status of the chip: logical “0”
means programming is still in progress; logical “1” means
the selected register has been written, and the part is
ready for another instruction (see Figure 5). (NOTE: The
combination of CS HIGH, DIN HIGH and the rising edge of
the SK clock, resets the READY/BUSY flag. Therefore, it
is important if you want to access the READY/BUSY flag
, not to reset it through this combination of control
signals.) Before a WRITE instruction can be executed, the
device must be write enabled (see WEN).

Write All (WRALL)

The write all (WRALL) instruction programs all registers
with the data pattern specified in the instruction. While the
WRALL instruction is being loaded, the address field

becomes a sequence of “Don’t Care” bits (see Figure 6).
As with the WRITE instruction, if CS is brought HIGH after

a minimum wait of 250 ns (tCS), the DOUT pin indicates the
READY/BUSY status of the chip (see Figure 6).

Write Disable (WDS)

The write disable
capabilities. This protects the entire part against acciden­tal modification of data until a WEN instruction is exe­cuted. (When Vcc is applied, this part powers up in the
write disabled state.) To protect data, a WDS instruction
should be executed upon completion of each programming
operation. (
has any effect on the READ instruction.) (See Figure 7.)

NOTE:

(WDS)

instruction disables all programming

Neither the

WEN

nor the

WDS

instruction

Erase Register (ERASE)

After the erase instruction is entered, CS must be brought
LOW. The falling edge of CS initiates the self-timed
internal programming cycle. Bringing CS HIGH after a
minimum of tCS, will cause DOUT to indicate the
status of the chip: a logical “0” indicates programming is
still in progress; a logical “1” indicates the erase cycle is
complete and the part is ready for another instruction (see
Figure 8).

READ/BUSY

Erase All (ERAL)

Full chip erase is provided for ease of programming.
Erasing the entire chip involves setting all bits in the entire
memory array to a logical “1” (see Figure 9).

INSTRUCTION SET

Instruction Start Bit OP Code Address Input Data

READ 1 10 (A5-A0)
WEN 1 00 11XXXX

(Write Enable)
WRITE 1 01 (A5-A0) D15-D0
WRALL 1 00 01XXXX D15-D0

(Write All Registers)

WDS 1 00 00XXXX
(Write Disable)

ERASE 1 11 (A5-A0)
ERAL 1 00 10XXXX

(Erase All Registers)

Note: 1. If input data is not 16 bits exactly, the last 16 bits will be taken as input data (a word).

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. G

04/26/01

(1)

(1)

3

IS93C46-3

®

ISSI

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VGND Voltage with Respect to GND –0.3 tp +6.5 V
TBIAS Temperature Under Bias (IS93C46-3) 0 to +70 °C
TBIAS Temperature Under Bias (IS93C46-3I) –40 to +85 °C
TSTG Storage Temperature –65 to +125 °C

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

(1)

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 2.7V to 6.0V
Industrial –40°C to +85°C 2.7V to 6.0V

CAPACITANCE

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 5 pF
COUT Output Capacitance VOUT = 0V 5 pF

FIGURE 1. AC TEST CONDITIONS

+2.08V

800Ω

D

OUT

100 pF

Vcc = 5.0V

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Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. G

04/26/01

®

IS93C46-3

ISSI

DC ELECTRICAL CHARACTERISTICS

TA = 0°C to +70°C for IS93C46-3 and –40°C to +85°C for IS93C46-3I.

Symbol Parameter Test Conditions Vcc Min. Max. Unit

VOL Output LOW Voltage IOL = 10 µA CMOS 2.7V to 3.3V — 0.2 V
VOL1 Output LOW Voltage IOL = 2.1 mA TTL 4.5V to 5.5V — 0.4 V
VOH Output HIGH Voltage IOH = –10 µA CMOS 2.7V to 3.3V VCC – 0.2 — V
VOH1 Output HIGH Voltage IOH = –400 µA TTL 4.5V to 5.5V 2.4 — V
VIH Input HIGH Voltage 2.7V to 3.3V 2.4 VCC V

4.5V to 5.5V 2 VCC

VIL Input LOW Voltage 2.7V to 3.3V –0.1 0.6 V

4.5V to 5.5V –0.1 0.8
ILI Input Leakage VIN = 0V to VCC (CS, SK, DIN)11µA
ILO Output Leakage VOUT = 0V to VCC, CS = 0V 1 1 µA

POWER SUPPLY CHARACTERISTICS

TA = 0°C to +70°C for IS93C46-3 and –40°C to +85°C for IS93C46-3I.

IS93C46-3 IS93C46-3I

Symbol Parameter Test Conditions Vcc Min. Typ. Max. Min. Typ. Max. Unit

ICC

ICC

ISB

Vcc Operating CS = VIH, SK = 500 KHz
Supply Current CMOS Input Levels

Vcc Operating CS = VIH, SK = 1 MHz
Supply Current CMOS Input Levels

Standby Current CS = DIN = SK = 0V

2.7V to 3.3V — 0.5 2 — 0.5 2 mA

4.5V to 5.5V — 46 — 46 mA

2.7V to 3.3V — 210 — 210 µA

4.5V to 5.5V — 10 50 — 10 50

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. G

04/26/01

5

IS93C46-3

ISSI

AC ELECTRICAL CHARACTERISTICS

TA = 0°C to +70°C for IS93C46-3 and –40°C to +85°C for IS93C46-3.

IS93C46-3 IS93C46-3I

Symbol Parameter Test Conditions Vcc Min. Max. Min. Max. Unit

SK SK Clock Frequency 2.7V to 6.0V 0 500 0 500 KHz

f

4.5V to 6.0V 0 1 0 1 MHz

tSKH SK HIGH Time 2.7V to 6.0V 500 — 500 — ns

4.5V to 6.0V 250 — 250 —

SKL SK LOW Time 2.7V to 6.0V 1 — 1 — µs

t

4.5V to 6.0V 250 — 250 — ns

t

CS Minimum CS LOW Time 2.7V to 6.0V 500 — 500 — ns

4.5V to 6.0V 250 — 250 —

tCSS CS Setup Time Relative to SK 2.7V to 6.0V 100 — 100 — ns

4.5V to 6.0V 50 — 50 — ns

tDIS DIN Setup Time Relative to SK 2.7V to 6.0V 200 — 200 — ns

4.5V to 6.0V 100 — 100 — ns

®

tCSH CS Hold Time Relative to SK 2.7V to 6.0V 0 — 0 — ns

4.5V to 6.0V 0 — 0 —

tDIH DIN Hold Time Relative to SK 2.7V to 6.0V 400 — 400 — ns

4.5V to 6.0V 100 — 100 —

tPD1 Output Delay to “1” AC Test 2.7V to 6.0V — 500 — 500 ns

4.5V to 6.0V — 500 — 500

tPD0 Output Delay to “0” AC Test 2.7V to 6.0V — 500 — 500 ns

4.5V to 6.0V — 500 — 500

tSV CS to Status Valid

tDF CS to DOUT in 3-state CS = VIL 2.7V to 6.0V — 200 — 200 ns

tWP Write Cycle Time 2.7V to 6.0V — 10 — 10 ms

AC Test, CL = 100 pF

2.7V to 6.0V — 500 — 500 ns

4.5V to 6.0V — 500 — 500

4.5V to 6.0V — 100 — 100

4.5V to 6.0V — 10 — 10

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. G

04/26/01

IS93C46-3

AC WAVEFORMS

FIGURE 2. SYNCHRONOUS DATA TIMING

®

ISSI

CS

tCSS tSKL tCSH

SK

tDIS tDIH

DIN

DOUT

(READ)

OUT

D

(WRITE)
(WRALL)
(ERASE)

(ERAL)

tSV

FIGURE 3. READ CYCLE TIMING

tSKH

tPD0

T

tPD1 tDF

tDF

STATUS VALID

CS

SK

D

IN

D

OUT

*

Address Pointer Cycles to the Next Register

110A5 A0

D15 D0

0

t

CS

*

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. G

04/26/01

7

IS93C46-3

FIGURE 4. SYNCHRONOUS DATA TIMING

CS

SK

D

IN

DOUT = 3-state

FIGURE 5. WRITE (WRITE) CYCLE TIMING

1100 1

®

ISSI

tCS

t

CS

CS

SK

D

IN

D

OUT

110A5A0

FIGURE 6. WRITE ALL (WRALL) TIMING

CS

SK

D15 D0

t

SV

BUSY READY

t

WP

t

CS

t

DF

D

D

OUT

IN

110

00

8

D15 D0

t

SV

BUSY READY

t

WP

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. G

04/26/01

IS93C46-3

FIGURE 7. WRITE DISABLE (WDS) CYCLE TIMING

t

CS

CS

SK

®

ISSI

D

IN

100

00

DOUT = 3-STATE

FIGURE 8. ERASE (REGISTER ERASE) CYCLE TIMING

SK

t

CS

CS

D

D

IN

OUT

111A4

A5

A0

t

SV

BUSY READY

t

WP

t

DF

FIGURE 9. ERASE ALL (ERAL) CYCLE TIMING

SK

t

CS

CS

D

IN

D

OUT

Note for Figures 8 and 9:

After the completion of the instruction (D
indicates BUSY status) then performs another instruction would cause device malfunction.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. G

04/26/01

010

OUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT

10

t

SV

BUSY READY

t

WP

t

DF

9

IS93C46-3

®

ISSI

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (KHz) Order Part No. Package

500 IS93C46-3P 300-mil Plastic DIP
500 IS93C46-3G Small Outline (JEDEC)
500 IS93C46-3GR Small Outline (JEDEC)

ORDERING INFORMATION
Industrial Range: –40°C to +85°C

Speed (MHz) Order Part No. Package

1 IS93C46-3PI 300-mil Plastic DIP
1 IS93C46-3GI Small Outline (JEDEC)
1 IS93C46-3GRI Small Outline (JEDEC)

10

®

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

www.issi.com

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. G

04/26/01