Datasheet IS62WV51216ALL, IS62WV51216BLL Datasheet (ISSI)

IS62WV51216ALL

®

IS62WV51216BLL

512K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access time: 45ns, 55ns

• CMOS low power operation
– 36 mW (typical) operating
– 12 µW (typical) CMOS standby

• TTL compatible interface levels

• Single power supply
– 1.65V--2.2V V
– 2.5V--3.6V V

• Fully static operation: no clock or refresh
required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Lead-free available

DD (62WV51216ALL)

DD (62WV51216BLL)

DESCRIPTION

The ISSI IS62WV51216ALL/ IS62WV51216BLL are high-
speed, 8M bit static RAMs organized as 512K words by 16
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high­performance and low power consumption devices.

When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.

Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.

The IS62WV51216ALL and IS62WV51216BLL are packaged
in the JEDEC standard 48-pin mini BGA (7.2mm x 8.7mm)
and 44-Pin TSOP (TYPE II).

ISSI

FEBRUARY 2005

FUNCTIONAL BLOCK DIAGRAM

A0-A18

VDD
GND

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

CS2

CS1

OE

WE

UB

LB

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

512K x 16

MEMORY ARRAY

COLUMN I/O

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IS62WV51216ALL, IS62WV51216BLL ISSI

®

PIN CONFIGURATIONS
48-Pin mini BGA (7.2mm x 8.7mm)

1 2 3 4 5 6

A1

A
B
C
D
E
F
G
H

LB

I/O

I/O

GND

V

I/O

I/O

A18

8

9

DD

14

15

A0

OE

UB A3

I/O10A5

A17

I/O

11

I/O12GND

A14

I/O

13

A12

NC

A9

A8

A6

A7

A16

A15

A13

A10

A4

A2

CS1 I/O

I/O1I/O

I/O

3

I/O

GND

4

I/O

5

WE

A11 NC

CS2

V

I/O

I/O

DD`

PIN DESCRIPTIONS

A0-A18 Address Inputs
I/O0-I/O15 Data Inputs/Outputs

CS1, CS2 Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)

0

2

6

7

UB Upper-byte Control (I/O8-I/O15)
N C No Connection
VDD Power
GND Ground

44-Pin TSOP (Type II)

1

A4

2

A3

3

A2

4

A1

5

A0

6

CS1

7

I/O0

8

I/O1

9

I/O2

10

I/O3

11

V

DD

12

GND

13

I/O4

14

I/O5

15

I/O6

16

I/O7

17

WE

18

A16

19

A15

20

A14

21

A13

22

A12

44

A5

43

A6

42

A7

41

OE

40

UB

39

LB

38

I/O15

37

I/O14

36

I/O13

35

I/O12

34

GND

33

V

DD

32

I/O11

31

I/O10

30

I/O9

29

I/O8

28

A18

27

A8

26

A9

25

A10

24

A11

23

A17

2

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IS62WV51216ALL, IS62WV51216BLL ISSI

TRUTH TABLE

I/O PIN

Mode

WEWE

WE

WEWE

Not Selected X H X X X X High-Z High-Z I

Output Disabled H L H H L X High-Z High-Z ICC

Read H L H L L H DOUT High-Z ICC

Write L L H X L H DIN High-Z ICC

CS1CS1

CS1 CS2

CS1CS1

OEOE

OE

OEOE

LBLB

LB

LBLB

UBUB

UB I/O0-I/O7 I/O8-I/O15 VDD Current

UBUB

SB1, ISB2

X X L X X X High-Z High-Z ISB1, ISB2
XXXXHH High-Z High-Z ISB1, ISB2

H L H H X L High-Z High-Z ICC

H L H L H L High-Z DOUT
HLHLLL DOUT DOUT

L L H X H L High-Z DIN
LLHXLL DIN DIN

®

OPERATING RANGE (VDD)

Range Ambient Temperature IS62WV51216ALL (70ns) IS62WV51216BLL (55ns, 70ns) IS62WV51216BLL (45ns)

Commercial 0°C to +70°C 1.65V - 2.2V 2.5V - 3.6V 3.0 - 3.6V
Industrial –40°C to +85°C 1.65V - 2.2V 2.5V - 3.6V

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IS62WV51216ALL, IS62WV51216BLL ISSI

®

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.2 to VDD+0.3 V
TBIAS Temperature Under Bias –40 to +85 °C
VDD VDD Related to GND –0.2 to +3.8 V
TSTG Storage Temperature –65 to +150 ° C
PT Power Dissipation 1.0 W

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions VDD Min. Max. Unit

VOH Output HIGH Voltage IOH = -0.1 mA 1.65-2.2V 1.4 — V

IOH = -1 mA 2.5-3.6V 2.2 — V

VOL Output LOW Voltage IOL = 0.1 mA 1.65-2.2V — 0.2 V

IOL = 2.1 mA 2.5-3.6V — 0.4 V

VIH Input HIGH Voltage 1.65-2.2V 1.4 VDD + 0.2 V

2.5-3.6V 2.2 VDD + 0.3 V

(1)

VIL

Input LOW Voltage 1.65-2.2V – 0. 2 0 .4 V

2.5-3.6V –0.2 0.6 V
ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled – 1 1 µA

Notes:

1. VIL (min.) = –1.0V for pulse width less than 10 ns.

4

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IS62WV51216ALL, IS62WV51216BLL ISSI

®

CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 8 pF
COUT Input/Output Capacitance VOUT = 0V 10 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

AC TEST CONDITIONS

Parameter 62WV51216ALL 62WV51216BLL

(Unit) (Unit)

Input Pulse Level 0.4V to VDD-0.2 0.4V to VDD-0.3V
Input Rise and Fall Times 5 ns 5ns
Input and Output Timing VREF VREF

and Reference Level
Output Load See Figures 1 and 2 See Figures 1 and 2

62WV51216ALL 62WV51216BLL

(1.65V - 2.2V) (2.5V - 3.6V)

R1(Ω) 3070 1029
R2(Ω) 3150 1728
VREF 0.9V 1.5V
VTM 1.8V 2.8V

AC TEST LOADS

R1

VTM

OUTPUT

30 pF

Including

jig and

scope

R2

VTM

OUTPUT

5 pF

Including

jig and

scope

R1

R2

Figure 1

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Figure 2

5

IS62WV51216ALL, IS62WV51216BLL ISSI

®

IS62WV51216ALL, POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

Symbol Parameter Test Conditions Max. Unit

70

CC VDD Dynamic Operating VDD = Max., Com. 20 m A

I

Supply Current IOUT = 0 mA, f = fMAX Ind. 25

I

CC1 Operating Supply VDD = Max., CS1 = 0.2V Com. 4 m A

Current WE = VDD – 0.2V Ind. 4

CS2 = VDD – 0.2V, f = 1MHZ

ISB1 TTL Standby Current VDD = Max., Com. 0.3 mA

(TTL Inputs) VIN = VIH or VIL Ind. 0.3

CS1 = VIH , CS2 = VIL,
f = 1 MHZ

OR

ULB Control

VDD = Max., VIN = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH

ISB2 CMOS Standby VDD = Max., Com. 1 5 µA

Current (CMOS Inputs) CS1 ≥ VDD – 0.2V, Ind. 2 1

CS2

≤ 0.2V, typ.

(1)

3
VIN ≥ VDD – 0.2V, or
VIN

≤

0.2V, f = 0

OR

ULB Control VDD = Max., CS1 = VIL, CS2=VIH

Note:.

1. Typical values are measured at V

VIN ≥ VDD – 0.2V, or VIN
UB / LB = VDD – 0.2V

DD = 1.8V, TA = 25

o

C and not 100% tested.

≤

0.2V, f = 0;

6

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IS62WV51216ALL, IS62WV51216BLL ISSI

®

IS62WV51216BLL, POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

Symbol Parameter Test Conditions Max. Max. Max. Unit

45 55 70

CC VDD Dynamic Operating VDD = Max., Com. 35 30 25 mA

I

Supply Current IOUT = 0 mA, f = fMAX Ind. 40 35 30

I

CC1 Operating Supply VDD = Max., CS1 = 0.2V Com. 5 5 5 m A

Current WE = VDD – 0.2V Ind. 5 5 5

CS2 = VDD – 0.2V, f = 1MHZ

ISB1 TTL Standby Current VDD = Max., Com. 0.3 0.3 0.3 m A

(TTL Inputs) VIN = VIH or VIL Ind. 0.3 0.3 0.3

CS1 = VIH , CS2 = VIL,
f = 1 MHZ

OR

ULB Control

VDD = Max., VIN = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH

ISB2 CMOS Standby VDD = Max., Com. 20 20 20 µ A

Current (CMOS Inputs) CS1 ≥ VDD – 0.2V, Ind . 25 25 25

CS2

≤ 0.2V, typ.

(2)

444
VIN ≥ VDD – 0.2V, or
VIN

≤

0.2V, f = 0

OR

ULB Control VDD = Max., CS1 = VIL, CS2=VIH

VIN ≥ VDD – 0.2V, or VIN

≤

0.2V, f = 0;

UB / LB = VDD – 0.2V

Note:

1. At f = f

2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

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IS62WV51216ALL, IS62WV51216BLL ISSI

®

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

45 ns 55 ns 70 ns

Symbol Parameter Min. Max. Min . Max. Min. Max. Unit

tRC Read Cycle Time 45 — 55 — 70 — ns
tAA Address Access Time — 45 — 55 — 70 ns
tOHA Output Hold Time 10 — 10 — 10 — ns
tACS1/tACS2 CS1/CS2 Access Time — 45 — 55 — 70 ns
tDOE OE Access Time — 20 — 25 — 35 ns

(2)

tHZOE

(2)

tLZOE
tHZCS1/tHZCS2
tLZCS1/tLZCS2

OE to High-Z Output — 15 — 2 0 — 2 5 ns
OE to Low-Z Output 5 — 5 — 5 — ns

(2)

CS1/CS2 to High-Z Output 0 15 0 20 0 25 ns

(2)

CS1/CS2 to Low-Z Output 10 — 10 — 10 — ns

tBA LB, UB Access Time — 45 — 55 — 70 ns
tHZB LB, UB to High-Z Output 0 15 0 20 0 25 ns
tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to

DD-0.2V/0.4V to VDD-0.3V and output loading specified in Figure 1.

V

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

AC WAVEFORMS
READ CYCLE NO. 1

ADDRESS

DQ0-D15

(1,2)

(Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH, UB or LB = VIL)

t

RC

t

AA

t

OHA

PREVIOUS DATA VALID

DATA VALID

t

OHA

8

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IS62WV51216ALL, IS62WV51216BLL ISSI

AC WAVEFORMS
READ CYCLE NO. 2

ADDRESS

OE

s

CS1

(1,3)

(CS1, CS2, OE, AND UB/LB Controlled)

t

RC

t

AA

t

DOE

t

LZOE

t

ACE1/tACE2

t

HZOE

t

OHA

®

LBs

DOUT

CS2s

,

UBs

t

LZCE1/

t

LZCE2

t

HIGH-Z

LZB

t

BA

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CS1, UB, or LB = V

3. Address is valid prior to or coincident with CS1 LOW transition.

IL. CS2=WE=VIH.

t

HZCS1/

t

HZCS1

t

DATA VALID

HZB

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IS62WV51216ALL, IS62WV51216BLL ISSI

®

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,2)

(Over Operating Range)

45ns 55 ns 70 ns

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 45 — 55 — 70 — ns
tSCS1/tSCS2 CS1/CS2 to Write End 35 — 45 — 60 — ns
tAW Address Setup Time to Write End 35 — 45 — 60 — ns
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 35 — 45 — 60 — ns

(4)

tPWE

WE Pulse Width 35 — 40 — 50 — ns

tSD Data Setup to Write End 20 — 25 — 30 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns

(3)

tHZWE
tLZWE

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
VDD-0.2V/0.4V to VDD-0.3V and output loading specified in Figure 1.

2.

The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to
write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

PWE

4. t

WE LOW to High-Z Output — 20 — 20 — 30 ns

(3)

WE HIGH to Low-Z Output 5 — 5 — 5 — ns

terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the

> tHZWE + tSD when OE is LOW.

AC WAVEFORMS

CS1

CS2

WE

DIN

(1,2)

(CS1 Controlled, OE = HIGH or LOW)

t

t

SCS1

t

SCS2

t

AW

t

t

t

SA

DATA UNDEFINED

t

HZWE

WC

PWE

PWB

HIGH-Z

t

SD

DATA-IN VALID

t

HA

t

LZWE

t

HD

WRITE CYCLE NO. 1

ADDRESS

LB, UB

DOUT

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.

2. WRITE = (CS1) [ (LB) = (UB) ] (WE).

10

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IS62WV51216ALL, IS62WV51216BLL ISSI

WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)

t

WC

ADDRESS

OE

t

HA

t

t

LZWE

HD

CS1

CS2

WE

LB, UB

DOUT

t

SA

DATA UNDEFINED

t

AW

t

HZWE

t

SCS1

t

SCS2

t

PWE

HIGH-Z

t

SD

®

DIN

DATA-IN VALID

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

t

WC

ADDRESS

OE

tSCS1

CS1

tSCS2

CS2

tAW

WE

LB, UB

DOUT

tSA

DATA UNDEFINED

tPWE

tHZWE

HIGH-Z

tSD tHD

tHA

tLZWE

DIN

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DATA-IN VALID

11

IS62WV51216ALL, IS62WV51216BLL ISSI

WRITE CYCLE NO. 4 (UB/LB Controlled)

t

t

WC

WC

®

ADDRESS

CS1

CS2

UB, LB

OUT

D

OE

WE

D

LOW

HIGH

DATA UNDEFINED

IN

t

HZWE

ADDRESS 1 ADDRESS 2

t

SA

t

HA

t

SA

t

PBW

t

SD

WORD 1

HIGH-Z

DATA

VALID

t

HD

IN

t

SD

WORD 2

t

PBW

DATA

VALID

t

HA

t

LZWE

t

HD

IN

UB_CSWR4.eps

12

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IS62WV51216ALL, IS62WV51216BLL ISSI

DATA RETENTION SWITCHING CHARACTERISTICS

Symbol Parameter Test Condition Min. Max. Unit

VDR VDD for Data Retention See Data Retention Waveform 1.2 3. 6 V

IDR Data Retention Current VDD = 1.2V, CS1 ≥ VDD – 0.2V — 20 µA

tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform tRC —ns

DATA RETENTION WAVEFORM (CS1 Controlled)

®

Data Retention Mode

CS1 ≥ V

1.65V

1.4V

GND

V

V

CS1

SDR

t

DD

DR

DATA RETENTION WAVEFORM (CS2 Controlled)

Data Retention Mode

V

DD

3.0
t

SDR

2.2V

CE2
V

DR

0.4V

DD

- 0.2V

CS2 ≤ 0.2V

t

RDR

t

RDR

GND

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IS62WV51216ALL, IS62WV51216BLL ISSI

ORDERING INFORMATION
IS62WV51216ALL (1.65V - 2.2V)

Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

70 IS62WV51216ALL-70TI TSOP-II

IS62WV51216ALL-70BI mini BGA (7.2mm x 8.7mm)
IS62WV51216ALL-70XI DIE

ORDERING INFORMATION
IS62WV51216BLL (2.5V - 3.6V)

Commercial Range: 0°C to +70°C

®

Speed (ns) Order Part No. Package

45 IS62WV51216BLL-45B mini BGA (7.2mm x 8.7mm)

Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

55 IS62WV51216BLL-55TI TSOP-II

70 IS62WV51216BLL-70XI DIE

IS62WV51216BLL-55TLI TSOP-II, Lead-free
IS62WV51216BLL-55BI mini BGA (7.2mm x 8.7mm)
IS62WV51216BLL-55BLI mini BGA (7.2mm x 8.7mm), Lead-free

14

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IS62WV51216ALL, IS62WV51216BLL ISSI

Mini Ball Grid Array
Package Code: B (48-pin)

Top View Bottom View

φ b (48x)

6 5 4 3 2 11 2 3 4 5 6

®

A
B
C
D

D

E
F
G
H

A2

SEATING PLANE

mBGA - 7.2mm x 8.7mm

A1

e

D1

e

E1E

A

A
B
C
D
E
F
G
H

Notes:

1. Controlling dimensions are in millimeters.

MILLIMETERS INCHES

Sym. M i n. Typ. Max. Min. Typ. Max.

N0.
Leads 48

A — — 1.20 — — 0.047

A1 0 .24 — 0.30 0.009 — 0.012

A2 0.60 — — 0.024 — —

D 8.60 8.70 8.80 0.339 0.343 0.346

D1 5.25BSC 0.207BSC

E 7.10 7.20 7.30 0.280 0.283 0.287

E1 3.75BSC 0.148BSC

e 0.75BSC 0.030BSC

b 0.30 0.35 0.40 0.012 0.014 0.016

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PACKAGING INFORMATION ISSI

Plastic TSOP
Package Code: T (Type II)

®

N/2+1N

E

E1

1

N/2

Notes:

1. Controlling dimension: millimieters,
unless otherwise specified.

2. BSC = Basic lead spacing
between centers.

3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the

bottom of the package.

4. Formed leads shall be planar with
respect to one another within

0.004 inches at the seating plane.

D

SEATING PLANE

A

ZD

.

e

b

A1

L

α

C

Plastic TSOP (T - Type II)

Millimeters Inches Millimeters Inches Millimeters Inches

Symbol Min Max Min Max Min Max Min Max Min Max Min Max

Ref. Std.

No. Leads (N) 32 44 50

A — 1.20 — 0.047 — 1.20 — 0.047 — 1.20 — 0.047

A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006

b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018
C 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008
D 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830

E1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405

E 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471

e 1.27 BSC 0.050 BSC 0.80 BSC 0.032 BSC 0.80 BSC 0.031 BSC

L 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024

ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF

α 0° 5° 0° 5° 0° 5° 0° 5° 0° 5° 0° 5°

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. F

06/18/03