Datasheet IS62VV51216LL-85MI, IS62VV51216LL-70M, IS62VV51216LL-85M, IS62VV51216LL-70MI Datasheet (ISSI)

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

PRELIMINARY INFORMATION Rev. 00B

01/10/01

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

IS62VV51216LL ISSI

®

512K x 16 LOW VOLTAGE, 1.8V ULTRA
LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access time: 70, 85 ns

• CMOS low power operation

– 36 mW (typical) operating

– 9 µW (typical) CMOS standby

• TTL compatible interface levels

• Single 1.65V-1.95V V

CC power supply

• Fully static operation: no clock or refresh
required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Available in 48-pin mini BGA (7.2mm x 8.7mm)

DESCRIPTION

The

ISSI

IS62VV51216LL is a high-speed, 8M bit static
RAMs organized as 512K words by 16 bits. It is fabricated
using

ISSI

's high-performance CMOS technology. This
highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices.

For the IS62VV51216LL, when CS1 is HIGH (deselected)
or when CS2 is LOW (deselected) or when CS1 is LOW,
CS2 is HIGH and both LB and UB are HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.

The IS62VV51216LL is packaged in the JEDEC standard
48-pin mini BGA (7.2mm x 8.7mm).

FUNCTIONAL BLOCK DIAGRAM

PRELIMINARY INFORMATION

DECEMBER 2000

A0-A18

CS1

OE

WE

512K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB

CS2

2

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PRELIMINARY INFORMATION Rev. 00B

01/10/01

IS62VV51216LL ISSI

®

PIN CONFIGURATIONS

48-Pin mini BGA (7.2mm x 8.7mm)

TRUTH TABLE

I/O PIN

Mode WE CS1 CS2 OE LB UB I/O0-I/O7 I/O8-I/O15 Vcc Current

Not Selected X H XXXX High-Z High-Z ISB1, ISB2

X X L X X X High-Z High-Z ISB1, ISB2
XXXXHH High-Z High-Z ISB1, ISB2

Output Disabled H L H H L X High-Z High-Z ICC

H L H H X L High-Z High-Z ICC

Read H L H L L H DOUT High-Z ICC

H L H L H L High-Z DOUT
HLHLLL DOUT DOUT

Write L L H X L H DIN High-Z ICC

L L H X H L High-Z DIN
LLHXLL DIN DIN

PIN DESCRIPTIONS

A0-A18 Address Inputs

I/O0-I/O15 Data Inputs/Outputs

CS1, CS2 Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)

NC No Connection

Vcc Power

GND Ground

1 2 3 4 5 6

A

B

C

D

E

F

G

H

LB

OE

A0

A1

A2

CS2

I/O

8

UB A3

A4

CS1 I/O

0

I/O

9

I/O10A5

A6

I/O1I/O

2

GND

I/O

11

A17

A7

I/O

3

Vcc

Vcc

I/O

12

V

SS

A16

I/O

4

GND

I/O

14

I/O

13

A14

A15

I/O

5

I/O

6

I/O

15

NC

A12

A13

WE

I/O

7

A18

A8

A9

A10

A11 NC

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3

PRELIMINARY INFORMATION Rev. 00B

01/10/01

IS62VV51216LL ISSI

®

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage IOH = -0.1 mA 1.4 — V

VOL Output LOW Voltage IOL = 0.1 mA — 0.2 V

VIH Input HIGH Voltage 1.4 VCC + 0.2 V

VIL

(1)

Input LOW Voltage –0.3 0.4 V

ILI Input Leakage GND ≤ VIN ≤ VCC –11µA

ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –11µA

Notes:

1. VIL (min.) = –1.0V for pulse width less than 10 ns.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.2 to Vcc+0.3 V

TBIAS Temperature Under Bias –40 to +85 °C

VCC Vcc Related to GND –0.2 to +2.6 V

TSTG Storage Temperature –65 to +150 °C

PT Power Dissipation 1.0 W

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 1.65V - 1.95V

Industrial –40°C to +85°C 1.65V - 1.95V

CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 8 pF

COUT Input/Output Capacitance VOUT = 0V 10 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

01/10/01

IS62VV51216LL ISSI

®

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0.4V to VCC - 0.2V

Input Rise and Fall Times 5 ns

Input and Output Timing 0.9V
and Reference Level

Output Load See Figures 1 and 2

AC TEST LOADS

3070 Ω

30 pF

Including

jig and

scope

3150 Ω

OUTPUT

1.8V

Figure 1

3070 Ω

5 pF

Including

jig and

scope

3150 Ω

OUTPUT

1.8V

Figure 2

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5

PRELIMINARY INFORMATION Rev. 00B

01/10/01

IS62VV51216LL ISSI

®

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-70 -85 -100

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 70 — 85 — 100 — ns

tAA Address Access Time — 70 — 85 — 100 ns

tOHA Output Hold Time 10 — 10 — 10 — ns
tACS1 CS1 Access Time — 70 — 85 — 100 ns
tDOE OE Access Time — 35 — 40 — 50 ns

tHZOE

(2)

OE to High-Z Output — 25 — 25 — 30 ns

tLZOE

(2)

OE to Low-Z Output 5 — 5 — 5 — ns

tHZCS1

(2)

CS1 to High-Z Output 0 25 0 25 0 30 ns

tLZCS1

(2)

CS1 to Low-Z Output 10 — 10 — 10 — ns

tBA LB, UB Access Time — 70 — 85 — 100 ns
tHZB LB, UB to High-Z Output 0 25 0 25 0 35 ns
tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and
output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

IS62VV51216LL POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-70 -85 -100

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

I

CC Vcc Dynamic Operating VCC = Max., Com. — 20 — 15 — 10 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 25 — 20 — 15

I

CC1 Operating Supply VCC = Max., Com. — 3 — 3 — 3mA

Current IOUT = 0 mA, f = 0 Ind. — 3 — 3 — 3

I

SB1 TTL Standby Current VCC = Max., Com. — 0.3 — 0.3 — 0.3 mA

(TTL Inputs) VIN = VIH or VIL Ind. — 0.3 — 0.3 — 0.3

CS1 = VIH , CS2 = VIL,
f = 1 MHZ

OR

ULB Control

VCC = Max., VIN = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH

ISB2 CMOS Standby VCC = Max., Com. — 10 — 10 — 10 µA

Current (CMOS Inputs) CS1 ≥ VCC – 0.2V, Ind. — 10 — 10 — 10

CS2

≤ 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0

OR

ULB Control VCC = Max., CS1 = VIL

VIN ≤ 0.2V, f = 0; UB / LB = VCC – 0.2V

Note:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

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PRELIMINARY INFORMATION Rev. 00B

01/10/01

IS62VV51216LL ISSI

®

DATA VALID

PREVIOUS DATA VALID

tAA

tOHA

tOHA

tRC

DOUT

ADDRESS

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (CS1 = OE = VIL, UB or LB = VIL)

t

RC

t

OHA

t

AA

t

DOE

t

LZOE

t

ACS1/tACS2

t

LZCS1/

t

LZCS2

t

HZOE

HIGH-Z

DATA VALID

t

HZCS1

ADDRESS

OE

CS1

CS2

DOUT

LB, UB

t

HZB

t

BA

t

LZB

AC WAVEFORMS

READ CYCLE NO. 2

(1,3)

(CS1, OE, AND UB/LB Controlled)

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CS1, UB, or LB = V

IL.

3. Address is valid prior to or coincident with CS1 LOW transition.

Integrated Silicon Solution, Inc. — 1-800-379-4774

7

PRELIMINARY INFORMATION Rev. 00B

01/10/01

IS62VV51216LL ISSI

®

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,2)

(Over Operating Range)

-70 -85 -100

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 70 — 85 — 100 — ns
tSCS1 CS1 to Write End 60 — 70 — 80 — ns

tAW Address Setup Time to Write End 60 — 70 — 80 — ns

tHA Address Hold from Write End 0 — 0 — 0 — ns

tSA Address Setup Time 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 60 — 70 — 80 — ns
tPWE WE Pulse Width 50 — 60 — 80 — ns

tSD Data Setup to Write End 30 — 35 — 40 — ns

tHD Data Hold from Write End 0 — 0 — 0 — ns

tHZWE

(3)

WE LOW to High-Z Output — 20 — 25 — 30 ns

tLZWE

(3)

WE HIGH to Low-Z Output 5 — 5 — 5 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and
output loading specified in Figure 1.

2.

The internal write time is defined by the overlap of CS1 LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to

terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 and WE inputs and at least one
of the LB and UB inputs being in the LOW state.

2. WRITE = (CS1) [ (LB) = (UB) ] (WE).

AC WAVEFORMS

WRITE CYCLE NO. 1

(1,2)

(CS1 Controlled, OE = HIGH or LOW)

DATA-IN VALID

DATA UNDEFINED

t

WC

t

SCS1

t

SCS2

t

AW

t

HA

t

PWE

(4)

t

HZWE

HIGH-Z

t

LZWE

t

SA

t

SD

t

HD

ADDRESS

CS1

CS2

WE

DOUT

DIN

LB, UB

8

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

01/10/01

IS62VV51216LL ISSI

®

WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

DATA-IN VALID

DATA UNDEFINED

t

WC

t

SCS1

t

SCS2

t

AW

t

HA

t

PWE1, 2

t

HZWE

HIGH-Z

t

LZWE

t

SA

t

SD

t

HD

ADDRESS

OE

CS1

CS2

WE

LB, UB

DOUT

DIN

DATA-IN VALID

DATA UNDEFINED

t

WC

t

SCS1

t

SCS2

t

AW

t

HA

t

PWE1, 2

t

HZWE

HIGH-Z

t

LZWE

t

SA

t

SD

t

HD

ADDRESS

OE

CS1

CS2

WE

LB, UB

DOUT

DIN

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9

PRELIMINARY INFORMATION Rev. 00B

01/10/01

IS62VV51216LL ISSI

®

DATA RETENTION SWITCHING CHARACTERISTICS (LL)

Symbol Parameter Test Condition Min. Max. Unit

VDR Vcc for Data Retention See Data Retention Waveform 1.0 2.2 V

IDR Data Retention Current Vcc = 1.0V, CS1 ≥ Vcc – 0.2V — 5µA

tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns

tRDR Recovery Time See Data Retention Waveform tRC — ns

DATA RETENTION WAVEFORM (CS1 Controlled)

VCC

CS1 ≥ VCC - 0.2V

t

SDR tRDR

VDR

CS1

GND

1.65V

1.4V

Data Retention Mode

WRITE CYCLE NO. 4 (UB/LB Controlled)

DATA UNDEFINED

t

WC

ADDRESS 1 ADDRESS 2

t

WC

HIGH-Z

t

PBW

WORD 1

LOW

WORD 2

t

HD

t

SA

t

HZWE

ADDRESS

CS1

UB, LB

WE

D

OUT

DIN

OE

DATA

IN

VALID

t

LZWE

t

SD

t

PBW

DATA

IN

VALID

t

SD

t

HD

t

SA

t

HA

t

HA

UB_CSWR4.eps

HIGH

CS2

10

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

01/10/01

IS62VV51216LL ISSI

®

ISSI

®

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: [phone]
Fax: [phone]

E-mail: [e-mail]

www.issi.com

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

70 IS62VV51216LL-70M Mini BGA (7.2mm x 8.7mm)

85 IS62VV51216LL-85M Mini BGA (7.2mm x 8.7mm)

Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

70 IS62VV51216LL-70MI Mini BGA (7.2mm x 8.7mm)

85 IS62VV51216LL-85MI Mini BGA (7.2mm x 8.7mm)