Datasheet IS62VV25616LL-85T, IS62VV25616LL-85MI, IS62VV25616LL-85M, IS62VV25616LL-70TI, IS62VV25616LL-70T Datasheet (ISSI)

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

PRELIMINARY INFORMATION Rev. 00C

11/30/00

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

IS62VV25616L/LL ISSI

®

256K x 16 LOW VOLTAGE, 1.8V ULTRA
LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access time: 70, 85, 100 ns

• CMOS low power operation

– 36 mW (typical) operating

– 9 µW (typical) CMOS standby

• TTL compatible interface levels

• Single 1.65V-1.95V V

CC power supply

• Fully static operation: no clock or refresh
required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (7.2mm x 8.7mm)

DESCRIPTION

The ISSI IS62VV25616L and IS62VV25616LL are
high-speed, 4,194,304 bit static RAMs organized as
262,144 words by 16 bits. They are fabricated using

ISSI's high-performance CMOS technology. This highly

reliable process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices.

For the IS62VV25616L/LL, when CE is HIGH (deselected)
or CE is low and both LB and UB are HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.

The IS62VV25616L and IS62VV25616LL are packaged in
the JEDEC standard 44-pin TSOP (Type II) and 48-pin
mini BGA (7.2mm x 8.7mm).

FUNCTIONAL BLOCK DIAGRAM

PRELIMINARY INFORMATION

NOVEMBER 2000

A0-A17

CE
OE

WE

256K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00C

11/30/00

IS62VV25616L/LL ISSI

®

PIN CONFIGURATIONS

44-Pin TSOP (Type II) 48-Pin mini BGA (7.2mm x 8.7mm)

TRUTH TABLE

I/O PIN

Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 Vcc Current

Not Selected X H X X X High-Z High-Z ISB1, ISB2

X L X H H High-Z High-Z ISB1, ISB2

Output Disabled H L H X X High-Z High-Z ICC

X L X H H High-Z High-Z ISB1, ISB2

Read H L L L H DOUT High-Z ICC

H L L H L High-Z DOUT
HLLLL DOUT DOUT

Write L L X L H DIN High-Z ICC

L L X H L High-Z DIN
LLXLL DIN DIN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A4
A3
A2
A1
A0

CE

I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

WE

A16
A15
A14
A13
A12

A5
A6
A7

OE
UB
LB

I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A17

PIN DESCRIPTIONS

A0-A17 Address Inputs

I/O0-I/O15 Data Inputs/Outputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input

LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)

NC No Connection

Vcc Power

GND Ground

1 2 3 4 5 6

A

B

C

D

E

F

G

H

LB

OE

A0

A1

A2

N/C

I/O

8

UB A3

A4

CE I/O

0

I/O

9

I/O10A5

A6

I/O1I/O

2

GND

I/O

11

A17

A7

I/O

3

Vcc

Vcc

I/O

12

NC

A16

I/O

4

GND

I/O

14

I/O

13

A14

A15

I/O

5

I/O

6

I/O

15

NC

A12

A13

WE

I/O

7

NC

A8

A9

A10

A11 NC

Integrated Silicon Solution, Inc. — 1-800-379-4774

3

PRELIMINARY INFORMATION Rev. 00C

11/30/00

IS62VV25616L/LL ISSI

®

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage IOH = -0.1 mA 1.4 — V

VOL Output LOW Voltage IOL = 0.1 mA — 0.2 V

VIH Input HIGH Voltage 1.4 VCC + 0.2 V

VIL

(1)

Input LOW Voltage –0.3 0.4 V

ILI Input Leakage GND ≤ VIN ≤ VCC –11µA

ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –11µA

Notes:

1. VIL (min.) = –1.0V for pulse width less than 10 ns.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.2 to Vcc+0.3 V

TBIAS Temperature Under Bias –40 to +85 °C

VCC Vcc Related to GND –0.2 to +2.6 V

TSTG Storage Temperature –65 to +150 °C

PT Power Dissipation 1.0 W

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 1.65V - 1.95V

Industrial –40°C to +85°C 1.65V - 1.95V

CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 8 pF

COUT Input/Output Capacitance VOUT = 0V 10 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00C

11/30/00

IS62VV25616L/LL ISSI

®

IS62VV25616L POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-70 -85 -100

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

ICC

Vcc Dynamic Operating VCC = Max., Com. — 20 — 15 — 10 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 25 — 20 — 15

ICC1

Operating Supply VCC = Max., Com. — 3 — 3 — 3mA
Current IOUT = 0 mA, f = 1 MHZ Ind. — 3 — 3 — 3

ISB1

TTL Standby Current VCC = Max., Com. — 0.3 — 0.3 — 0.3 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 0.3 — 0.3 — 0.3

CE ≥ VIH , f = 0

OR

ULB Control Vcc = Max., VIN = VIH or VIL

CE = VIL, f = 0, UB = VIH, LB = VIH

ISB2

CMOS Standby VCC = Max., Com. — 10 — 10 — 10 µA
Current (CMOS Inputs) CE ≥ VCC – 0.2V, Ind. — 10 — 10 — 10

VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0

OR

ULB Control VCC = Max., CE = VIL

VIN ≤ 0.2V, f = 0; UB / LB = VCC – 0.2V

Note:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0.4V to VCC - 0.2V

Input Rise and Fall Times 5 ns

Input and Output Timing 0.9V
and Reference Level

Output Load See Figures 1 and 2

AC TEST LOADS

3070 Ω

30 pF

Including

jig and

scope

3150 Ω

OUTPUT

1.8V

Figure 1

3070 Ω

5 pF

Including

jig and

scope

3150 Ω

OUTPUT

1.8V

Figure 2

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5

PRELIMINARY INFORMATION Rev. 00C

11/30/00

IS62VV25616L/LL ISSI

®

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-70 -85 -100

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 70 — 85 — 100 — ns

tAA Address Access Time — 70 — 85 — 100 ns

tOHA Output Hold Time 10 — 10 — 10 — ns
tACE CE Access Time — 70 — 85 — 100 ns
tDOE OE Access Time — 35 — 40 — 50 ns

tHZOE

(2)

OE to High-Z Output — 25 — 25 — 30 ns

tLZOE

(2)

OE to Low-Z Output 5 — 5 — 5 — ns

tHZCE

(2)

CE to High-Z Output 0 25 0 25 0 30 ns

tLZCE

(2)

CE to Low-Z Output 10 — 10 — 10 — ns

tBA LB, UB Access Time — 70 — 85 — 100 ns
tHZB LB, UB to High-Z Output 0 25 0 25 0 35 ns
tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and
output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

IS62VV25616LL POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-70 -85 -100

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

I

CC Vcc Dynamic Operating VCC = Max., Com. — 20 — 15 — 10 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 25 — 20 — 15

I

CC1 Operating Supply V CC = Max., Com. — 3 — 3 — 3mA

Current IOUT = 0 mA, f = 0 Ind. — 3 — 3 — 3

I

SB1 TTL Standby Current VCC = Max., Com. — 0.3 — 0.3 — 0.3 mA

(TTL Inputs) VIN = VIH or VIL Ind. — 0.3 — 0.3 — 0.3

CE ≥ VIH , f = 1 MHZ

OR

ULB Control

VCC = Max., VIN = VIH or VIL
CE = VIL, f = 0, UB = VIH, LB = VIH

ISB2 CMOS Standby VCC = Max., Com. — 5 — 5 — 5µA

Current (CMOS Inputs) CE

≥

VCC – 0.2V, Ind. — 5 — 5 — 5
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0

OR

ULB Control VCC = Max., CE = VIL

VIN ≤ 0.2V, f = 0; UB / LB = VCC – 0.2V

Note:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00C

11/30/00

IS62VV25616L/LL ISSI

®

DATA VALID

PREVIOUS DATA VALID

tAA

tOHA

tOHA

tRC

DOUT

ADDRESS

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (CE = OE = VIL, UB or LB = VIL)

tRC

tOHA

tAA

tDOE

tLZOE

tACE

tLZCE

tHZOE

HIGH-Z

DATA VALID

tHZB

ADDRESS

OE

CE

LB, UB

D

OUT

tHZCE

tBA

tLZB

AC WAVEFORMS

READ CYCLE NO. 2

(1,3)

(CE, OE, AND UB/LB Controlled)

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE, UB, or LB = V

IL.

3. Address is valid prior to or coincident with CE LOW transition.

Integrated Silicon Solution, Inc. — 1-800-379-4774

7

PRELIMINARY INFORMATION Rev. 00C

11/30/00

IS62VV25616L/LL ISSI

®

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,2)

(Over Operating Range)

-70 -85 -100

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 70 — 85 — 100 — ns
tSCE CE to Write End 65 — 70 — 80 — ns

tAW Address Setup Time to Write End 65 — 70 — 80 — ns

tHA Address Hold from Write End 0 — 0 — 0 — ns

tSA Address Setup Time 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 60 — 70 — 80 — ns
tPWE WE Pulse Width 55 — 60 — 80 — ns

tSD Data Setup to Write End 30 — 35 — 40 — ns

tHD Data Hold from Write End 0 — 0 — 0 — ns

tHZWE

(3)

WE LOW to High-Z Output — 30 — 30 — 40 ns

tLZWE

(3)

WE HIGH to Low-Z Output 5 — 5 — 5 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and
output loading specified in Figure 1.

2.

The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to

terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.

2. WRITE = (CE) [ (LB) = (UB) ] (WE).

AC WAVEFORMS

WRITE CYCLE NO. 1

(1,2)

(CE Controlled, OE = HIGH or LOW)

DATA UNDEFINED

t

WC

VALID ADDRESS

t

SCS

t

PWE1

t

PWE2

t

AW

t

HA

HIGH-Z

t

PBW

t

HD

t

SA

t

HZWE

ADDRESS

CE

UB, LB

WE

D

OUT

D

IN

DATA

IN

VALID

t

LZWE

t

SD

UB_CSWR1.eps

8

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00C

11/30/00

IS62VV25616L/LL ISSI

®

WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)

DATA UNDEFINED

LOW

t

WC

VALID ADDRESS

t

PWE1

t

AW

t

HA

HIGH-Z

t

PBW

t

HD

t

SA

t

HZWE

ADDRESS

CE

UB, LB

WE

D

OUT

D

IN

OE

DATAIN VALID

t

LZWE

t

SD

UB_CSWR2.eps

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

DATA UNDEFINED

t

WC

VALID ADDRESS

LOW

LOW

t

PWE2

t

AW

t

HA

HIGH-Z

t

PBW

t

HD

t

SA

t

HZWE

ADDRESS

CE

UB, LB

WE

D

OUT

DIN

OE

DATAIN VALID

t

LZWE

t

SD

UB_CSWR3.eps

Integrated Silicon Solution, Inc. — 1-800-379-4774

9

PRELIMINARY INFORMATION Rev. 00C

11/30/00

IS62VV25616L/LL ISSI

®

DATA RETENTION SWITCHING CHARACTERISTICS (L/LL)

Symbol Parameter Test Condition Min. Max. Unit

VDR Vcc for Data Retention See Data Retention Waveform 1.0 2.2 V

IDR Data Retention Current Vcc = 1.0V, CE ≥ Vcc – 0.2V — 15 µA (For -L version)

— 5 (For -LL version)

tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns

tRDR Recovery Time See Data Retention Waveform tRC — ns

DATA RETENTION WAVEFORM (CE Controlled)

VCC

CE ≥ VCC - 0.2V

t

SDR tRDR

VDR

CE

GND

1.65V

1.4V

Data Retention Mode

WRITE CYCLE NO. 4 (UB/LB Controlled)

DATA UNDEFINED

t

WC

ADDRESS 1 ADDRESS 2

t

WC

HIGH-Z

t

PBW

WORD 1

LOW

WORD 2

t

HD

t

SA

t

HZWE

ADDRESS

CE

UB, LB

WE

D

OUT

D

IN

OE

DATA

IN

VALID

t

LZWE

t

SD

t

PBW

DATA

IN

VALID

t

SD

t

HD

t

SA

t

HA

t

HA

UB_CSWR4.eps

10

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00C

11/30/00

IS62VV25616L/LL ISSI

®

ISSI

®

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: [phone]
Fax: [phone]

E-mail: [e-mail]

www.issi.com

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

70 IS62VV25616L-70T TSOP (Type II)

IS62VV25616L-70M Mini BGA

(7.2mm x 8.7mm)

85 IS62VV25616L-85T TSOP (Type II)

IS62VV25616L-85M Mini BGA

(7.2mm x 8.7mm)

100 IS62VV25616L-10T TSOP (Type II)

IS62VV25616L-10M Mini BGA

(7.2mm x 8.7mm)

Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

70 IS62VV25616L-70TI TSOP (Type II)

IS62VV25616L-70MI Mini BGA

(7.2mm x 8.7mm)

85 IS62VV25616L-85TI TSOP (Type II)

IS62VV25616L-85MI Mini BGA

(7.2mm x 8.7mm)

100 IS62VV25616L-10TI TSOP (Type II)

IS62VV25616L-10MI Mini BGA

(7.2mm x 8.7mm)

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

70 IS62VV25616LL-70T TSOP (Type II)

IS62VV25616LL-70M Mini BGA

(7.2mm x 8.7mm)

85 IS62VV25616LL-85T TSOP (Type II)

IS62VV25616LL-85M Mini BGA

(7.2mm x 8.7mm)

100 IS62VV25616LL-10T TSOP (Type II)

IS62VV25616LL-10M Mini BGA

(7.2mm x 8.7mm)

Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

70 IS62VV25616LL-70TI TSOP (Type II)

IS62VV25616LL-70MI Mini BGA

(7.2mm x 8.7mm)

85 IS62VV25616LL-85TI TSOP (Type II)

IS62VV25616LL-85MI Mini BGA

(7.2mm x 8.7mm)

100 IS62VV25616LL-10TI TSOP (Type II)

IS62VV25616LL-10MI Mini BGA

(7.2mm x 8.7mm)