Datasheet IS62V6416BLL-12TI, IS62V6416BLL-12T, IS62V6416BLL-12KI, IS62V6416BLL-12K, IS62V6416BLL-12BI Datasheet (ISSI)

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. A

03/17/00

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

IS62V6416BLL ISSI

®

FEATURES

• Access time: 100 and 120 ns

• CMOS low power operation

• TTL compatible interface levels

• Single 2.7V-3.3V power supply

• Fully static operation: no clock or refresh
required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Available in Jedec Std 44-pin SOJ package,
44-pin TSOP (Type II), and 48-pin mini BGA

64K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM

DESCRIPTION

The ISSI IS62V6416BLL is an ultra-low power, 1,048,576-bit
static RAM organized as 65,536 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques yields access times as fast as 100 ns with
low power consumption.

When CS is HIGH (deselected) or when CS is LOW and both
LB and UB are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced down with CMOS
input levels.

Easy memory expansion is provided by using Chip Select and
Output Enable inputs, CS and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB) access.

FUNCTIONAL BLOCK DIAGRAM

MARCH 2000

A0-A15

CS

OE
WE

64K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB

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Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

03/17/00

IS62V6416BLL ISSI

®

PIN DESCRIPTIONS

A0-A15 Address Inputs

I/O0-I/O15 Data Inputs/Outputs

CS Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)

NC No Connection

Vcc Power

GND Ground

48-Pin mini BGA (Top View)

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7
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12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A4
A3
A2
A1
A0

CS
I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

WE
A15
A14
A13
A12

NC

A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC

PIN CONFIGURATIONS

44-Pin SOJ 44-Pin TSOP

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2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A4

A3

A2

A1

A0

CS

I/O0

I/O1

I/O2

I/O3

Vcc

GND

I/O4

I/O5

I/O6

I/O7

WE

A15

A14

A13

A12

NC

A5

A6

A7

OE

UB

LB

I/O15

I/O14

I/O13

I/O12

GND

Vcc

I/O11

I/O10

I/O9

I/O8

NC

A8

A9

A10

A11

NC

1 2 3 4 5 6

A

B

C

D

E

F

G

H

LB

OE

A0

A1

A2

N/C

UB A3

A4

CS

I/O

0

A5

A6

GND

NC

A7

Vcc

Vcc

NC

NC

GND

I/O

14

I/O

15

I/O

13

I/O

12

I/O

11

I/O

10

I/O

1

I/O

3

I/O

2

I/O

5

I/O

4

I/O

6

I/O

7

I/O

9

I/O

8

A14

A15

NC

A12

A13

WE

NC

A8

A9

A10

A11 NC

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Integrated Silicon Solution, Inc. — 1-800-379-4774

3

Rev. A

03/17/00

IS62V6416BLL ISSI

®

TRUTH TABLE

I/O Pin

Mode WE CS OE LB UB I/O0-I/O7 I/O8-I/O15 Vcc Current

Not Selected X H X X X High-Z High-Z ISB1, ISB2

X L X H H High-Z High-Z ISB1, ISB2

Output Disabled H L H L L High-Z High-Z ICC

Read H L L L H DOUT High-Z ICC

H L L H L High-Z DOUT
HLLLL DOUT DOUT

Write L L X L H DIN High-Z ICC

L L X H L High-Z DIN
LLXLL DIN DIN

AC TEST LOADS

Figure 1.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0 to 3V

(1)

Input Rise and Fall Times 5 ns
Input and Output Timing and Reference Level 1.5V

(1)

Output Load See Figures 1 and 2

1076 Ω

30 pF

Including

jig and

scope

1262 Ω

OUTPUT

3V

1076 Ω

5 pF

Including

jig and

scope

1262 Ω

OUTPUT

3V

Figure 2.

Figure 3.

581 Ω

THEVENIN EQUIVALENT

OUTPUT 1.61V

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Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

03/17/00

IS62V6416BLL ISSI

®

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 2.7V (Min.) to 3.3V (Max.)

Industrial –40°C to +85°C 2.7V (Min.) to 3.3V (Max.)

DC ELECTRICAL CHARACTERISTICS (Over Operating Range Unless Otherwise Specified)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –1 mA 2.2 — V

VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V

VIH Input HIGH Voltage 2.0 VCC + 0.3 V

VIL

(1)

Input LOW Voltage –0.2 0.4 V

ILI Input Leakage GND ≤ VIN ≤ VCC –11µA

ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –11µA

Note:

1. V

IL (min.) = –1.5V for pulse width less than 30 ns.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to Vcc +0.5 V

TSTG Storage Temperature –65 to +150 °C

PT Power Dissipation 1.5 W

IOUT DC Output Current (LOW) 20 mA

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

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Rev. A

03/17/00

IS62V6416BLL ISSI

®

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range Unless Otherwise Specified)

-100 -120

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

ICC Vcc Dynamic VCC = Max., Com. — 35 — 30 mA

Operating IOUT = 0 mA, f = fMAX Ind. — 45 — 40
Supply Current CS = VIH

ISB1 TTL Standby VCC = Max., Com. — 0.3 — 0.3 mA

Current VIN = VIH or VIL Ind. — 0.3 — 0.3
(TTL Inputs) CS ≥ VIH, f = 0

OR

ULB Control VCC = Max., VIN = VIH or VIL

CS = VIL, f = 0, UB = VIH, LB = VIH

ISB2 CMOS Standby VCC = Max., Com. — 5 — 5µA

Current CS ≥ VCC – 0.2V Ind. — 5 — 5
(CMOS Inputs) VIN ≤ 0.2V, f = 0

OR

ULB Control

VCC = Max., CS = VIL
VIN ≤ 0.2V, f = 0; UB / LB = VCC – 0.2V

Note:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency; f = 0 means no input lines change.

CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 8 pF

COUT Input/Output Capacitance VOUT = 0V 10 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

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Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

03/17/00

IS62V6416BLL ISSI

®

DATA VALID

READ1.eps

PREVIOUS DATA VALID

t

AA

t

OHA

t

OHA

t

RC

D

OUT

ADDRESS

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (CS = OE = VIL, UB or LB = VIL)

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-100 -120

Symbol Parameter Min. Max. Min. Max. Unit

tRC Read Cycle Time 100 — 120 — ns

tAA Address Access Time — 100 — 120 ns

tOHA Output Hold Time 10 — 10 — ns
tACS CS Access Time — 100 — 120 ns
tDOE OE Access Time — 50 — 70 ns

tHZOE

(2)

OE to High-Z Output 0 30 0 35 ns

tLZOE

(2)

OE to Low-Z Output 5 — 5 — ns

tHZCS

(2)

CS to High-Z Output 0 30 0 35 ns

tLZCS

(2)

CS to Low-Z Output 10 — 10 — ns

tBA LB, UB Access Time — 100 — 120 ns

tHZB

(2)

LB, UB to High-Z Output 0 40 0 45 ns

tLZB

(2)

LB, UB to Low-Z Output 10 — 10 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500mV from steady-state voltage. Not 100% tested.

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7

Rev. A

03/17/00

IS62V6416BLL ISSI

®

t

RC

t

OHA

t

AA

t

DOE

t

LZOE

t

ACS

t

LZCS

t

HZOE

HIGH-Z

DATA VALID

t

HZB

ADDRESS

OE

CS

LB, UB

D

OUT

t

HZCS

t

BA

t

LZB

UB_CSRD2.eps

READ CYCLE NO. 2

(1,3)

(CS, OE, and UB / LB Controlled)

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CS, UB, or LB = V

IL.

3. Address is valid prior to or coincident with CS LOW transition.

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Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

03/17/00

IS62V6416BLL ISSI

®

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,2)

(Over Operating Range)

-100 -120

Symbol Parameter Min. Max. Min. Max. Unit

tWC Write Cycle Time 100 — 120 — ns
tSCS CS to Write End 80 — 100 — ns

tAW Address Setup Time to Write End 80 — 100 — ns

tHA Address Hold from Write End 0 — 0 — ns

tSA Address Setup Time 0 — 0 — ns
tPWB LB, UB Valid to End of Write 80 — 100 — ns
tPWE1,2 WE Pulse Width 80 — 100 — ns

tSD Data Setup to Write End 60 — 60 — ns

tHD Data Hold from Write End 0 — 0 — ns

tHZWE

(3)

WE LOW to High-Z Output 0 30 0 — ns

tLZWE

(3)

WE HIGH to Low-Z Output 5 — 5 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CS LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least one of
the LB and UB inputs being in the LOW state.

2. WRITE = (CS) [ (LB) = (UB) ] (WE).

WRITE CYCLE NO. 1

(1,2)

(CS Controlled, OE = HIGH or LOW)

DATA UNDEFINED

t

WC

VALID ADDRESS

t

SCS

t

PWE1

t

PWE2

t

AW

t

HA

HIGH-Z

t

PBW

t

HD

t

SA

t

HZWE

ADDRESS

CS

UB, LB

WE

D

OUT

DIN

DATAIN VALID

t

LZWE

t

SD

UB_CSWR1.eps

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Integrated Silicon Solution, Inc. — 1-800-379-4774

9

Rev. A

03/17/00

IS62V6416BLL ISSI

®

WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)

DATA UNDEFINED

LOW

t

WC

VALID ADDRESS

t

PWE1

t

AW

t

HA

HIGH-Z

t

PBW

t

HD

t

SA

t

HZWE

ADDRESS

CS

UB, LB

WE

D

OUT

D

IN

OE

DATAIN VALID

t

LZWE

t

SD

UB_CSWR2.eps

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

DATA UNDEFINED

t

WC

VALID ADDRESS

LOW

LOW

t

PWE2

t

AW

t

HA

HIGH-Z

t

PBW

t

HD

t

SA

t

HZWE

ADDRESS

CS

UB, LB

WE

D

OUT

D

IN

OE

DATAIN VALID

t

LZWE

t

SD

UB_CSWR3.eps

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Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

03/17/00

IS62V6416BLL ISSI

®

WRITE CYCLE NO. 4 (UB/LB Controlled)

DATA UNDEFINED

t

WC

ADDRESS 1 ADDRESS 2

t

WC

HIGH-Z

t

PBW

WORD 1

LOW

WORD 2

t

HD

t

SA

t

HZWE

ADDRESS

CS

UB, LB

WE

D

OUT

D

IN

OE

DATA

IN

VALID

t

LZWE

t

SD

t

PBW

DATA

IN

VALID

t

SD

t

HD

t

SA

t

HA

t

HA

UB_CSWR4.eps

DATA RETENTION TIMING DIAGRAM

DATA RETENTION CHARACTERISTICS

Symbol Parameter Test Condition Min. Max. Unit

V

DR

Vcc for Data Retention CS ≥ VCC – 0.2V 2.0 — V

I

DR

Data Retention Current VCC = V

DR

— 5.0 µA

CS ≥ VCC – 0.2V

t

SDR

Data Retention Set up Time

See Data Retention Waveform

0 — ns

t

RDR

Recovery Time

See Data Retention Waveform t

RC

— ns

V

CC

CS ≥ V

CC

– 0.2V

t

SDR

t

RDR

V

DR

CS

GND

Data Retention Mode

CS_DR.eps

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Integrated Silicon Solution, Inc. — 1-800-379-4774

11

Rev. A

03/17/00

IS62V6416BLL ISSI

®

ISSI

®

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: [phone]
Fax: [phone]

E-mail: [e-mail]

www.issi.com

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

100 IS62V6416BLL-10T Plastic TSOP (Type II)

IS62V6416BLL-10K 400-mil Plastic SOJ
IS62V6416BLL-10B Mini BGA (6mm x 8mm)

120 IS62V6416BLL-12T Plastic TSOP (Type II)

IS62V6416BLL-12K 400-mil Plastic SOJ
IS62V6416BLL-12B Mini BGA (6mm x 8mm)

Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

100 IS62V6416BLL-10TI Plastic TSOP (Type II)

IS62V6416BLL-10KI 400-mil Plastic SOJ
IS62V6416BLL-10BI Mini BGA (6mm x 8mm)

120 IS62V6416BLL-12TI Plastic TSOP (Type II)

IS62V6416BLL-12KI 400-mil Plastic SOJ
IS62V6416BLL-12BI Mini BGA (6mm x 8mm)