Datasheet IS62LV5128LL-85BI, IS62LV5128LL-70B, IS62LV5128LL-85B, IS62LV5128LL-70BI Datasheet (ISSI)

®

IS62LV5128LL

512K x 8 LOW POWER and LOW Vcc
CMOS STATIC RAM

FEATURES

• Access times of 70, 85 ns

• CMOS low power operation:
— 135 mW (typical) operating
— 16.5 µW (typical) standby

• Low data retention voltage: 2V (min.)

• Output Enable (OE) and Chip Enable
(CE) inputs for ease in applications

• TTL compatible inputs and outputs

• Fully static operation:
— No clock or refresh required

Single 2.7V (min) to 3.15V (max) VCC power supply

•

• Available in 36-pin mini BGA

DESCRIPTION

The

ISSI

8 bits, CMOS SRAM. It is fabricated using
six transistor (6T),
satisfy the demands of the state-of-the-art technologies
such as cell phones and pagers.

When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation
down with CMOS input levels. Additionally, easy memory
expansion is provided by using Chip Enable and Output
Enable inputs, CE and OE. The active LOW Write Enable (WE)
controls both writing and reading of the memory.

The IS62LV5128LL is available in a 36-pin mini BGA
package (8mm x 10mm).

ISSI

MAY 2001

IS62LV5128LL is a low voltage, 524,288 words by

ISSI

’

s low

voltage,

CMOS technology.

The device

can be reduced

is

targeted

to

FUNCTIONAL BLOCK DIAGRAM

A0-A18

VCC

GND

I/O0-I/O7

CE

OE
WE

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

512K x 8

MEMORY ARRAY

COLUMN I/O

ISSI

reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any

errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01

1

IS62LV5128LL

PIN CONFIGURATION

ISSI

®

36-pin mini BGA (B)

1 2 3 4 5 6

A

B

C

D

E

F

G

H

A0

I/O4

I/O5

GND

Vcc

I/O6

I/O7

A9

A1

A2

OE

A10

NC

WE

NC

A18

CE

A11

A3

A4

A5

A17

A16

A12

A6

A7

A15

A13

A8

I/O0

I/O1

Vcc

GND

I/O2

I/O3

A14

PIN DESCRIPTIONS

A0-A18 Address Inputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input

I/O0-I/O7 Input/Output

NC No Connection

Vcc Power

GND Ground

TRUTH TABLE

Mode WE CE OE I/O Operation Vcc Current

Not Selected X H X High-Z ISB1, ISB2
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC

OPERATING RANGE

Range Ambient Temperature VCC Min. VCC Max.

Commercial 0°C to +70°C 2.7V 3.15V

Industrial –40°C to +85°C 2.7V 3.15V

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01

IS62LV5128LL

ISSI

®

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.3 V
VCC Vcc related to GND –0.3 to +3.3 V
TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1 W

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

CAPACITANCE

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF

COUT Output Capacitance VOUT = 0V 8 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

(1,2)

A = 25°C, f = 1 MHz, Vcc = 3.0V.

(1)

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = 3.0V, IOH = –1.0 mA 2.2 — V
VOL Output LOW Voltage VCC = 3.0V, IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC –11µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, OUTPUTS Disabled –11µA

Note:

IL = –2.0V for pulse width less than 10 ns.

1. V

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01

(1)

–0.2 0.4 V

3

IS62LV5128LL

ISSI

®

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

ICC Vcc Dynamic VCC = Max., CE = VIL Com. — 40 — 35 mA

Operating IOUT = 0 mA, f = fMAX Ind. — 45 — 40
Supply Current

CC1

I

ISB1 TTL Standby VCC = Max., Com. — 0.4 — 0.4 mA

ISB2 CMOS Standby VCC = Max., f = 0 Com. — 10 — 10 µA

Note:

1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

Operating Supply VCC = Max., Com. — 5 — 5mA
Current IOUT = 0 mA, f = 0 Ind. — 5 — 5

Current VIN = VIH or VIL,Ind.— 1.0 — 1.0
(TTL Inputs) CE1 ≥ VIH, f = 0

Current CE1 ≥ VCC – 0.2V, Ind. — 10 — 10
(CMOS Inputs) or VIN ≥ VCC – 0.2V,

VIN ≤ 0.2V

(1)

(Over Operating Range)

-70 -85

READ CYCLE SWITCHING CHARACTERISTICS

Symbol Parameter Min. Max. Min. Max. Unit

(1)

(Over Operating Range)

-70 -85

tRC Read Cycle Time 70 — 85 — ns

tAA Address Access Time — 70 — 85 ns

tOHA Output Hold Time 10 — 15 — ns
tACE CE Access Time — 70 — 85 ns
tDOE OE Access Time — 35 — 40 ns

(2)

tHZOE

(2)

tLZOE

(2)

tLZCE

(2)

tHZCE

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and
output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

OE to High-Z Output — 25 — 25 ns
OE to Low-Z Output 5 — 5 — ns
CE to Low-Z Output 10 — 10 — ns
CE to High-Z Output 0 25 0 25 ns

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01

IS62LV5128LL

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.5V

and Reference Level
Output Load See Figures 1 and 2

AC TEST LOADS

ISSI

®

3070 Ω

2.8V

OUTPUT

30 pF

Including

jig and

scope

Figure 1 Figure 2

3150 Ω

2.8V

OUTPUT

5 pF

Including

jig and

scope

3070 Ω

3150 Ω

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01

5

IS62LV5128LL

AC WAVEFORMS

READ CYCLE NO. 1

ADDRESS

(1,2)

tRC

ISSI

®

DOUT

READ CYCLE NO. 2

ADDRESS

OE

(1,3)

tAA

tOHA

DATA VALID

t

RC

t

AA

t

OHA

tOHA

t

DOE

t

CE

t

ACE

t

LZCE

DOUT

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE = V

3. Address is valid prior to or coincident with CE LOW transitions.

HIGH-Z

LZOE

IL.

6

t

HZOE

t

HZCE

DATA VALID

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01

IS62LV5128LL

ISSI

®

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range, Standard and Low Power)

-70 -85

Symbol Parameter Min. Max. Min. Max. Unit

tWC Write Cycle Time 70 — 85 — ns
tSCE CE to Write End 65 — 70 — ns

tAW Address Setup Time to Write End 65 — 70 — ns

tHA Address Hold from Write End 0 — 0 — ns

tSA Address Setup Time 0 — 0 — ns

(4)

tPWE

WE Pulse Width 60 — 60 — ns

tSD Data Setup to Write End 30 — 35 — ns

tHD Data Hold from Write End 0 — 0 — ns

(2)

tHZWE

(2)

tLZWE

Notes:

Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1.

1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the

3.
Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.

4. Tested with OE HIGH.

WE LOW to High-Z Output — 33 — 35 ns
WE HIGH to Low-Z Output 5 — 5 — ns

AC WAVEFORMS

WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW)

t

WC

ADDRESS

t

SCE

CE

t

AW

(4)

t

t

HZWE

PWE

HIGH-Z

WE

DOUT

DIN

t

SA

DATA UNDEFINED

t

SD

DATA-IN VALID

t

HA

t

LZWE

t

HD

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01

7

IS62LV5128LL

WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)

t

WC

ADDRESS

OE

t

SCE

CE

t

AW

t

t

HZWE

PWE1, 2

HIGH-Z

t

SD

WE

DOUT

t

SA

DATA UNDEFINED

t

HA

t

LZWE

t

HD

ISSI

®

DIN

DATA-IN VALID

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

t

WC

ADDRESS

OE

t

SCE

CE

t

AW

t

t

HZWE

PWE1, 2

HIGH-Z

WE

DOUT

t

SA

DATA UNDEFINED

t

HA

t

LZWE

t

SD

DIN

8

DATA-IN VALID

Integrated Silicon Solution, Inc. — 1-800-379-4774

t

HD

Rev. D

05/04/01

IS62LV5128LL

ISSI

DATA RETENTION SWITCHING CHARACTERISTICS

Symbol Parameter Test Condition Min. Max. Unit

VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.15 V

DR Data Retention Current Vcc = 2.0V, CE ≥ Vcc – 0.2V Com. — 10 µA

I

Ind. — 10 µA

tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns

tRDR Recovery Time See Data Retention Waveform tRC — ns

DATA RETENTION WAVEFORM (CE Controlled)

®

2.7V

2.0V

GND

V

V

CE

CC

DR

t

SDR

Data Retention Mode

CE ≥ V

CC

- 0.2V

t

RDR

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01

9

IS62LV5128LL

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

70 IS62LV5128LL-70B mini BGA (8mm x 10mm)

85 IS62LV5128LL-85B mini BGA (8mm x 10mm)

Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

70 IS62LV5128LL-70BI mini BGA (8mm x 10mm)

85 IS62LV5128LL-85BI mini BGA (8mm x 10mm)

ISSI

®

10

®

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: [phone]
Fax: [phone]

E-mail: [e-mail]

www.issi.com

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

05/04/01