Datasheet IS62LV256L-25TI, IS62LV256L-25T, IS62LV256L-25JI, IS62LV256L-20TI, IS62LV256L-20T Datasheet (ISSI)
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®
IS62LV256L
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
FEATURES
• High-speed access time: 15, 20, 25 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 255 mW (max.) operating
— 0.18 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
ISSI
APRIL 1999
DESCRIPTION
The ISSI IS62LV256L is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields
access times as fast as 15 ns maximum.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IS62LV256L is available in the JEDEC standard 28-pin
SOJ and the 450-mil TSOP package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VCC
GND
I/O0-I/O7
CE
OE
WE
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
256 X 1024
MEMORY ARRAY
COLUMN I/O
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
SR033-1A
04/27/99
1
IS62LV256L
®
ISSI
PIN CONFIGURATION
28-Pin SOJ
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A14
A12
I/O0
I/O1
I/O2
GND
PIN DESCRIPTIONS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
28-Pin TSOP
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
TRUTH TABLE
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
9
A1
8
A2
A0-A14 Address Inputs
CE
OE
WE
Chip Enable Input
Output Enable Input
Write Enable Input
I/O0-I/O7 Input/Output
Mode
WEWE
WE
WEWE
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC1, ICC2
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2
CECE
CE
CECE
OEOE
OE
OEOE
Vcc Power
GND Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 0.5 W
IOUT DC Output Current (LOW) 20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
I/O Operation Vcc Current
2
Integrated Silicon Solution, Inc.
SR033-1A
04/27/99
IS62LV256L
ISSI
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V +10%
Industrial –40°C to +85°C 3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –2 2 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –2 2 µA
(1)
Ind. –5 5
Ind. –5 5
–0.3 0.8 V
®
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC1 Vcc Operating VCC = Max., CE = VIL Com. — 1 — 1 — 1 mA
Supply Current IOUT = 0 mA, f = 0 Ind. — 2 — 2 — 2
ICC2 Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 70 — 60 — 50 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 80 — 70 — 60
ISB1 TTL Standby Current VCC = Max., Com. — 3 — 3 — 3 mA
(TTL Inputs) VIN = VIH or VIL Ind. —5 —5 —5
CE
≥ VIH, f = 0
ISB2 CMOS Standby VCC = Max., Com. — 80 — 80 — 80 µA
Current (CMOS Inputs)
Note:
1. At f = f
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1,2)
CE
≤ VCC – 0.2V, Ind. — 100 — 100 — 100
VIN > VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
(1)
(Over Operating Range)
-15 ns -20 ns -25 ns
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 5 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc.
SR033-1A
04/27/99
3
IS62LV256L
®
ISSI
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-15 ns -20 ns -25 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 15 — 20 — 25 — ns
tAA Address Access Time — 15 — 20 — 25 ns
tOHA Output Hold Time 2 — 2 — 2 — ns
tACE
tDOE
(2)
tLZOE
(2)
tHZOE
(2)
tLZCE
(2)
tHZCE
(3)
tPU
(3)
tPD
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
CE
Access Time — 15 — 20 — 25 ns
OE
Access Time — 7 — 8 — 9 ns
OE
to Low-Z Output 0 — 0 — 0 — ns
OE
to High-Z Output — 8 — 9 — 10 ns
CE
to Low-Z Output 3 — 3 — 3 — ns
CE
to High-Z Output — 6 — 9 — 10 ns
CE
to Power-Up 0 — 0 — 0 — ns
CE
to Power-Down — 15 — 18 — 20 ns
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
AC TEST LOADS
635 Ω
3.3V
OUTPUT
30 pF
Including
jig and
scope
702 Ω
Figure 1. Figure 2.
OUTPUT
3.3V
5 pF
Including
jig and
scope
635 Ω
702 Ω
4
Integrated Silicon Solution, Inc.
SR033-1A
04/27/99
IS62LV256L
AC WAVEFORMS
®
ISSI
READ CYCLE NO. 1
ADDRESS
D
OUT
READ CYCLE NO. 2
ADDRESS
OE
(1,2)
(1,3)
t
RC
t
AA
t
OHA
DATA VALID
t
RC
t
AA
t
t
OHA
OHA
t
DOE
t
LZOE
D
CE
OUT
HIGH-Z
t
PU
t
LZCE
t
ACE
SUPPLY
CURRENT
Notes:
1.WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = V
IL.
3. Address is valid prior to or coincident with CE LOW transitions.
t
HZCE
DATA VALID
t
HZOE
t
PD
ICC
50%50%
ISB
Integrated Silicon Solution, Inc.
SR033-1A
04/27/99
5
IS62LV256L
®
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-15 ns -20 ns -25 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 15 — 20 — 25 — ns
tSCE
CE
to Write End 10 — 13 — 15 — ns
tAW Address Setup Time to Write End 10 — 15 — 20 — ns
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
(4)
tPWE
WE
Pulse Width 10 — 13 — 15 — ns
tSD Data Setup to Write End 8 — 10 — 12 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns
(2)
tHZWE
tLZWE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with OE HIGH.
WE
LOW to High-Z Output — 7 — 8 — 10 ns
(2)
WE
HIGH to Low-Z Output 0 — 0 — 0 — ns
AC WAVEFORMS
WRITE CYCLE NO. 1 (
ADDRESS
CE
WE
OUT
D
D
IN
WEWE
WE
Controlled)
WEWE
t
SA
DATA UNDEFINED
(1,2)
t
AW
t
HZWE
t
SCE
t
WC
t
PWE
HIGH-Z
t
SD
DATA-IN VALID
t
HA
t
LZWE
t
HD
6
Integrated Silicon Solution, Inc.
SR033-1A
04/27/99
IS62LV256L
®
ISSI
IH.
(1,2)
t
HZWE
t
AW
t
SCE
t
t
WC
PWE
HIGH-Z
t
SD
DATA-IN VALID
t
HA
t
t
LZWE
HD
WRITE CYCLE NO. 2 (
ADDRESS
CE
WE
D
OUT
D
IN
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ V
CECE
CE
Controlled)
CECE
t
SA
DATA UNDEFINED
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
15 IS62LV256L-15T 450-mil TSOP
IS62LV256L-15J 300-mil Plastic SOJ
20 IS62LV256L-20T 450-mil TSOP
IS62LV256L-20J 300-mil Plastic SOJ
25 IS62LV256L-25T 450-mil TSOP
IS62LV256L-25J 300-mil Plastic SOJ
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
15 IS62LV256L-15TI 450-mil TSOP
IS62LV256L-15JI 300-mil Plastic SOJ
20 IS62LV256L-20TI 450-mil TSOP
IS62LV256L-20JI 300-mil Plastic SOJ
25 IS62LV256L-25TI 450-mil TSOP
IS62LV256L-25JI 300-mil Plastic SOJ
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
Integrated Silicon Solution, Inc.
SR033-1A
04/27/99
7
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