Datasheet IS62LV2568LL-70BI, IS62LV2568LL-70B, IS62LV2568LL-85T, IS62LV2568LL-85HI, IS62LV2568LL-85H Datasheet (ISSI)

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IS62LV2568LL ISSI
256K x 8 LOW POWER and LOW Vcc
APRIL 2000
CMOS STATIC RAM
®
FEATURES
• Access times of 70 and 85 ns
CMOS low power operation: — 120 mW (typical) operating — 6 µW (typical) standby
• Low data retention voltage: 2V (min.)
• Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications
• TTL compatible inputs and outputs
• Fully static operation: — No clock or refresh required
• Single 2.5V to 3.0V power supply
• Available in 32-pin TSOP (Type I), STSOP (Type I), and 36-pin mini BGA
FUNCTIONAL BLOCK DIAGRAM
The
ISSI
IS62LV2568LL is a low voltage, 262,144 words
by 8 bits, CMOS SRAM. It is fabricated using voltage, six transistor (6T), targeted technologies such as cell phones and pagers.
When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation down with CMOS input levels. Additionally, easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory.
The IS62LV2568LL is available in 32-pin TSOP (Type I), STSOP (Type I), and 36-pin mini BGA.
to satisfy the demands of the state-of-the-art
CMOS technology.
ISS
I’s low
The device
can be reduced
is
A0-A17
VCC
GND
I/O0-I/O7
CE1
CE2
OE WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
256K x 8
MEMORY ARRAY
COLUMN I/O
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
1
IS62LV2568LL ISSI
PIN CONFIGURATION
®
36-pin mini BGA (B)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
Vcc
I/O6
I/O7
A9
A1
A2
OE
A10
CE2
WE
NC
NC
CE1
A11
A3
A4
A5
A17
A16
A12
A6
A7
A15
A13
A8
I/O0
I/O1
Vcc
GND
I/O2
I/O3
A14
PIN DESCRIPTIONS
A0-A17 Address Inputs CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
OE Output Enable Input WE Write Enable Input
I/O0-I/O7 Input/Output
NC No Connection
Vcc Power
GND Ground
32-Pin TSOP (Type I), STSOP (Type I)
A11
A9 A8
A13
WE
CE2
A15
VCC
A17 A16 A14 A12
A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
2
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
05/03/00
IS62LV2568LL ISSI
TRUTH TABLE
Mode W E CE1 CE2 OE I/O Operation Vcc Current
Not Selected X H X X High-Z ISB1, ISB2 (Power-down) X X L X High-Z ISB1, ISB2
Output Disabled H L H H High-Z ICC Read H L H L DOUT ICC Write L L H X DIN ICC
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 2.5V to 3.0V
Industrial –40°C to +85°C 2.5V to 3.0V
®
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V VCC Vcc related to GND –0.3 to +4.6 V TBIAS Temperature Under Bias –40 to +85 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 0.7 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.0V.
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
05/03/00
3
®
IS62LV2568LL ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.0 V VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V VIL Input LOW Voltage ILI Input Leakage GND VIN VCC –11µA ILO Output Leakage GND VOUT VCC –11µA
Note:
IL = –3.0V for pulse width less than 10 ns.
1. V
(1)
–0.3 0.4 V
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-70 -85
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC Vcc Dynamic VCC = Max., CE = VIL Com. 30 25 mA
Operating IOUT = 0 mA, f = fMAX Ind. 35 30 Supply Current
ISB1 TTL Standby VCC = Max., Com. 0.4 0.4 mA
Current VIN = VIH or VIL, Ind. 1.0 1.0 (TTL Inputs) CE1 ≥ VIH or CE2 ≤ VIL, f = 0
ISB2 CMOS Standby VCC = Max., f = 0 Com. 5 A
Current CE1 VCC – 0.2V, Ind. 5 5 (CMOS Inputs) CE2 ≤ 0.2V,
or VIN VCC – 0.2V, VIN 0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
05/03/00
IS62LV2568LL ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-70 -85
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 70 85 ns
tAA Address Access Time 70 85 ns
tOHA Output Hold Time 10 15 ns tACE1 CE1 Access Time 70 85 ns
tACE2 CE2 Access Time 70 85 ns tDOE OE Access Time 35 45 ns
(2)
tHZOE
(2)
tLZOE
(2)
tLZCE1
(2)
tLZCE2
(2)
tHZCE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
OE to High-Z Output 25 25 ns OE to Low-Z Output 5 5 ns CE1 to Low-Z Output 10 10 ns
CE2 to Low-Z Output 10 10 ns CE1 or CE2 to High-Z Output 0 25 0 25 ns
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0.4V to 2.2V Input Rise and Fall Times 5 ns Input and Output Timing 1.3V
and Reference Level Output Load See Figures 1 and 2
AC TEST LOADS
3070
2.8V
OUTPUT
30 pF
Including
jig and
scope
3150
2.8V
OUTPUT
5 pF
Including
jig and
scope
3070
3150
Figure 1 Figure 2
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
05/03/00
5
IS62LV2568LL ISSI
AC WAVEFORMS
READ CYCLE NO. 1
ADDRESS
(1,2)
t
OHA
t
AA
t
RC
t
OHA
®
DOUT
READ CYCLE NO. 2
ADDRESS
OE
(1,3)
tAA
tDOE
DATA VALID
tRC
tOHA
tHZOE
CE1
tACE1/tACE2
CE2
DOUT
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = V
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
tLZCE1/
tLZCE2
HIGH-Z
6
tLZOE
IL, CE2 = VIH.
Integrated Silicon Solution, Inc. 1-800-379-4774
tHZCE
DATA VALID
Rev. B
05/03/00
IS62LV2568LL ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range, Standard and Low Power)
-70 -85
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 70 85 ns tSCE1 CE1 to Write End 65 70 ns
tSCE2 CE2 to Write End 65 70 ns
tAW Address Setup Time to Write End 65 70 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Setup Time 0 0 ns
(4)
tPWE
WE Pulse Width 60 60 ns
tSD Data Setup to Write End 30 35 ns
tHD Data Hold from Write End 0 0 ns
(2)
tHZWE
(2)
tLZWE
Notes:
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1.
1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.
The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
WE LOW to High-Z Output 33 25 ns WE HIGH to Low-Z Output 5 5 ns
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW)
t
WC
ADDRESS
t
SCE1
CE1
t
SCE2
CE2
t
AW
(4)
t
t
HZWE
PWE
HIGH-Z
WE
DOUT
DIN
t
SA
DATA UNDEFINED
t
SD
DATA-IN VALID
t
HA
t
LZWE
t
HD
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
05/03/00
7
IS62LV2568LL ISSI
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
®
tSCE1
CE1
tSCE2
CE2
tAW
WE
DOUT
DIN
tSA
DATA UNDEFINED
tPWE1, 2
tHZWE
HIGH-Z
tSD tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
tHA
tLZWE
OE
t
t
SCE1
HA
CE1
t
SCE2
CE2
t
AW
t
PWE1, 2
WE
t
SA
DOUT
DATA UNDEFINED
DIN
8
t
HZWE
t
LZWE
HIGH-Z
t
SD
DATA-IN VALID
t
HD
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
05/03/00
IS62LV2568LL ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Max. Unit
VDR Vcc for Data Retention See Data Retention Waveform 2.0 3.6 V
DR Data Retention Current Vcc = 2.0V, CE1 Vcc – 0.2V Com. A
I
Ind. A
tSDR Data Retention Setup Time See Data Retention Waveform 0 ns
tRDR Recovery Time See Data Retention Waveform tRC ns
DATA RETENTION WAVEFORM (CE1 Controlled)
®
Data Retention Mode
CE1 V
3.0V
2.2V
GND
V
CC
V
DR
CE1
t
SDR
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode
V
CC
3.0
t
SDR
CE2 0.2V
2.2V
CE2
V
DR
0.4V
CC
Ð 0.2V
t
RDR
t
RDR
GND
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
05/03/00
9
IS62LV2568LL ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
70 IS62LV2568LL-70B mini BGA (6mm x 8mm)
IS62LV2568LL-70T TSOP, Type I IS62LV2568LL-70H STSOP, Type I
85 IS62LV2568LL-85B mini BGA (6mm x 8mm)
IS62LV2568LL-85T TSOP, Type I IS62LV2568LL-85H STSOP, Type I
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
70 IS62LV2568LL-70BI mini BGA (6mm x 8mm)
IS62LV2568LL-70TI TSOP, Type I IS62LV2568LL-70HI STSOP, Type I
®
85 IS62LV2568LL-85BI mini BGA (6mm x 8mm)
IS62LV2568LL-85TI TSOP, Type I IS62LV2568LL-85HI STSOP, Type I
Integrated Silicon Solution, Inc.
®
ISSI
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774 Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
10
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
05/03/00
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