• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• TTL compatible inputs and outputs
• Fully static operation:
— No clock or refresh required
• Single 2.5V to 3.0V power supply
• Available in 32-pin TSOP (Type I), STSOP (Type I),
and 36-pin mini BGA
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The
ISSI
IS62LV2568LL is a low voltage, 262,144 words
by 8 bits, CMOS SRAM. It is fabricated using
voltage, six transistor (6T),
targeted
technologies such as cell phones and pagers.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation
down with CMOS input levels. Additionally, easy memory
expansion is provided by using Chip Enable and Output
Enable inputs, CE and OE. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62LV2568LL is available in 32-pin TSOP (Type I),
STSOP (Type I), and 36-pin mini BGA.
VTERMTerminal Voltage with Respect to GND–0.5 to Vcc + 0.5V
VCCVcc related to GND–0.3 to +4.6V
TBIASTemperature Under Bias–40 to +85°C
TSTGStorage Temperature–65 to +150°C
PTPower Dissipation0.7W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE
(1,2)
SymbolParameterConditionsMax.Unit
CINInput CapacitanceVIN = 0V6pF
COUTOutput CapacitanceVOUT = 0V8pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
3
®
IS62LV2568LLISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
OE to High-Z Output—25—25ns
OE to Low-Z Output5—5—ns
CE1 to Low-Z Output10—10—ns
CE2 to Low-Z Output10—10—nsCE1 or CE2 to High-Z Output025025ns
AC TEST CONDITIONS
ParameterUnit
Input Pulse Level0.4V to 2.2V
Input Rise and Fall Times5 ns
Input and Output Timing1.3V
and Reference Level
Output LoadSee Figures 1 and 2
AC TEST LOADS
3070 Ω
2.8V
OUTPUT
30 pF
Including
jig and
scope
3150 Ω
2.8V
OUTPUT
5 pF
Including
jig and
scope
3070 Ω
3150 Ω
Figure 1Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
5
IS62LV2568LLISSI
AC WAVEFORMS
READ CYCLE NO. 1
ADDRESS
(1,2)
t
OHA
t
AA
t
RC
t
OHA
®
DOUT
READ CYCLE NO. 2
ADDRESS
OE
(1,3)
tAA
tDOE
DATA VALID
tRC
tOHA
tHZOE
CE1
tACE1/tACE2
CE2
DOUT
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = V
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
tLZCE1/
tLZCE2
HIGH-Z
6
tLZOE
IL, CE2 = VIH.
Integrated Silicon Solution, Inc. — 1-800-379-4774
tHZCE
DATA VALID
Rev. B
05/03/00
IS62LV2568LLISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range, Standard and Low Power)
-70-85
SymbolParameterMin.Max.Min.Max.Unit
tWCWrite Cycle Time70—85—ns
tSCE1CE1 to Write End65—70—ns
tSCE2CE2 to Write End65—70—ns
tAWAddress Setup Time to Write End65—70—ns
tHAAddress Hold from Write End0—0—ns
tSAAddress Setup Time0—0—ns
(4)
tPWE
WE Pulse Width60—60—ns
tSDData Setup to Write End30—35—ns
tHDData Hold from Write End0—0—ns
(2)
tHZWE
(2)
tLZWE
Notes:
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1.
1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.
The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
WE LOW to High-Z Output—33—25ns
WE HIGH to Low-Z Output5—5—ns
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW)
t
WC
ADDRESS
t
SCE1
CE1
t
SCE2
CE2
t
AW
(4)
t
t
HZWE
PWE
HIGH-Z
WE
DOUT
DIN
t
SA
DATA UNDEFINED
t
SD
DATA-IN VALID
t
HA
t
LZWE
t
HD
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
7
IS62LV2568LLISSI
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
®
tSCE1
CE1
tSCE2
CE2
tAW
WE
DOUT
DIN
tSA
DATA UNDEFINED
tPWE1, 2
tHZWE
HIGH-Z
tSDtHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
tHA
tLZWE
OE
t
t
SCE1
HA
CE1
t
SCE2
CE2
t
AW
t
PWE1, 2
WE
t
SA
DOUT
DATA UNDEFINED
DIN
8
t
HZWE
t
LZWE
HIGH-Z
t
SD
DATA-IN VALID
t
HD
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
IS62LV2568LLISSI
DATA RETENTION SWITCHING CHARACTERISTICS
SymbolParameterTest ConditionMin.Max.Unit
VDRVcc for Data RetentionSee Data Retention Waveform2.03.6V