Datasheet IS62LV12816BLL-55T, IS62LV12816BLL-55BI, IS62LV12816BLL-55B, IS62LV12816BLL-10TI, IS62LV12816BLL-10T Datasheet (ISSI)

IS62LV12816BLL ISSI

128K x 16 LOW VOLTAGE, ULTRA

®

LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access time: 55, 70, 100 ns

• CMOS low power operation
– 120 mW (typical) operating
– 6 µW (typical) CMOS standby

• TTL compatible interface levels

• Single 2.7V-3.45V V

CC power supply

• Fully static operation: no clock or refresh
required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (6mm x 8mm)

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The
static RAM organized as 131,072 words by 16 bits. It is
fabricated using
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.

When CE is HIGH (deselected) or when CE is low and
both LB and UB are HIGH, the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.

Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.

The IS62LV12816BLL is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA (6mm x 8mm).

FEBRUARY 2001

ISSI

IS62LV12816BLL is a high-speed, 2,097,152-bit

ISSI

's high-performance CMOS

A0-A16

VCC

GND

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

CE
OE

WE

UB

LB

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

128K x 16

MEMORY ARRAY

COLUMN I/O

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

03/07/01

1

IS62LV12816BLL ISSI

PIN CONFIGURATIONS

44-Pin TSOP (Type II) 48-Pin mini BGA

®

1

A4

2

A3

3

A2

4

A1

5

A0

6

CE

Vcc

WE

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

I/O0
I/O1
I/O2
I/O3

GND

I/O4
I/O5
I/O6
I/O7

A16
A15
A14
A13
A12

PIN DESCRIPTIONS

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A5
A6
A7

OE
UB
LB

I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC

1 2 3 4 5 6

A1

OE

UB A3

I/O10A5

I/O

11

I/O

12

I/O

13

NC

A8

A0

NC

NC

A14

A12

A9

A

B

C

D

E

F

G

H

LB

I/O

I/O

GND

Vcc

I/O

I/O

NC

8

9

14

15

A6

A7

A16

A15

A13

A10

A4

A2

N/C

CE I/O

I/O1I/O

I/O

3

I/O

GND

4

I/O

I/O

5

WE

I/O

A11 NC

0

2

Vcc

6

7

A0-A16 Address Inputs

I/O0-I/O15 Data Inputs/Outputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input

LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)

NC No Connection

Vcc Power

GND Ground

TRUTH TABLE

I/O PIN

Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 Vcc Current

Not Selected X H X X X High-Z High-Z ISB1, ISB2

X L X H H High-Z High-Z ISB1, ISB2

Output Disabled H L H X X High-Z High-Z ICC

X L X H H High-Z High-Z ISB

Read H L L L H DOUT High-Z ICC

H L L H L High-Z DOUT
HLLLL DOUT DOUT

Write L L X L H DIN High-Z ICC

L L X H L High-Z DIN
LLXLL DIN DIN

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

03/07/01

IS62LV12816BLL ISSI

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 2.7V - 3.45V

Industrial –40°C to +85°C 2.7V - 3.45V

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to Vcc+0.5 V

TBIAS Temperature Under Bias –40 to +85 °C

VCC Vcc Related to GND –0.3 to +3.6 V

TSTG Storage Temperature –65 to +150 °C

PT Power Dissipation 1.0 W

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.

(1)

®

1

2

3

4

5

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –1 mA 2.0 — V

VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V

VIH Input HIGH Voltage 2.2 VCC + 0.2 V

(1)

VIL

ILI Input Leakage GND ≤ VIN ≤ VCC –11µA

ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –11µA

Notes:

1. V

CAPACITANCE

Symbol Parameter Conditions Max. Unit

Input LOW Voltage –0.2 0.4 V

IL (min.) = –2.0V for pulse width less than 10 ns.

(1)

6

7

8

9

10

11

CIN Input Capacitance VIN = 0V 6 pF

COUT Input/Output Capacitance VOUT = 0V 8 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

03/07/01

12

3

IS62LV12816BLL ISSI

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0.4V to 2.2V

Input Rise and Fall Times 5 ns

Input and Output Timing 1.3V
and Reference Level

Output Load See Figures 1 and 2

®

AC TEST LOADS

3.0V

OUTPUT

Including

Figure 1

30 pF

jig and

scope

3070 Ω

3150 Ω

Figure 2

3.0V

OUTPUT

5 pF

Including

jig and

scope

3070 Ω

3150 Ω

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

03/07/01

IS62LV12816BLL ISSI

®

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = Max., Com. — 40 — 30 — 20 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 45 — 35 — 25

I

SB1 TTL Standby Current VCC = Max., Com. — 0.4 — 0.4 — 0.4 mA

(TTL Inputs) V

OR

ULB Control V

ISB2 CMOS Standby VCC = Max., Com. — 5 — 5 — 5µA

Current (CMOS Inputs) CE ≥ VCC – 0.2V, Ind. — 5 — 5 — 5

OR

ULB Control VCC = Max., CE = VIL

Note:

1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

IN = VIH or VIL Ind. — 1.0 — 1.0 — 1.0

CE ≥ VIH , f = 0

CC = Max., VIN = VIH or VIL

CE = VIL, f = 0, UB = VIH, LB = VIH

VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0

VIN ≤ 0.2V, f = 0; UB / LB = VCC – 0.2V

(1)

(Over Operating Range)

-55 -70 -100

1

2

3

4

5

6

READ CYCLE SWITCHING CHARACTERISTICS

-55 -70 -100

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 55 — 70 — 100 — ns

tAA Address Access Time — 55 — 70 — 100 ns

tOHA Output Hold Time 10 — 10 — 15 — ns
tACE CE Access Time — 55 — 70 — 100 ns
tDOE OE Access Time — 30 — 35 — 50 ns

(2)

tHZOE

tLZOE

tHZCE

tLZCE
tBA LB, UB Access Time — 55 — 70 — 100 ns
tHZB LB, UB to High-Z Output 0 25 0 25 0 35 ns
tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of

0.4 to 2.2V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

OE to High-Z Output — 20 — 25 — 30 ns

(2)

OE to Low-Z Output 5 — 5 — 5 — ns

(2)

CE to High-Z Output 0 20 0 25 0 30 ns

(2)

CE to Low-Z Output 10 — 10 — 10 — ns

(1)

(Over Operating Range)

7

8

9

10

11

12

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

03/07/01

5

IS62LV12816BLL ISSI

AC WAVEFORMS

®

READ CYCLE NO. 1

ADDRESS

D

OUT

PREVIOUS DATA VALID

(1,2)

(Address Controlled) (CE = OE = VIL, UB or LB = VIL)

t

RC

t

AA

t

OHA

t

OHA

DATA VALID

AC WAVEFORMS

t

LZB

(1,3)

(CE, OE, AND UB/LB Controlled)

t

RC

t

AA

t

DOE

t

LZOE

t

ACE

t

LZCE

t

BA

READ CYCLE NO. 2

ADDRESS

OE

CE

LB, UB

OUT

D

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE, UB, or LB = V

3. Address is valid prior to or coincident with CE LOW transition.

HIGH-Z

DATA VALID

IL.

t

HZOE

t

HZCE

t

HZB

t

OHA

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

03/07/01

IS62LV12816BLL ISSI

®

WRITE CYCLE SWITCHING CHARACTERISTICS

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

(1,2)

(Over Operating Range)

-55 -70 -100

tWC Write Cycle Time 55 — 70 — 100 — ns
tSCE CE to Write End 50 — 65 — 80 — ns

tAW Address Setup Time to Write End 50 — 65 — 80 — ns

tHA Address Hold from Write End 0 — 0 — 0 — ns

tSA Address Setup Time 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 45 — 60 — 80 — ns
tPWE WE Pulse Width 45 — 60 — 80 — ns

tSD Data Setup to Write End 25 — 30 — 40 — ns

tHD Data Hold from Write End 0 — 0 — 0 — ns

(3)

tHZWE

tLZWE

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

WE LOW to High-Z Output — 30 — 30 — 40 ns

(3)

WE HIGH to Low-Z Output 5 — 5 — 5 — ns

1

2

3

4

5

6

AC WAVEFORMS
WRITE CYCLE NO. 1

ADDRESS

CE

WE

UB, LB

D

OUT

D

IN

(1,2)

(CE Controlled, OE = HIGH or LOW)

t

WC

VALID ADDRESS

t

SA

t

DATA UNDEFINED

t

HZWE

AW

t

PWE1

t

PWE2

t

SCS

t

PBW

HIGH-Z

t

SD

DATA

IN

VALID

7

t

HA

8

9

10

t

LZWE

11

t

HD

UB_CSWR1.eps

12

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one
of the LB and UB inputs being in the LOW state.

2. WRITE = (CE) [ (LB) = (UB) ] (WE).

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

03/07/01

7

IS62LV12816BLL ISSI

WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)

t

WC

®

ADDRESS

OE

CE

WE

UB, LB

OUT

D

D

VALID ADDRESS

t

HA

LOW

t

AW

t

PWE1

t

SA

t

HZWE

DATA UNDEFINED

IN

t

PBW

HIGH-Z

t

SD

DATAIN VALID

t

t

HD

LZWE

UB_CSWR2.eps

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

t WC

ADDRESS

OE

CE

WE

UB, LB

D

OUT

DIN

LOW

LOW

t SA

DATA UNDEFINED

VALID ADDRESS

t AW

t PWE2

t PBW

t HZWE

HIGH-Z

t SD

DATAIN VALID

t HA

t LZWE

t HD

UB_CSWR3.eps

8

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

03/07/01

IS62LV12816BLL ISSI

WRITE CYCLE NO. 4 (UB/LB Controlled)

t

t

WC

WC

®

ADDRESS

OE

CE

WE

UB, LB

OUT

D

D

IN

LOW

t

HZWE

DATA UNDEFINED

ADDRESS 1 ADDRESS 2

t

SA

t

HA

t

SA

t

t

SD

PBW

WORD 1

HIGH-Z

DATA

VALID

t

HD

IN

t

SD

t

PBW

WORD 2

DATA

VALID

1

2

t

HA

3

4

t

LZWE

t

HD

IN

UB_CSWR4.eps

5

6

DATA RETENTION SWITCHING CHARACTERISTICS

Symbol Parameter Test Condition Min. Max. Unit

VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.45 V

IDR Data Retention Current Vcc = 2.0V, CE • Vcc – 0.2V — 5µA

tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns

tRDR Recovery Time See Data Retention Waveform tRC — ns

DATA RETENTION WAVEFORM (CE Controlled)

Data Retention Mode

CE ≥ VCC Ð 0.2V

2.3V

2.0V

GND

VCC

VDR

CE

t

SDR tRDR

7

8

9

10

11

12

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

03/07/01

9

IS62LV12816BLL ISSI

ORDERING INFORMATION

®

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

55 IS62LV12816BLL-55T TSOP (Type II)

IS62LV12816BLL-55B Mini BGA (6mm x 8mm)

70 IS62LV12816BLL-70T TSOP (Type II)

IS62LV12816BLL-70B Mini BGA (6mm x 8mm)

100 IS62LV12816BLL-10T TSOP (Type II)

IS62LV12816BLL-10B Mini BGA (6mm x 8mm)

Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

55 IS62LV12816BLL-55TI TSOP (Type II)

IS62LV12816BLL-55BI Mini BGA (6mm x 8mm)

70 IS62LV12816BLL-70TI TSOP (Type II)

IS62LV12816BLL-70BI Mini BGA (6mm x 8mm)

100 IS62LV12816BLL-10TI TSOP (Type II)

IS62LV12816BLL-10BI Mini BGA (6mm x 8mm)

10

®

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: [phone]
Fax: [phone]

E-mail: [e-mail]

www.issi.com

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

03/07/01