Datasheet IS62LV12816ALL-70TI, IS62LV12816ALL-70T, IS62LV12816ALL-70BI, IS62LV12816ALL-70B, IS62LV12816ALL-55BI Datasheet (ISSI)
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Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
04/17/01
IS62LV12816ALL
ISSI
®
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
128K x 16 CMOS STATIC RAM
FEATURES
• High-speed access time: 55, 70, 100 ns
• CMOS low power operation
– 120 mW (typical) operating
– 6 µW (typical) CMOS standby
• TTL compatible interface levels
•
Single
2.5V
(min.)
to 3.45V
(max.)
power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (6mm x 8mm)
DESCRIPTION
The
ISSI
IS62LV12816ALL is a high-speed, 2,097,152-bit
static RAM organized as 131,072 words by 16 bits. It is
fabricated using
ISSI
's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62LV12816ALL is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA. (6mm x 8mm)
FUNCTIONAL BLOCK DIAGRAM
MARCH 2001
A0-A16
CE
OE
WE
128K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
IS62LV12816ALL
ISSI
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
PIN CONFIGURATIONS
44-Pin TSOP (Type II)
TRUTH TABLE
I/O PIN
Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 Vcc Current
Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC
X L X H H High-Z High-Z
Read H L L L H DOUT High-Z ICC
H L L H L High-Z DOUT
HLLLL DOUT DOUT
Write L L X L H DIN High-Z ICC
L L X H L High-Z DIN
LLXLL DIN DIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
48-Pin mini BGA
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
N/C
I/O
8
UB A3
A4
CE I/O
0
I/O
9
I/O10A5
A6
I/O1I/O
2
GND
I/O
11
NC
A7
I/O
3
Vcc
Vcc
I/O
12
NC
A16
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
NC
A8
A9
A10
A11 NC
PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
Vcc Power
GND Ground
IS62LV12816ALL
ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. A
04/17/01
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DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –1 mA 2.0 — V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.2 V
VIL
(1)
Input LOW Voltage –0.2 0.4 V
ILI Input Leakage GND ≤ VIN ≤ VCC –11µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –11µA
Notes:
1. V
IL (min.) = –2.0V for pulse width less than 10 ns.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc+0.5 V
TBIAS Temperature Under Bias –40 to +85 °C
VCC Vcc Related to GND –0.3 to +3.6 V
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.0 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Ambient Temperature VCC MIN.VCC MAX.
Commercial 0°C to +70°C 2.5V 3.45V
Industrial –40°C to +85°C 2.5V 3.45V
CAPACITANCE
(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
IS62LV12816ALL
ISSI
®
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.3V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
3070 Ω
100 pF
Including
jig and
scope
3150 Ω
OUTPUT
3.0V
Figure 1
3070 Ω
5 pF
Including
jig and
scope
3150 Ω
OUTPUT
3.0V
Figure 2
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-55 -70 -100
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., Com. — 40 — 30 — 20 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 60 — 50 — 40
ISB1 TTL Standby Current VCC = Max., Com. — 0.4 — 0.4 — 0.4 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 1.0 — 1.0 — 1.0
CE ≥ VIH , f = 0
ISB2 CMOS Standby VCC = Max., Com. — 5 — 5 — 5µA
Current (CMOS Inputs) CE ≥ VCC – 0.2V, Ind. — 5 — 5 — 5
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = f
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS62LV12816ALL
ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. A
04/17/01
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READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-55 -70 -100
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 55 — 70 — 100 — ns
tAA Address Access Time — 55 — 70 — 100 ns
tOHA Output Hold Time 10 — 10 — 15 — ns
tACE CE Access Time — 55 — 70 — 100 ns
tDOE OE Access Time — 30 — 35 — 50 ns
tHZOE
(2)
OE to High-Z Output — 20 — 25 — 30 ns
tLZOE
(2)
OE to Low-Z Output 5 — 5 — 5 — ns
tHZCE
(2)
CE to High-Z Output 0 20 0 25 0 30 ns
tLZCE
(2)
CE to Low-Z Output 10 — 10 — 10 — ns
tBA LB, UB Access Time — 20 — 35 — 50 ns
tHZB LB, UB to High-Z Output 0 25 0 25 0 35 ns
tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of
0.4 to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CE = OE = VIL, UB or LB = VIL)
IS62LV12816ALL
ISSI
®
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-55 -70 -100
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 55 — 70 — 100 — ns
tSCE CE to Write End 50 — 65 — 80 — ns
tAW Address Setup Time to Write End 50 — 65 — 80 — ns
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 45 — 60 — 80 — ns
tPWE WE Pulse Width 45 — 60 — 80 — ns
tSD Data Setup to Write End 25 — 30 — 40 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns
tHZWE
(3)
WE LOW to High-Z Output — 30 — 30 — 40 ns
tLZWE
(3)
WE HIGH to Low-Z Output 5 — 5 — 5 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to
2.2V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
t
HZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
t
BA
t
LZB
AC WAVEFORMS
READ CYCLE NO. 2
(1,3)
(CS, OE, AND UB/LB Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = V
IL.
3. Address is valid prior to or coincident with CE LOW transition.
IS62LV12816ALL
ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
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Rev. A
04/17/01
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Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS) [ (LB) = (UB) ] (WE).
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(CS Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCS
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CS
UB, LB
WE
D
OUT
D
IN
DATAIN VALID
t
LZWE
t
SD
UB_CSWR1.eps
IS62LV12816ALL
ISSI
®
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CS
UB, LB
WE
D
OUT
D
IN
OE
DATAIN VALID
t
LZWE
t
SD
UB_CSWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CS
UB, LB
WE
D
OUT
D
IN
OE
DATAIN VALID
t
LZWE
t
SD
UB_CSWR3.eps
IS62LV12816ALL
ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. A
04/17/01
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DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Max. Unit
VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.45 V
IDR Data Retention Current Vcc = 2.0V, CE ≥ Vcc – 0.2V — 5µA
tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform tRC — ns
DATA RETENTION WAVEFORM (CE Controlled)
V
CC
CE ≥ V
CC
— 0.2V
t
SDR
t
RDR
V
DR
CE
GND
2.3V
2.0V
Data Retention Mode
IS62LV12816ALL
ISSI
®
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
55 IS62LV12816ALL-55T TSOP (Type II)
IS62LV12816ALL-55B Mini BGA (6mm x 8mm)
70 IS62LV12816ALL-70T TSOP (Type II)
IS62LV12816ALL-70B Mini BGA (6mm x 8mm)
100 IS62LV12816ALL-10T TSOP (Type II)
IS62LV12816ALL-10B Mini BGA (6mm x 8mm)
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
55 IS62LV12816ALL-55TI TSOP (Type II)
IS62LV12816ALL-55BI Mini BGA
70 IS62LV12816ALL-70TI TSOP (Type II)
IS62LV12816ALL-70BI Mini BGA
100 IS62LV12816ALL-10TI TSOP (Type II)
IS62LV12816ALL-10BI Mini BGA (6mm x 8mm)
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