Datasheet IS62LV1024LL-70QI, IS62LV1024LL-70Q, IS62LV1024LL-70H, IS62LV1024LL-55T, IS62LV1024LL-55QI Datasheet (ISSI)
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IS62LV1024LL ISSI
A0-A16
CE1
OE
WE
512 X 2048
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
CE2
128K x 8 LOW POWER and LOW Vcc
®
CMOS STATIC RAM
FEATURES
• Access times of 45, 55, and 70 ns
• Low active power: 60 mW (typical)
• Low standby power: 15 µW (typical) CMOS
standby
• Low data retention voltage: 2V (min.)
• Ultra Low Power
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• TTL compatible inputs and outputs
• Single 2.5V to 3.3V
• Industrial temperature available
• Available in 32-pin TSOP (Type I), 32-pin
STSOP, and 450-mil SOP
JANUARY 2001
DESCRIPTION
The ISSI IS62LV1024LL is a low power and low
Vcc,131,072-word by 8-bit CMOS static RAM. It is
fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields higher
performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62LV1024LL is available in 32-pin TSOP (Type I),
STSOP (8 x 13.4mm), and 450-mil plastic SOP (525-mil
pin to pin) packages.
FUNCTIONAL BLOCK DIAGRAM
This document contISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no
responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
01/31/01
1
IS62LV1024LL ISSI
®
PIN CONFIGURATION
32-Pin SOP (Q)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
32-Pin TSOP (Type I) (T) and STSOP (Type 1) (H)
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
NC No Connection
Vcc Power
GND Ground
OPERATING RANGE
Range Ambient Temperature Speed VCC
Commercial 0°C to +70°C -45 ns 2.85V to 3.15V
-55 ns 2.5V to 3.3V
-70 ns 2.5V to 3.3V
Industrial –40°C to +85°C 2.5V to 3.3V
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
01/31/01
IS62LV1024LL ISSI
TRUTH TABLE
Mode WE CE1 CE2 OE I/O Operation Vcc Current
®
Not Selected X H X X High-Z I
SB1, ISB2
(Power-down) X X L X High-Z ISB1, ISB2
Output Disabled H L H H High-Z ICC
Read H L H L DOUT ICC
Write L L H X DIN ICC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
VCC Vcc related to GND –0.3 to +3.6 V
TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 0.7 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
01/31/01
3
®
IS62LV1024LL ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.2 — V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.2 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC –11µA
ILO Output Leakage GND ≤ VOUT ≤ VCC –11µA
Notes:
IL = –3.0V for pulse width less than 10 ns.
1. V
(1)
–0.2 0.4 V
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-45 -55 -70
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 35 — 30 — 25 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 40 — 35 — 30
ISB1 TTL Standby Current VCC = Max., Com. — 0.4 — 0.4 — 0.4 mA
(TTL Inputs) VIN = VIH or VIL, CE1 ≥ VIH Ind. — 1 — 1 — 1
or CE2 ≤ VIL, f = 0
ISB2 CMOS Standby VCC = Max., f = 0 Com. — 8 — 8 — 8µA
Current (CMOS Inputs) CE1 ≥ VCC – 0.2V, Ind. — 10 — 10 — 10
CE2 ≤ 0.2V,
or VIN ≥ VCC – 0.2V, VIN ≤ 0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
01/31/01
IS62LV1024LL ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-45 -55 -70
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 45 — 55 — 70 — ns
tAA Address Access Time — 45 — 55 — 70 ns
tOHA Output Hold Time 10 — 10 — 10 — ns
tACE1 CE1 Access Time — 45 — 55 — 70 ns
tACE2 CE2 Access Time — 45 — 55 — 70 ns
tDOE OE Access Time — 20 — 25 — 35 ns
(2)
tLZOE
tHZOE
tLZCE1
tLZCE2
tHZCE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
OE to Low-Z Output 0 — 5 — 5 — ns
(2)
OE to High-Z Output 0 15 0 20 0 25 ns
(2)
CE1 to Low-Z Output 5 — 7 — 10 — ns
(2)
CE2 to Low-Z Output 5 — 7 — 10 — ns
(2)
CE1 or CE2 to High-Z Output 0 15 0 20 0 25 ns
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.3V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
1213 Ω
3.0V
OUTPUT
30 pF
Including
jig and
scope
1378 Ω
OUTPUT
3.0V
5 pF
Including
jig and
scope
1213 Ω
1378 Ω
Figure 1. Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
01/31/01
5
IS62LV1024LL ISSI
AC WAVEFORMS
READ CYCLE NO. 1
ADDRESS
(1,2)
t
OHA
t
AA
t
RC
t
OHA
®
DOUT
READ CYCLE NO. 2
ADDRESS
OE
(1,3)
DATA VALID
t
RC
t
AA
t
DOE
t
HZOE
t
OHA
t
CE1
CE2
DOUT
t
ACE1/tACE2
t
LZCE1/
t
LZCE2
HIGH-Z
LZOE
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = V
IL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
t
HZCE
DATA VALID
Rev. H
01/31/01
IS62LV1024LL ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range, Standard and Low Power)
-45 -55 -70
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 45 — 55 — 70 — ns
tSCE1 CE1 to Write End 35 — 50 — 60 — ns
tSCE2 CE2 to Write End 35 — 50 — 60 — ns
tAW Address Setup Time to Write End 35 — 50 — 60 — ns
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
tPWE1,2 WE Pulse Width 35 — 40 — 55 — ns
tSD Data Setup to Write End 25 — 25 — 30 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns
(2)
tHZWE
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
WE LOW to High-Z Output — 15 — 20 0 25 ns
(2)
WE HIGH to Low-Z Output 5 — 5 — 5 — ns
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE1, CE2 Controlled, OE = HIGH or LOW)
t
WC
ADDRESS
t
HA
t
LZWE
t
CE1
CE2
WE
DOUT
DIN
t
SA
DATA UNDEFINED
t
AW
t
HZWE
t
SCE1
t
SCE2
t
PWE
(4)
HIGH-Z
t
SD
DATA-IN VALID
(1,2)
HD
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
01/31/01
7
IS62LV1024LL ISSI
®
WRITE CYCLE NO. 2 (WE, Controlled: OE is HIGH during Write Cycle)
t
WC
ADDRESS
OE
t
HA
t
t
LZWE
HD
CE1
CE2
WE
DOUT
DIN
t
SA
DATA UNDEFINED
t
AW
t
HZWE
t
SCE1
t
SCE2
t
PWE1, 2
HIGH-Z
t
SD
DATA-IN VALID
(1,2)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW during Write Cycle)
t
WC
(1,2)
ADDRESS
OE
t
t
SCE1
HA
CE1
t
SCE2
CE2
t
AW
t
t
HZWE
PWE1, 2
HIGH-Z
t
SD
DATA-IN VALID
t
LZWE
t
HD
WE
DOUT
DIN
t
SA
DATA UNDEFINED
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = V
IH.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
01/31/01
®
IS62LV1024LL ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Max. Unit
VDR Vcc for Data Retention See Data Retention Waveform 2.0 3.3 V
IDR Data Retention Current Vcc = 2.0V, CE1 ≥ Vcc – 0.2V Com. — 8µA
Ind. — 10 µA
tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform tRC — ns
DATA RETENTION WAVEFORM (CE1 Controlled)
Data Retention Mode
CE1 ≥ V
3.0V
2.2V
GND
V
CC
V
DR
CE1
t
SDR
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode
V
CC
3.0
t
SDR
CE2 ≤ 0.2V
2.2V
CE2
V
DR
0.4V
CC
– 0.2V
t
RDR
t
RDR
GND
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
01/31/01
9
IS62LV1024LL ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.Package
45 IS62LV1024LL-45Q 450-mil Plastic SOP
IS62LV1024LL-45T TSOP, Type I
IS62LV1024LL-45H STSOP, Type I
55 IS62LV1024LL-55Q 450-mil Plastic SOP
IS62LV1024LL-55T TSOP, Type I
IS62LV1024LL-55H STSOP, Type I
70 IS62LV1024LL-70Q 450-mil Plastic SOP
IS62LV1024LL-70T TSOP, Type I
IS62LV1024LL-70H STSOP, Type I
®
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
45 IS62LV1024LL-45QI 450-mil Plastic SOP
IS62LV1024LL-45TI TSOP, Type I
IS62LV1024LL-45HI STSOP, Type I
55 IS62LV1024LL-55QI 450-mil Plastic SOP
IS62LV1024LL-55TI TSOP, Type I
IS62LV1024LL-55HI STSOP, Type I
70 IS62LV1024LL-70QI 450-mil Plastic SOP
IS62LV1024LL-70TI TSOP, Type I
IS62LV1024LL-70HI STSOP, Type I
Integrated Silicon Solution, Inc.
®
ISSI
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
01/31/01
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