Datasheet IS62C256-70TI, IS62C256-45UI, IS62C256-45U, IS62C256-45TI, IS62C256-45T Datasheet (ISSI)
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®
IS62C256
32K x 8 LOW POWER CMOS STATIC RAM
FEATURES
• Access time: 45, 70 ns
• Low active power: 200 mW (typical)
• Low standby power
— 250 µW (typical) CMOS standby
— 28 mW (typical) TTL standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V power supply
DESCRIPTION
The ISSI IS62C256 is a low power, 32,768 word by 8-bit
CMOS static RAM. It is fabricated using ISSI's highperformance, low power CMOS technology.
When CS is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 µW (typical) at CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Select (CS) input and an active LOW Output Enable (OE)
input. The active LOW Write Enable (WE) controls both writing
and reading of the memory.
The IS62C256 is pin compatible with other 32K x 8 SRAMs in
plastic SOP or TSOP (Type I) package.
ISSI
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VCC
GND
I/O0-I/O7
CS
OE
WE
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
32K X 8
MEMORY ARRAY
COLUMN I/O
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
1
Page 2
IS62C256
®
ISSI
PIN CONFIGURATION
28-Pin SOP
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN DESCRIPTIONS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
28-Pin TSOP
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
TRUTH TABLE
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
9
A1
8
A2
A0-A14 Address Inputs
CS
OE
Chip Select Input
Output Enable Input
Mode
WEWE
WE
WEWE
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
CSCS
CS
CSCS
OEOE
OE
OEOE
Output Disabled H L H High-Z ICC1, ICC2
WE
I/O0-I/O7 Input/Output
Write Enable Input
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2
Vcc Power
GND Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 0.5 W
IOUT DC Output Current (LOW) 20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
I/O Operation Vcc Current
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
Page 3
IS62C256
ISSI
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –2 2 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, Com. –2 2 µA
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
(1)
Ind. –10 10
Outputs Disabled Ind. –10 10
–0.3 0.8 V
®
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC1 Vcc Operating VCC = Max., CS = VIL Com. — 60 — 60 mA
Supply Current IOUT = 0 mA, f = 0 Ind. — 70 — 70
ICC2 Vcc Dynamic Operating VCC = Max., CS = VIL Com. — 70 — 65 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 80 — 75
ISB1 TTL Standby Current VCC = Max., Com. — 5 — 5 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 10 — 10
CS
ISB2 CMOS Standby VCC = Max., Com. — 0.5 — 0.5 mA
Current (CMOS Inputs)
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
COUT Output Capacitance VOUT = 0V 10 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
(1,2)
A = 25°C, f = 1 MHz, Vcc = 5.0V.
CS
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
(1)
(Over Operating Range)
-45 ns -70 ns
≥ VIH, f = 0
≥ VCC – 0.2V, Ind. — 1.0 — 1.0
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
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IS62C256
DATA RETENTION CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Units
VDR VCC
IDR1
IDR2
for retention of data 2.0
Data retention current VDR = 3.0V, TA = 0°C to +25°C
Data retention current VDR = 3.0V, TA = 0°C to +70°C
—
—
—
200 µA
200 µA
®
ISSI
V
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-45 ns -70 ns
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 45 — 70 — ns
tAA Address Access Time — 45 — 70 ns
tOHA Output Hold Time 2 — 2 — ns
tACS
tDOE
tLZOE
tHZOE
tLZCS
tHZCS
tPU
tPD
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
CS
Access Time — 45 — 70 ns
OE
Access Time — 25 — 35 ns
(2)
OE
to Low-Z Output 0 — 0 — ns
(2)
OE
to High-Z Output 0 20 0 25 ns
(2)
CS
to Low-Z Output 3 — 3 — ns
(2)
CS
to High-Z Output 0 20 0 25 ns
(3)
CS
to Power-Up 0 — 0 — ns
(3)
CS
to Power-Down — 30 — 50 ns
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
AC TEST LOADS
480 Ω
5V
OUTPUT
100 pF
Including
jig and
scope
255 Ω
Figure 1. Figure 2.
4
OUTPUT
5V
480 Ω
5 pF
Including
jig and
scope
255 Ω
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
Page 5
IS62C256
AC WAVEFORMS
®
ISSI
READ CYCLE NO. 1
ADDRESS
D
OUT
READ CYCLE NO. 2
ADDRESS
OE
(1,2)
PREVIOUS DATA VALID
(1,3)
t
AA
t
OHA
t
RC
t
AA
DATA VALID
t
RC
t
OHA
t
OHA
READ1.eps
t
DOE
t
LZOE
t
ACS
D
CS
OUT
t
LZCS
HIGH-Z
Notes:
1.WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS = V
IL.
3. Address is valid prior to or coincident with CS LOW transitions.
DATA VALID
t
HZCS
t
HZOE
CS_RD2.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
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IS62C256
®
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-45 ns -70ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 45 — 70 — ns
tSCS
CS
to Write End 35 — 60 — ns
tAW Address Setup Time to Write End 25 — 60 — ns
tHA Address Hold from Write End 0 — 0 — ns
tSA Address Setup Time 0 — 0 — ns
(4)
tPWE
WE
Pulse Width 25 — 55 — ns
tSD Data Setup to Write End 20 — 30 — ns
tHD Data Hold from Write End 0 — 0 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1
ADDRESS
CS
WE
D
OUT
D
IN
(CS Controlled, OE is HIGH or LOW)
t
WC
VALID ADDRESS
t
SA
t
DATA UNDEFINED
t
AW
HZWE
t
PWE1
t
PWE2
t
SCS
(1 )
HIGH-Z
t
SD
DATAIN VALID
t
HA
t
LZWE
t
HD
CS_WR1.eps
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
Page 7
IS62C256
AC WAVEFORMS
®
ISSI
WRITE CYCLE NO. 2
ADDRESS
OE
LOW
CS
WE
t
OUT
D
D
IN
(OE is HIGH During Write Cycle)
t
WC
VALID ADDRESS
t
AW
t
PWE1
SA
DATA UNDEFINED
t
HZWE
(1,2)
HIGH-Z
t
SD
DATAIN VALID
t
HA
t
LZWE
t
HD
CS_WR2.eps
WRITE CYCLE NO. 3
ADDRESS
LOW
OE
CS
LOW
(OE is LOW During Write Cycle)
VALID ADDRESS
t
AW
t
WC
t
PWE2
(1)
t
HA
WE
t
D
OUT
D
SA
DATA UNDEFINED
IN
t
HZWE
HIGH-Z
t
SD
DATAIN VALID
t
LZWE
t
HD
CS_WR3.eps
Notes:
1. The internal write time is defined by the overlap of Cs LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = V
IH.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
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Page 8
IS62C256
®
ISSI
ORDERING INFORMATION
Commerical Range: 0°C to +70°C
Speed
(ns) Order Part No. Package
45 IS62C256-45T TSOP
IS62C256-45U Plastic SOP
70 IS62C256-70T TSOP
IS62C256-70U Plastic SOP
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed
(ns) Order Part No. Package
45 IS62C256-45TI TSOP
IS62C256-45UI Plastic SOP
70 IS62C256-70TI TSOP
IS62C256-70UI Plastic SOP
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
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