Datasheet IS62C1024-70W, IS62C1024-70TI, IS62C1024-70T, IS62C1024-55WI, IS62C1024-55TI Datasheet (ICSI)

IS62C1024

A0-A16

CE1

OE
WE

512 x 2048

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

CE2

IS62C1024

128K x 8 HIGH-SPEED CMOS STATIC RAM

FEATURES

• High-speed access time: 35, 45, 55, 70 ns

• Low active power: 450 mW (typical)

• Low standby power: 500 µW (typical) CMOS

standby

• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications

• Fully static operation: no clock or refresh
required

• TTL compatible inputs and outputs

• Single 5V (±10%) power supply

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The ICSI IS62C1024 is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using ICSI's high­performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields higher
performance and low power consumption devices.

When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.

Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.

The IS62C1024 is available in 32-pin 600mil DIP, 450mil SOP
and 8*20mm TSOP-1 packages.

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

Integrated Circuit Solution Inc. 1

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IS62C1024

PIN CONFIGURATION

32-Pin SOP and DIP

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3

NC
A16
A14
A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

PIN DESCRIPTIONS

A0-A16 Address Inputs

PIN CONFIGURATION

32-Pin 8x20mm TSOP-1

A11

A9
A8

A13

WE

CE2

A15

VCC

NC
A16
A14
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3

CE1 Chip Enable 1 Input

CE2 Chip Enable 2 Input

OE Output Enable Input
WE Write Enable Input

I/O0-I/O7 Input/Output

Vcc Power

GND Ground

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 5V ± 10%

Industrial –40°C to +85°C 5V ± 10%

TRUTH TABLE

Mode

WEWE

WE

WEWE

Not Selected X H X X High-Z ISB1, ISB2
(Power-down) X X L X High-Z ISB1, ISB2

Output Disabled H L H H High-Z ICC
Read H L H L DOUT ICC
Write L L H X DIN ICC

CE1CE1

CE1 CE2

CE1CE1

OEOE

OE I/O Operation Vcc Current

OEOE

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IS62C1024

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

CAPACITANCE

(1,2)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF

COUT Output Capacitance VOUT = 0V 8 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

A = 25°C, f = 1 MHz, Vcc = 5.0V.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –5 5 µA

ILO Output Leakage GND ≤ VOUT ≤ VCC Com. –5 5 µA

Notes:

IL = –3.0V for pulse width less than 10 ns.

1. V

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 150 — 135 — 120 — 90 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 160 — 145 — 130 — 100

ISB1 TTL Standby Current VCC = Max., Com. — 40 — 40 — 40 — 40 mA

(TTL Inputs) VIN = VIH or VIL, CE1 ≥ VIH, Ind. — 60 — 60 — 60 — 60

ISB2 CMOS Standby VCC = Max., Com. — 30 — 30 — 30 — 30 mA

Current (CMOS Inputs) CE1 ≥ VCC – 0.2V, Ind. — 40 — 40 — 40 — 40

(1)

(1)

(Over Operating Range)

or CE2 ≤ VIL, f = 0

CE2 ≤ 0.2V, VIN > VCC – 0.2V,
or VIN ≤ 0.2V, f = 0

–0.3 0.8 V

Ind. –10 10

Ind. –10 10

-35 ns -45 ns -55 ns -70 ns

Notes:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

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IS62C1024

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-35 -45 -55 -70

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 35 — 45 — 55 — 70 — ns

tAA Address Access Time — 35 — 45 — 55 — 70 ns

tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
tACE1 CE1 Access Time — 35 — 45 — 55 — 70 ns

tACE2 CE2 Access Time — 35 — 45 — 55 — 70 ns
tDOE OE Access Time — 10 — 20 — 25 — 35 ns

(2)

tLZOE

tHZOE

tLZCE1

tLZCE2

tHZCE

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

OE to Low-Z Output 0 — 0 — 0 — 0 — ns

(2)

OE to High-Z Output 0 10 0 15 0 20 0 25 ns

(2)

CE1 to Low-Z Output 3 — 5 — 7 — 10 — ns

(2)

CE2 to Low-Z Output 3 — 5 — 7 — 10 — ns

(2)

CE1 or CE2 to High-Z Output 0 10 0 15 0 20 0 25 ns

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.5V

and Reference Level
Output Load See Figures 1a and 1b

AC TEST LOADS

480 Ω

5V

OUTPUT

100 pF

Including

jig and

scope

Figure 1a. Figure 1b.

255 Ω

5V

OUTPUT

5 pF

Including

jig and

scope

480 Ω

255 Ω

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IS62C1024

AC WAVEFORMS

READ CYCLE NO. 1

ADDRESS

D

OUT

READ CYCLE NO. 2

ADDRESS

(1,2)

PREVIOUS DATA VALID

(1,3)

t

AA

t

OHA

t

RC

t

RC

t

AA

DATA VALID

t

OHA

t

OHA

OE

t

DOE

t

CE

t

LZCE

OUT

D

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE1 = V

3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.

HIGH-Z

LZOE

t

ACE

IL, CE2 = VIH.

DATA VALID

t

HZCE

t

HZOE

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IS62C1024

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range, Standard and Low

Power)

-35 -45 -55 -70

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 35 — 45 — 55 — 70 — ns
tSCE1 CE1 to Write End 25 — 35 — 50 — 60 — ns

tSCE2 CE2 to Write End 25 — 35 — 50 — 60 — ns

tAW Address Setup Time to Write End 25 — 35 — 45 — 60 — ns

tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns

tSA Address Setup Time 0 — 0 — 0 — 0 — ns

(4)

tPWE

WE Pulse Width 25 — 35 — 40 — 50 — ns

tSD Data Setup to Write End 20 — 25 — 25 — 30 — ns

tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns

(2)

tHZWE

tLZWE

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.

4. Tested with OE HIGH.

WE LOW to High-Z Output — 10 — 15 — 20 — 25 ns

(2)

WE HIGH to Low-Z Output 3 — 5 — 5 — 5 — ns

AC WAVEFORMS
WRITE CYCLE NO. 1 (

ADDRESS

CE

WE

OUT

D

D

IN

WEWE

WE Controlled)

WEWE

t

SA

DATA UNDEFINED

(1,2)

VALID ADDRESS

t

AW

t

HZWE

t

PWE1

t

PWE2

t

t

WC

SCE

HIGH-Z

t

SD

DATAIN VALID

t

HA

t

LZWE

t

HD

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IS62C1024

t

(1,2)

WC

t

HA

WRITE CYCLE NO. 2 (

ADDRESS

CE1CE1

CE1, CE2 Controlled)

CE1CE1

VALID ADDRESS

OE

LOW

CE

t

AW

t

PWE1

WE

t

D

OUT

D

SA

DATA UNDEFINED

IN

t

HZWE

HIGH-Z

t

SD

DATAIN VALID

t

LZWE

t

HD

Notes:

1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE = V

IH.

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IS62C1024

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

35 IS62C1024-35W 600mil DIP
35 IS62C1024-35Q 450mil SOP
35 IS62C1024-35T 8*20mm TSOP-1

45 IS62C1024-45W 600mil DIP
45 IS62C1024-45Q 450mil SOP
45 IS62C1024-45T 8*20mm TSOP-1

55 IS62C1024-55W 600mil DIP
55 IS62C1024-55Q 450mil SOP
55 IS62C1024-55T 8*20mm TSOP-1

70 IS62C1024-70W 6600mil DIP
70 IS62C1024-70Q 450mil SOP
70 IS62C1024-70T 8*20mm TSOP-1

ORDERING INFORMATION
Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

35 IS62C1024-35WI 600mil DIP
35 IS62C1024-35QI 450mil SOP
35 IS62C1024-35TI 8*20mm TSOP-1

45 IS62C1024-45WI 600mil DIP
45 IS62C1024-45QI 450mil SOP
45 IS62C1024-45TI 8*20mm TSOP-1

55 IS62C1024-55WI 600mil DIP
55 IS62C1024-55QI 450mil SOP
55 IS62C1024-55TI 8*20mm TSOP-1

70 IS62C1024-70WI 600mil DIP
70 IS62C1024-70QI 450mil SOP
70 IS62C1024-70TI 8*20mm TSOP-1

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