Datasheet IS62C1024-70T, IS62C1024-70QI, IS62C1024-70Q, IS62C1024-55TI, IS62C1024-55T Datasheet (ISSI)
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IS62C1024 ISSI
128K x 8 HIGH-SPEED CMOS STATIC RAM JANUARY 2000
®
FEATURES
• High-speed access time: 35, 45, 55, 70 ns
• Low active power: 450 mW (typical)
• Low standby power: 500 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS62C1024 is a low power,131,072-word by
8-bit CMOS static RAM. It is fabricated using ISSI's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques,
yields higher performance and low power consumption
devices.
When CE1 is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write
Enable (WE) controls both writing and reading of the
memory.
The IS62C1024 is available in 32-pin 525-mil plastic SOP
and TSOP (type 1) packages.
A0-A16
VCC
GND
I/O0-I/O7
CE1
CE2
OE
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
512 X 2048
MEMORY ARRAY
COLUMN I/O
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
1
IS62C1024 ISSI
PIN CONFIGURATION
32-Pin SOP 32-Pin TSOP (Type 1)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
62C1024
7
8
9
10
11
12
13
14
15
16
ISSI
®
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
Vcc Power
GND Ground
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
IS62C1024 ISSI
TRUTH TABLE
Mode WE CE1 CE2 OE I/O Operation Vcc Current
®
Not Selected X H X X High-Z I
SB1, ISB2
(Power-down) X X L X High-Z ISB1, ISB2
Output Disabled H L H H High-Z ICC
Read H L H L DOUT ICC
Write L L H X DIN ICC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –55µA
ILO Output Leakage GND ≤ VOUT ≤ VCC Com. –55µA
(1)
–0.3 0.8 V
Ind. –10 10
Ind. –10 10
Notes:
IL = –3.0V for pulse width less than 10 ns.
1. V
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
3
IS62C1024 ISSI
®
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-35 -45 -55 -70
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
CC Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 150 — 135 — 120 — 90 mA
I
Supply Current IOUT = 0 mA, f = fMAX Ind. — 160 — 145 — 130 — 100
ISB1 TTL Standby Current VCC = Max., Com. — 40 — 40 — 40 — 40 mA
(TTL Inputs) VIN = VIH or VIL, CE1 ≥ VIH, Ind. — 60 — 60 — 60 — 60
or CE2 ≤ VIL, f = 0
SB2 CMOS Standby VCC = Max., Com. — 30 — 30 — 30 — 30 mA
I
Current (CMOS Inputs) CE1 ≤ V
CC – 0.2V, Ind. — 40 — 40 — 40 — 40
CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V, f = 0
Notes:
1. At f = f
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1a and 1b
AC TEST LOADS
480 Ω
5V
OUTPUT
100 pF
Including
jig and
scope
255 Ω
OUTPUT
5V
5 pF
Including
jig and
scope
480 Ω
255 Ω
Figure 1a. Figure 1b.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
IS62C1024 ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-35 -45 -55 -70
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 35 — 45 — 55 — 70 — ns
tAA Address Access Time — 35 — 45 — 55 — 70 ns
tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
tACE1 CE1 Access Time — 35 — 45 — 55 — 70 ns
tACE2 CE2 Access Time — 35 — 45 — 55 — 70 ns
tDOE OE Access Time — 10 — 20 — 25 — 35 ns
(2)
tLZOE
tHZOE
tLZCE1
tLZCE2
tHZCE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
OE to Low-Z Output 0 — 0 — 0 — 0 — ns
(2)
OE to High-Z Output 0 10 0 15 0 20 0 25 ns
(2)
CE1 to Low-Z Output 3 — 5 — 7 — 10 — ns
(2)
CE2 to Low-Z Output 3 — 5 — 7 — 10 — ns
(2)
CE1 or CE2 to High-Z Output 0 10 0 15 0 20 0 25 ns
AC WAVEFORMS
READ CYCLE NO. 1
ADDRESS
DOUT
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
(1,2)
t
OHA
t
AA
t
RC
t
OHA
DATA VALID
5
IS62C1024 ISSI
®
READ CYCLE NO. 2
(1,3)
t
RC
ADDRESS
t
AA
OE
t
DOE
t
CE1
t
ACE1/tACE2
CE2
DOUT
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = V
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
t
LZCE1/
t
LZCE2
HIGH-Z
LZOE
IL, CE2 = VIH.
t
HZCE
DATA VALID
t
HZOE
t
OHA
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range, Standard and Low Power)
-35 -45 -55 -70
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 35 — 45 — 55 — 70 — ns
tSCE1 CE1 to Write End 25 — 35 — 50 — 60 — ns
tSCE2 CE2 to Write End 25 — 35 — 50 — 60 — ns
tAW Address Setup Time to Write End 25 — 35 — 45 — 60 — ns
tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
(4)
tPWE
WE Pulse Width 25 — 35 — 40 — 50 — ns
tSD Data Setup to Write End 20 — 25 — 25 — 30 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
(2)
tHZWE
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
WE LOW to High-Z Output — 10 — 15 — 20 — 25 ns
(2)
WE HIGH to Low-Z Output 3 — 5 — 5 — 5 — ns
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
IS62C1024 ISSI
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)
ADDRESS
CE1
CE2
WE
t
SA
DOUT
DATA UNDEFINED
(1,2)
t
AW
t
HZWE
t
SCE1
t
SCE2
t
WC
t
PWE
(4)
HIGH-Z
t
HA
t
LZWE
®
DIN
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)
ADDRESS
t
SA
CE1
CE2
t
AW
t
WE
t
HZWE
DOUT
DATA UNDEFINED
(1,2)
t
SCE1
t
PWE
t
WC
SCE2
(4)
HIGH-Z
t
SD
DATA-IN VALID
t
HA
t
HD
t
LZWE
t
HD
DIN
t
SD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = V
IH.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
7
IS62C1024 ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
35 IS62C1024-35Q 525-mil Plastic SOP
35 IS62C1024-35T TSOP, Type 1
45 IS62C1024-45Q 525-mil Plastic SOP
45 IS62C1024-45T TSOP, Type 1
55 IS62C1024-55Q 525-mil Plastic SOP
55 IS62C1024-55T TSOP, Type 1
70 IS62C1024-70Q 525-mil Plastic SOP
70 IS62C1024-70T TSOP, Type 1
®
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
35 IS62C1024-35QI 525-mil Plastic SOP
35 IS62C1024-35TI TSOP, Type 1
45 IS62C1024-45QI 525-mil Plastic SOP
45 IS62C1024-45TI TSOP, Type 1
55 IS62C1024-55QI 525-mil Plastic SOP
55 IS62C1024-55TI TSOP, Type 1
70 IS62C1024-70QI 525-mil Plastic SOP
70 IS62C1024-70TI TSOP, Type 1
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
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