Datasheet IS61VPD51236-200TQI, IS61VPD51236-200TQ, IS61VPD51236-166TQI, IS61VPD51236-166TQ, IS61VPD51236-166BI Datasheet (ISSI)

...

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION Rev. 00A

05/31/01

This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

IS61VPD51232 IS61VPD51236 IS61VPD10018

ISSI

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and control

• Linear burst sequence control using MODE input

•

Three chip enable option for simple depth expansion and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and 119-pin PBGA package

• Single +2.5V, ±5% operation

• Auto Power-down during deselect

• Double cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

DESCRIPTION

The ISSI IS61VPD51232, IS61VPD51236, and IS61VPD10018 are high-speed, low-power synchronous static

RAMs

designed to provide burstable,

high-performance memory for communication and networking applications. The

IS61VPD51232

is organized as 524,288 words by 32 bits and the IS61VPD51236 is organized as 524,288 words by 36 bits. The IS61VPD10018 is organized as 1,048,576 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edgetriggered single clock input.

Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls.

Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin.

The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.

512K x 32, 512K x 36, 1024K x 18 SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

ADVANCE INFORMATION

MAY 2001

FAST ACCESS TIME

Symbol Parameter -200 -166 Units

tKQ Clock Access Time 3.1 3.5 ns tKC Cycle Time 5 6 ns

Frequency 200 166 MHz

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION Rev. 00A

05/31/01

IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

BLOCK DIAGRAM

19/20

BINARY

COUNTER

BWa

CLR

CLK

MODE

A0'

A1'

CLK

ADV

ADSC ADSP

17/18 19/20

ADDRESS

CLK

DQd

BYTE WRITE

REGISTERS

CLK

DQc

BYTE WRITE

REGISTERS

CLK

DQb

BYTE WRITE

REGISTERS

CLK

DQa

BYTE WRITE

REGISTERS

CLK

ENABLE

CLK

ENABLE

DELAY

CLK

BWE

BWd

CE2

BWb

BWc

512Kx32; 512Kx36;

1024Kx18

MEMORY ARRAY

32, 36,

or 18

INPUT

REGISTERS

CLK

OUTPUT

REGISTERS

CLK

DQa - DQd

32, 36,

or 18

32, 36,

or 18

A19-A0 A18-A0

(x32/x36)

(x32/x36/x18)

(x32/x36)

(x32/x36/x18)

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION Rev. 00A

05/31/01

IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

PIN CONFIGURATION

100-Pin TQFP

512K x 32

PIN DESCRIPTIONS

A0, A1 Synchronous Address Inputs. These

pins must tied to the two LSBs of the address bus.

A2-A18 Synchronous Address Inputs

ADSC

Synchronous Controller Address Status

ADSP

Synchronous Processor Address Status

ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable

CLK Synchronous Clock

DQa-DQd Synchronous Data Input/Output GND Ground GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output Enable VCC +2.5V Power Supply VCCQ Isolated Output Buffer Supply:

+2.5V

ZZ Snooze Enable

NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 NC

A7CECE2

BWd

BWc

BWb

BWa

CE2

VCC

GND

CLK

BWEOEADSC

ADSP

ADV

NC DQc1 DQc2

VCCQ

GND DQc3 DQc4 DQc5 DQc6

GND

VCCQ

DQc7 DQc8

VCC

GND DQd1 DQd2

VCCQ

GND DQd3 DQd4 DQd5 DQd6

GND

VCCQ

DQd7 DQd8

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

A5A4A3A2A1

GND

VCC

A18

A17

A10

A11

A12

A13

A14

A15

A16

46 47 48 49 50

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ADVANCE INFORMATION Rev. 00A

05/31/01

IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

PIN CONFIGURATION

VCCQ

DQc1

DQc2

VCCQ

DQc5

DQc7

VCCQ

DQd1

DQd4

VCCQ

DQd6

DQd8

VCCQ

A18

DQPc

DQc3

DQc4

DQc6

DQc8

VCC

DQd2

DQd3

DQd5

DQd7

DQPd

TMS

GND

BWc

GND

BWd

GND

MODE

A10

TDI

ADSP

ADSC

VCC

ADV

VCC

CLK

BWE

VCC

A11

TCK

A12

GND

BWb

GND

BWa

GND

A14

TDO

A16

A17

A15

DQPb

DQb6

DQb5

DQb4

DQb2

VCC

DQa7

DQa5

DQa4

DQa3

DQPa

A13

VCCQ

DQb8

DQb7

VCCQ

DQb3

DQb1

VCCQ

DQa8

DQa6

VCCQ

DQa2

DQa1

VCCQ

1 2 3 4 5 6 7

DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 DQPa

A7CECE2

BWd

BWc

BWb

BWa

CE2

VCC

GND

CLK

BWEOEADSC

ADSP

ADV

DQPc

DQc1 DQc2

VCCQ

GND DQc3 DQc4 DQc5 DQc6

GND

VCCQ

DQc7 DQc8

VCC

GND DQd1 DQd2

VCCQ

GND DQd3 DQd4 DQd5 DQd6

GND

VCCQ

DQd7 DQd8

DQPd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

A5A4A3A2A1

GND

VCC

A18

A17

A10

A11

A12

A13

A14

A15

A16

46 47 48 49 50

512K x 36

119-pin PBGA (Top View) 100-Pin TQFP

PIN DESCRIPTIONS

A0, A1 Synchronous Address Inputs. These

pins must tied to the two LSBs of the address bus.

A2-A18 Synchronous Address Inputs

ADSC

Synchronous Controller Address Status

ADSP

Synchronous Processor Address Status

ADV

Synchronous Burst Address Advance

BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable

CLK Synchronous Clock DQa-DQd Synchronous Data Input/Output

DQPa-DQPd Parity Data Input/Output GND Ground GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output Enable TMS, TDI, JTAG Boundary Scan Pins

TCK, TDO VCC +2.5V Power Supply VCCQ Isolated Output Buffer Supply:

+2.5V

ZZ Snooze Enable

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION Rev. 00A

05/31/01

IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

PIN CONFIGURATION

VCCQ

DQb1

VCCQ

DQb4

VCCQ

DQb6

VCCQ

DQb8

VCCQ

A19

DQb2

DQb3

VCC

DQb5

DQb7

DQPb

A11

TMS

GND

BWb

GND

MODE

A10

TDI

ADSP

ADSC

VCC

ADV

VCC

CLK

BWE

VCC

TCK

A12

GND

BWa

GND

A14

TDO

A16

A18

A15

DQPa

DQa7

DQa5

VCC

DQa3

DQa2

A13

A17

VCCQ

DQa8

VCCQ

DQa6

VCCQ

DQa4

VCCQ

DQa1

VCCQ

1 2 3 4 5 6 7

1024K x 18

119-pin PBGA (Top View) 100-Pin TQFP

PIN DESCRIPTIONS

A0, A1 Synchronous Address Inputs. These

pins must tied to the two LSBs of the address bus.

A2-A19 Synchronous Address Inputs

ADSC

Synchronous Controller Address Status

ADSP

Synchronous Processor Address Status

ADV

Synchronous Burst Address Advance

BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable

CLK Synchronous Clock DQa-DQd Synchronous Data Input/Output

DQPa-DQPb Parity Data I/O; DQPa is parity for

DQa1-8; DQPb is parity for DQb1-8 GND Ground GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output Enable TMS, TDI, JTAG Boundary Scan Pins

TCK, TDO VCC +2.5V Power Supply VCCQ Isolated Output Buffer Supply:

+2.5V ZZ Snooze Enable

A17 NC NC VCCQ GND NC DQPa DQa8 DQa7 GND VCCQ DQa6 DQa5 GND NC VCC ZZ DQa4 DQa3 VCCQ GND DQa2 DQa1 NC NC GND VCCQ NC NC NC

A7CECE2NCNC

BWb

BWa

CE2

VCC

GND

CLK

BWEOEADSC

ADSP

ADV

NC NC NC

VCCQ

GND

NC DQb1 DQb2

GND

VCCQ

DQb3 DQb4

VCC

GND DQb5 DQb6

VCCQ

GND DQb7 DQb8 DQPb

GND

VCCQ

NC NC NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

A5A4A3A2A1

GND

VCC

A19

A18

A10

A11

A12

A13

A14

A15

A16

46 47 48 49 50

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ADVANCE INFORMATION Rev. 00A

05/31/01

IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

TRUTH TABLE

(1-8)

(3CE option)

OPERATION ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power-Down None H X X L X L X X X L-H High-Z Deselect Cycle, Power-Down None L X L L L XXXXL-HHigh-Z Deselect Cycle, Power-Down None L H X L L XXXXL-HHigh-Z Deselect Cycle, Power-Down None L X L L H L X X X L-H High-Z Deselect Cycle, Power-Down None L H X L H L X X X L-H High-Z Snooze Mode, Power-Down None XXXHXXXXXX High-Z Read Cycle, Begin Burst External L L H L L X X X L L-H Q Read Cycle, Begin Burst External L L H L L XXXHL-HHigh-Z Write Cycle, Begin Burst External L L H L H L X L X L-H D Read Cycle, Begin Burst External L L H L H L X H L L-H Q Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L HHHHLL-H Q Read Cycle, Suspend Burst Current X X X L HHHHHL-HHigh-Z Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X HHHHL-HHigh-Z Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

NOTE:

1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.

2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH.

3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version.

4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.

6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.

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ADVANCE INFORMATION Rev. 00A

05/31/01

IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

PARTIAL TRUTH TABLE

Function GW BWE BWa BWb BWc BWd

Read H H XXXX Read H L HHHH Write Byte 1 H L L H H H Write All Bytes H LLLLL Write All Bytes L XXXXX

TRUTH TABLE

(1-8)

(1CE option)

NEXT CYCLE ADDRESS CE ADSP ADSC ADV WRITE OE DQ

Deselected None H X L X X X High-Z Read, Begin External L L X X X L Q Read, Begin External L L X X X H High-Z Write, Begin Current L H L X Write X D Read, Begin External L H L X Read L Q Read, Begin External L H L X Read H High-Z Read, Burst Next X H H L Read L Q Read, Burst Next X H H L Read H High-Z Read, Burst Next H X H L Read L Q Read, Burst Next H X H L Read H High-Z Write, Burst Next X H H L Write X D Write, Burst Next H X H L Write X D Read, Suspend Current X H H H Read L Q Read, Suspend Current X H H H Read H High-Z Read, Suspend Current H X H H Read L Q Read, Suspend Current H X H H Read H High-Z Write, Suspend Current X H H H Write X D Write, Suspend Current H X H H Write X D

NOTE:

1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.

2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH.

4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.

6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

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ADVANCE INFORMATION Rev. 00A

05/31/01

IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)

External Address 1st Burst Address 2nd Burst Address 3rd Burst Address

A1 A0 A1 A0 A1 A0 A1 A0

00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00

LINEAR BURST ADDRESS TABLE (MODE = GND)

0,0

1,0

0,1A1', A0' = 1,1

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

TBIAS Temperature Under Bias –40 to +85 °C TSTG Storage Temperature –55 to +150 °C PD Power Dissipation 1.6 W IOUT Output Current (per I/O) 100 mA VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.5 V VIN Voltage Relative to GND for –0.5 to VCC + 0.5 V

for Address and Control Inputs

VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 3.2 V

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

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ADVANCE INFORMATION Rev. 00A

05/31/01

IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

OPERATING RANGE

Range Ambient Temperature VCC VCCQ

Commercial 0°C to +70°C 2.375–2.625V 2.375–2.625V Industrial –40°C to +85°C 2.375–2.625V 2.375–2.625V

DC ELECTRICAL CHARACTERISTICS

(1)

(Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage IOH = –2.0 mA, VCCQ = 2.5V 1.7 — V VOL Output LOW Voltage IOL = 2.0 mA, VCCQ = 2.5V — 0.7 V VIH Input HIGH Voltage VCCQ = 2.5V 1.7 VCCQ + 0.3 V VIL Input LOW Voltage VCCQ = 2.5V –0.3 0.7 V ILI Input Leakage Current GND ≤ VIN ≤ VCCQ

(2)

Com. –22µA

Ind. –55

ILO Output Leakage Current GND ≤ VOUT ≤ VCCQ, OE = VIH Com. –22µA

Ind. –55

POWER SUPPLY CHARACTERISTICS (Over Operating Range)

-200 -166

Symbol Parameter Test Conditions Max. Max. Unit

ICC AC Operating Device Selected, Com. 300 275 mA

Supply Current All Inputs = VIL or VIH Ind. 325 300 mA

OE = VIH, Vcc = Max. Cycle Time ≥ tKC min.

ISB Standby Current Device Deselected, Com. 70 60 mA

VCC = Max., Ind. 80 70 mA All Inputs = VIH or VIL CLK Cycle Time ≥ tKC min.

Notes:

1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to V

CC.

2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to - GND + 0.2V or ≥ Vcc – 0.2V.

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ADVANCE INFORMATION Rev. 00A

05/31/01

IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

CAPACITANCE

(1,2)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF COUT Input/Output Capacitance VOUT = 0V 8 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

A = 25°C, f = 1 MHz, Vcc = 3.3V.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 2.5V Input Rise and Fall Times 1.5 ns Input and Output Timing VCCQ/2V

and Reference Level Output Load See Figures 1 and 2

AC TEST LOADS

Figure 2

1667 Ω

5 pF

Including

jig and

scope

1538 Ω

OUTPUT

2.5V

Figure 1

Output Buffer

ZO = 50Ω

CCQ

/2V

50Ω

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ADVANCE INFORMATION Rev. 00A

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IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

-200 -166

Symbol Parameter Min. Max. Min. Max. Unit

fMAX Clock Frequency — 200 — 166 MHz tKC Cycle Time 5 — 6 — ns tKH Clock High Pulse Width 2 — 2.3 — ns tKL Clock Low Pulse Width 2 — 2.3 — ns tKQ Clock Access Time — 3.1 — 3.5 ns tKQX

(1)

Clock High to Output Invalid 1.0 — 1.5 — ns

tKQLZ

(1,2)

Clock High to Output Low-Z 0 — 0 — ns

tKQHZ

(1,2)

Clock High to Output High-Z — 3.1 — 3.5 ns tOEQ Output Enable to Output Valid — 3.1 — 3.5 ns tOELZ

(1,2)

Output Enable to Output Low-Z 0 — 0 — ns tOEHZ

(1,2)

Output Enable to Output High-Z — 3.0 — 3.2 ns tAS Address Setup Time 1.5 — 1.5 — ns tSS Address Status Setup Time 1.5 — 1.5 — ns tWS Write Setup Time 1.5 — 1.5 — ns tCES Chip Enable Setup Time 1.5 — 1.5 — ns tAVS Address Advance Setup Time 1.5 — 1.5 — ns tAH Address Hold Time 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — ns

Note:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.

2. Tested with load in Figure 2.

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ADVANCE INFORMATION Rev. 00A

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IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

READ/WRITE CYCLE TIMING

Single Read

High-Z

DATA

OUT

DATA

CE2

BWx

BWE

Address

ADV

ADSC

ADSP

CLK

RD1 RD2

2c 2d 3a

Unselected

Burst Read

KQX

RD3

CES

CEH

CES

CEH

CES

CEH

CE2 and CE2 only sampled with ADSP or ADSC

CE Masks ADSP

Unselected with CE2

OEQ

OEQX

OELZ

KQLZ

OEHZ

KQHZ

ADSC initiate read

ADSP is blocked by CE inactive

AVH

AVS

Suspend Burst

Pipelined Read

2a 2b

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ADVANCE INFORMATION Rev. 00A

05/31/01

IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

-200 -166

Symbol Parameter Min. Max. Min. Max. Unit

tKC Cycle Time 5 — 6 — ns tKH Clock High Pulse Width 2 — 2.3 — ns tKL Clock Low Pulse Width 2 — 2.3 — ns tAS Address Setup Time 1.5 — 1.5 — ns tSS Address Status Setup Time 1.5 — 1.5 — ns tWS Write Setup Time 1.5 — 1.5 — ns tDS Data In Setup Time 1.5 — 1.5 — ns tCES Chip Enable Setup Time 1.5 — 1.5 — ns tAVS Address Advance Setup Time 1.5 — 1.5 — ns tAH Address Hold Time 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — ns tDH Data In Hold Time 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — ns

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ADVANCE INFORMATION Rev. 00A

05/31/01

IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

WRITE CYCLE TIMING

Single Write

DATA

OUT

DATA

CE2

BWx

BWE

Address

ADV

ADSC

ADSP

CLK

WR1 WR2

Unselected

Burst Write

WR3

CES

CEH

CES

CEH

CES

CEH

CE2 and CE2 only sampled with ADSP or ADSC

CE Masks ADSP

Unselected with CE2

ADSC initiate Write

ADSP is blocked by CE inactive

AVH

AVS

ADV must be inactive for ADSP Write

WR1 WR2

WR3

High-Z

BW4-BW1 only are applied to first cycle of WR2

Write

2c 2d2a 2b

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IS61VPD51232 IS61VPD51236

IS61VPD10018 ISSI

SNOOZE MODE TIMING

Don't Care

Deselect or Read Only

RZZI

CLK

Isupply

All Inputs (except ZZ)

Outputs (Q)

SB2

ZZ setup cycle ZZ recovery cycle

Normal

operation

cycle

PDS

PUS

ZZI

High-Z

SNOOZE MODE ELECTRICAL CHARACTERISTICS

Symbol Parameter Conditions Min. Max. Unit

ISB2 Current during SNOOZE MODE ZZ ≥ Vih — 15 mA tPDS ZZ active to input ignored — 2 cycle tPUS ZZ inactive to input sampled 2 — cycle tZZI ZZ active to SNOOZE current — 2 cycle tRZZI ZZ inactive to exit SNOOZE current 0 — ns

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IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)

The IS61VPS51236 and IS61VPS10018 have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (Not available in TQFP package or with the IS61VPS51232.) This port operates in accordance with IEEE

Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the

IEEE specification

are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using

1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels.

DISABLING THE JTAG FEATURE

The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (GND) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to VCC through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation.

TEST ACCESS PORT (TAP) - TEST CLOCK

The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK.

TEST MODE SELECT (TMS)

The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level.

TEST DATA-IN (TDI)

The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register.

31 30 29 . . . 2 1 0

2 1 0

x . . . . . 2 1 0

Bypass Register

Instruction Register

Identification Register

Boundary Scan

TAP CONTROLLER

Selection Circuitry Selection Circuitry TDOTDI

TCK

TMS

TAP CONTROLLER BLOCK DIAGRAM

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TEST DATA OUT (TDO)

The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the

TAP

state machine (see

TAP

Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register.

PERFORMING A TAP RESET

A Reset is performed by forcing TMS HIGH (VCC) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state.

TAP REGISTERS

Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the

TDI

and

TDO

pins. (See

TAP

Controller Block Diagram) At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described.

When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the

SRAM

with minimal delay. The bypass register

is set LOW (GND) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all input and output pins on the

SRAM

. Several no connect

(NC)

pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 70-bit-long register and the x18 configuration has a 51-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the

TDI

and

TDO

pins when the controller is moved

to the

Shift-DR

state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring.

The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has vendor code and other information described in the Identification Register Definitions table.

Scan Register Sizes

Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 51 70

IDENTIFICATION REGISTER DEFINITIONS

Instruction Field Description 512K x 36 1M x 18

Revision Number (31:28) Reserved for version number. xxxx xxxx Device Depth (27:23) Defines depth of SRAM. 512K or 1M 00111 01000 Device Width (22:18) Defines with of the SRAM. x36 or x18 00100 00011 ISSI Device ID (17:12) Reserved for future use. xxxxx xxxxx ISSI JEDEC ID (11:1) Allows unique identification of SRAM vendor. 00011010101 00011010101 ID Register Presence (0) Indicate the presence of an ID register. 1 1

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TAP INSTRUCTION SET

Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as

RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the

Input

Output

buffers. The

SRAM

does not implement the

1149.1

com-

mands

EXTEST

INTEST

or the

PRELOAD

portion of SAMPLE/PRELOAD

; instead it performs a capture of the

Inputs and Output

ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. Because EXTEST is not implemented in the TAP controller, this device is not 1149.1 standard compliant. The TAP controller recognizes an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is a difference between the instructions, unlike the

SAMPLE/PRELOAD

instruction,

EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.

It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capture while in transition (metastable state). The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results.

To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (t

CS and tCH). To insure that

the SRAM clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK and CLK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

Note that since the

PRELOAD

part of the command is not

implemented, putting the

TAP

into the

Update

to the

Update-DR

state while performing a

SAMPLE/PRELOAD

instruction

will have the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

RESERVED

These instructions are not implemented but are reserved for future use. Do not use these instructions.

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INSTRUCTION CODES

Code Instruction Description

000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register

between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.

001 IDCODE Loads the ID register with the vendor ID code and places the register between

TDI and TDO. This operation does not affect SRAM operation.

010 SAMPLE Z Captures the Input/Output contents. Places the boundary scan register between

TDI and TDO. Forces all SRAM output drivers to a High-Z state. 011 RESERVED Do Not Use: This instruction is reserved for future use. 100

SAMPLE/PRELOAD

Captures the Input/Output ring contents. Places the boundary scan register

between

TDI and TDO. Does not affect the SRAM operation. This instruction does not

implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 RESERVED Do Not Use: This instruction is reserved for future use. 110 RESERVED Do Not Use: This instruction is reserved for future use. 111 BYPASS Places the bypass register between TDI and TDO. This operation does not

affect SRAM operation.

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test/Idle

11 1

TAP CONTROLLER STATE DIAGRAM

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TAP Electrical Characteristics Over the Operating Range

(1,2)

Symbol Parameter Test Conditions Min. Max. Units

VOH1 Output HIGH Voltage IOH = –2.0 mA 1.7 — V VOH2 Output HIGH Voltage IOH = –100 mA 2.1 — V VOL1 Output LOW Voltage IOL = 2.0 mA — 0.7 V VOL2 Output LOW Voltage IOL = 100 mA — 0.2 V VIH Input HIGH Voltage 1.7 VCC +0.3 V VIL Input LOW Voltage IOLT = 2mA –0.3 0.7 V IX Input Load Current GND ≤ V I ≤ VDDQ –55mA

Notes:

1. All Voltage referenced to Ground.

2. Overshoot: V

IH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2,

Undershoot:V

IL (AC) ≤ 0.5V for t ≤ tTCYC/2,

Power-up: V

IH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.

TAP AC ELECTRICAL CHARACTERISTICS

(1)

(OVER OPERATING RANGE)

Symbol Parameter Min. Max. Unit

tTCYC TCK Clock cycle time 100 — ns fTF TCK Clock frequency — 10 MHz tTH TCK Clock HIGH 40 — ns tTL TCK Clock LOW 40 — ns tTMSS TMS setup to TCK Clock Rise 10 — ns tTDIS TDI setup to TCK Clock Rise 10 — ns tCS Capture setup to TCK Rise 10 — ns tTMSH

TMS hold after TCK Clock Rise

10 — ns tTDIH TDI Hold after Clock Rise 10 — ns tCH Capture hold after Clock Rise 10 — ns tTDOV TCK LOW to TDO valid — 20 ns tTDOX TCK LOW to TDO invalid 0 — ns

Notes:Notes:

Notes:

7. t

CS and tCHrefer to the set-up and hold time requirements of latching data from the boundary scan register.

8. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

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DON'T CARE

UNDEFINED

TCK

TMS

TDI

TDO

THTL

TLTH

THTH

MVTH tTHMX

DVT H tTHDX

1 2 3 4 5 6

TLOX

TLOV

TAP TIMING

20 pF

TDO

GND

50Ω

1.25V

Z0 = 50Ω

TAP Output Load EquivalentTAP Output Load Equivalent

TAP Output Load EquivalentTAP AC TEST CONDITIONS

Input pulse levels 0 to 2.5V Input rise and fall times 1ns Input timing reference levels 1.25V Output reference levels 1.25V Test load termination supply voltage 1.25V

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BOUNDARY SCAN ORDER (512K X 36)

Signal Bump Signal Bump Signal Bump Signal Bump

Bit # Name ID Bit # Name ID Bit # Name ID Bit # Name ID

1 A 2R 19 DQb 7G 37 BWa 5L 55 DQd 2K 2 A 3T 20 DQb 6F 38 BWb 5G 56 DQd 1L 3 A 4T 21 DQb 7E 39 BWc 3G 57 DQd 2M 4 A 5T 22 DQb 6D 40 BWd 3L 58 DQd 1N 5 A 6R 23 DQb 7H 41 A 2B 59 DQd 2P 6 A 3B 24 DQb 6G 42 CE 4E 60 DQd 1K 7 A 5B 25 DQb 6E 43 A 3A 61 DQd 2L 8 DQa 6P 26 DQb 7D 44 A 2A 62 DQd 2N

9 DQa 7N 27 A 6A 45 DQc 2D 63 DQd 1P 10 DQa 6M 28 A 5A 46 DQc 1E 64 MODE 3R 11 DQa 7L 29 ADV 4G 47 DQc 2F 65 A 2C 12 DQa 6K 30 ADSP 4A 48 DQc 1G 66 A 3C 13 DQa 7P 31 ADSC 4B 49 DQc 1D 67 A 5C 14 DQa 6N 32 OE 4F 50 DQc 1D 68 A 6C 15 DQa 6L 33 BWE 4M 51 DQc 2E 69 A1 4N 16 DQa 7K 34 GW 4H 52 DQc 2G 70 A0 4P 17 ZZ 7T 35 CLK 4K 53 DQc 1H 18 DQb 6H 36 A 6B 54 NC 5R

BOUNDARY SCAN ORDER (1M X 18)

Signal Bump Signal Bump Signal Bump Signal Bump

Bit # Name ID Bit # Name ID Bit # Name ID Bit # Name ID

1 A 2R 14 DQa 7G 27 CLK 4K 40 DQb 2K

2 A 2T 15 DQa 6F 27 A 6B 41 DQb 1L

3 A 3T 16 DQa 7E 29 BWa 5L 42 DQb 2M

4 A 5T 17 DQa 6D 30 BWb 3G 43 DQb 1N

5 A 6R 18 A 6T 31 A 2B 44 DQb 2P

6 A 3B 19 A 6A 32 CE 4E 45 MODE 3R

7 A 5B 20 A 5A 33 A 3A 46 A 2C

8 DQa 7P 21 ADV 4G 34 A 2A 47 A 3C

9 DQa 6N 22 ADSP 4A 35 DQb 1D 48 A 5C 10 DQa 6L 23 ADSC 4B 36 DQb 2E 49 A 6C 11 DQa 7K 24 OE 4F 37 DQb 2G 50 A1 4N 12 ZZ 7T 25 BWE 4M 38 DQb 1H 51 A0 4P 13 DQa 6H 26 GW 4H 39 NC 5R

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ORDERING INFORMATION Commercial Range: 0°C to +70°C

Speed Order Part Number Package

200 MHz IS61VPD51232-200TQ TQFP 166 MHz IS61VPD51232-166TQ TQFP

Industrial Range: –40°C to +85°C

Speed Order Part Number Package

200 MHz IS61VPD51232-200TQI TQFP 166 MHz IS61VPD51232-166TQI TQFP

Commercial Range: 0°C to +70°C

Speed Order Part Number Package

200 MHz IS61VPD51236-200TQ TQFP

IS61VPD51236-200B PBGA

166 MHz IS61VPD51236-166TQ TQFP

IS61VPD51236-166B PBGA

Industrial Range: –40°C to +85°C

Speed Order Part Number Package

200 MHz IS61VPD51236-200TQI TQFP

IS61VPD51236-200BI PBGA

166 MHz IS61VPD51236-166TQI TQFP

IS61VPD51236-166BI PBGA

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ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774 Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

ORDERING INFORMATION Commercial Range: 0°C to +70°C

Speed Order Part Number Package

200 MHz IS61VPD10018-200TQ TQFP

IS61VPD10018-200B PBGA

166 MHz IS61VPD10018-166TQ TQFP

IS61VPD10018-166B PBGA

Industrial Range: –40°C to +85°C

Speed Order Part Number Package

200 MHz IS61VPD10018-200TQI TQFP

IS61VPD10018-200BI PBGA

166 MHz IS61VPD10018-166TQI TQFP

IS61VPD10018-166BI PBGA

Datasheet IS61VPD51236-200TQI, IS61VPD51236-200TQ, IS61VPD51236-166TQI, IS61VPD51236-166TQ, IS61VPD51236-166BI Datasheet (ISSI)

Specifications and Main Features

Frequently Asked Questions

User Manual