Datasheet IS61SPS51218T-150TQ, IS61SPS51218T-133TQI, IS61SPS51218T-133TQ, IS61SPS51218D-150TQI, IS61SPS51218D-150TQ Datasheet (ISSI)
...
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
PRELIMINARY INFORMATION Rev. 00B
05/09/01
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D
ISSI
®
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Linear burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
• 3.3V I/O For SPS
• 2.5V I/O For LPS
• Single cycle deselect
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)
DESCRIPTION
The ISSI IS61SPS25632, IS61SPS25636, IS61SPS51218,
IS61LPS25632, IS61LPS25636, and IS61LPS51218 are
high-speed, low-power synchronous static RAMs designed
to provide a burstable, high-performance memory for
communication and networking applications. The
IS61SPS25632 and IS61LPS25632 are organized as
262,144 words by 32 bits and the IS61SPS25636 and
IS61LPS25636 are organized as 262,144 words by 36 bits.
The IS61SPS51218 and IS61LPS51218 are organized as
524,288 words by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positiveedge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE).input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINE,
SINGLE-CYCLE DESELECT STATIC RAM
PRELIMINARY INFORMATION
MAY 2001
FAST ACCESS TIME
Symbol Parameter -150 -133 Units
tKQ
Clock Access Time
3.8 4 ns
tKC Cycle Time 6.7 7.5 ns
Frequency 150 133 MHz
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
BLOCK DIAGRAM
18/19
BINARY
COUNTER
A17-A0
(61SPS25632/36,
61LPS25632/36)
BWa
GW
CLR
CE
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
16/17 18/19
ADDRESS
REGISTER
CE
D
CLK
Q
DQd
BYTE WRITE
REGISTERS
D
CLK
Q
DQc
BYTE WRITE
REGISTERS
D
CLK
Q
DQb
BYTE WRITE
REGISTERS
D
CLK
Q
DQa
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BWd
(T, D) CE
(T) CE2
(T, D)
CE2
BWb
BWc
256Kx32; 256Kx36;
512Kx18
MEMORY ARRAY
32, 36,
or 18
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
4
OE
DQa - DQd
32, 36,
or 18
32, 36,
or 18
A18-A0
(61SPS51218,
61LPS51218)
(x32/x36)
(x32/x36/x18)
(x32/x36)
(x32/x36/x18)
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
A6
CE2
A7
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
A5
NC
NC
A4
A3
A2
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A14
NC
A16
A17
A15
NC
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
A6
A7CECE2
BWd
BWc
BWb
BWa
A17
VCC
GND
CLKGWBWEOEADSC
ADSP
ADV
A8
A9
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
119-pin PBGA (Top View) 100-Pin TQFP (D Version)
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
GNDQ Isolated Output Buffer Ground
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
PIN CONFIGURATION
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
A6
A7CECE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWEOEADSC
ADSP
ADV
A8
A9
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
A17
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
100-Pin TQFP (T Version)
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
GNDQ Isolated Output Buffer Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
A6
CE2
A7
DQPc
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
DQPd
A5
NC
NC
A4
A3
A2
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A14
NC
A16
A17
A15
DQPb
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
DQPa
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
A6
A7CECE2
BWd
BWc
BWb
BWa
A17
VCC
GND
CLK
GW
BWEOEADSC
ADSP
ADV
A8
A9
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
256K x 36
119-pin PBGA (Top View) 100-Pin TQFP (D Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Individual Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
PIN CONFIGURATION
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
A6
A7CECE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWEOEADSC
ADSP
ADV
A8
A9
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
A17
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
256K x 36
100-Pin TQFP (T Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Individual Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
PIN CONFIGURATION
A17
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
A6
A7CECE2NCNC
BWb
BWa
A18
VCC
GND
CLK
GW
BWEOEADSC
ADSP
ADV
A8
A9
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
VCC
VCC
NC
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQb1
NC
VCCQ
NC
DQb4
VCCQ
NC
DQb6
VCCQ
DQb8
NC
NC
NC
VCCQ
A6
CE2
A7
NC
DQb2
NC
DQb3
NC
VCC
DQb5
NC
DQb7
NC
DQPb
A5
A11
NC
A4
A3
A2
GND
GND
GND
BWb
GND
NC
GND
GND
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
GND
GND
NC
GND
BWa
GND
GND
GND
NC
A14
NC
A16
A18
A15
DQPa
NC
DQa7
NC
DQa5
VCC
NC
DQa3
NC
DQa2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQa8
VCCQ
DQa6
NC
VCCQ
DQa4
NC
VCCQ
NC
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
512K x 18
119-pin PBGA (Top View) 100-Pin TQFP (D Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A18 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWb Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQb Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPb
Parity Data I/O DQPa is parity for DQa1-8;
DQPb is parity for DQb1-8
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A18 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWb Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQb Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPb
Parity Data I/O DQPa is parity for DQa1-8;
DQPb is parity for DQb1-8
PIN CONFIGURATION
A17
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
A6
A7CECE2NCNC
BWb
BWa
CE2
VCC
GND
CLK
GW
BWEOEADSC
ADSP
ADV
A8
A9
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
VCC
VCC
NC
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
A18
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
512K x 18
100-Pin TQFP (T Version)
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
PARTIAL TRUTH TABLE
Function GW BWE BWa BWb BWc BWd
Read H H XXXX
Read H L HHHH
Write Byte 1 H L L H H H
Write All Bytes H LLLLL
Write All Bytes L XXXXX
TRUTH TABLE
Address
Operation Used CE CE2 CE2 ADSP ADSC ADV WRITE OE DQ
Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L X H L XXXXHigh-Z
Deselected, Power-down None L L X L XXXXHigh-Z
Deselected, Power-down None L X H H L X X X High-Z
Deselected, Power-down None L L X H L X X X High-Z
Read Cycle, Begin Burst External L H L L XXXXQ
Read Cycle, Begin Burst External L H L H L X Read X Q
Write Cycle, Begin Burst External L H L H L X Write X D
Read Cycle, Continue Burst Next X X X H H L Read L Q
Read Cycle, Continue Burst Next X X X H H L Read H High-Z
Read Cycle, Continue Burst Next H X X X H L Read L Q
Read Cycle, Continue Burst Next H X X X H L Read H High-Z
Write Cycle, Continue Burst Next X X X H H L Write X D
Write Cycle, Continue Burst Next H X X X H L Write X D
Read Cycle, Suspend Burst Current X X X H H H Read L Q
Read Cycle, Suspend Burst Current X X X H H H Read H High-Z
Read Cycle, Suspend Burst Current H X X X H H Read L Q
Read Cycle, Suspend Burst Current H X X X H H Read H High-Z
Write Cycle, Suspend Burst Current X X X H H H Write X D
Write Cycle, Suspend Burst Current H X X X H H Write X D
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.5 V
VIN Voltage Relative to GND for –0.5 to VCC + 0.5 V
for Address and Control Inputs
VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
0,0
1,0
0,1A1', A0' = 1,1
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
OPERATING RANGE
Range Ambient Temperature VCC VCCQ
Commercial 0°C to +70°C 3.3V, +10%, –5% 2.375–3.6V
Industrial –40°C to +85°C 3.3V, +10%, –5% 2.375–3.6V
DC ELECTRICAL CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
V
OH Output HIGH Voltage IOH = –2.0 mA, VCCQ = 2.5V 1.7 — V
IOH = –4.0 mA, VCCQ = 3.3V 2.4 — V
V
OL Output LOW Voltage IOL = 2.0 mA, VCCQ = 2.5V — 0.7 V
IOL = 8.0 mA, VCCQ = 3.3V — 0.4 V
VIH Input HIGH Voltage VCCQ = 2.5V 1.7 VCCQ + 0.3 V
VCCQ = 3.3V 2.0 VCCQ + 0.3 V
VIL Input LOW Voltage VCCQ = 2.5V –0.3 0.7 V
VCCQ = 3.3V –0.3 0.8 V
ILI Input Leakage Current GND ≤ VIN ≤ VCCQ
(2)
Com. –22µA
Ind. –55
ILO Output Leakage Current GND ≤ VOUT ≤ VCCQ, OE = VIH Com. –22µA
Ind. –55
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-150 -133
Symbol Parameter Test Conditions Max. Max. Unit
ICC AC Operating Device Selected, Com. 250 230 mA
Supply Current All Inputs = VIL or VIH Ind. 280 250 mA
OE = VIH, Vcc = Max.
Cycle Time ≥ tKC min.
ISB Standby Current Device Deselected, Com. 50 40 mA
VCC = Max., Ind. 60 50 mA
All Inputs = VIH or VIL
CLK Cycle Time ≥ tKC min.
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to V
CC.
2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to
- GND + 0.2V or ≥ Vcc – 0.2V.
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V for 3.3V I/O
and Reference Level VCCQ/2V for 2.5V I/O
Output Load See Figures 1 and 2
Figure 2
317 Ω/1667 Ω
5 pF
Including
jig and
scope
351 Ω/1538 Ω
OUTPUT
3.3V for 3.3V I/O
/2.5V for 2.5v I/O
Figure 1
Output
Buffer
Z
O = 50Ω
1.5V for 3,3V I/O
V
CCQ/2V for 2.5V I/O
50Ω
AC TEST LOADS
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-150 -133
Symbol Parameter Min. Max. Min. Max. Unit
fMAX Clock Frequency — 150 — 133 MHz
tKC Cycle Time 6.7 — 7.5 — ns
tKH Clock High Pulse Width 2.5 — 2.8 — ns
tKL Clock Low Pulse Width 2.5 — 2.8 — ns
tKQ Clock Access Time — 3.8 — 4ns
tKQX
(1)
Clock High to Output Invalid 1.5 — 1.5 — ns
tKQLZ
(1,2)
Clock High to Output Low-Z 0 — 0 — ns
tKQHZ
(1,2)
Clock High to Output High-Z — 3.8 — 4ns
tOEQ Output Enable to Output Valid — 3.8 — 4ns
tOELZ
(1,2)
Output Enable to Output Low-Z 0 — 0 — ns
tOEHZ
(1,2)
Output Enable to Output High-Z — 3.8 — 4ns
tAS Address Setup Time 1.5 — 1.5 — ns
tSS Address Status Setup Time 1.5 — 1.5 — ns
tWS Write Setup Time 1.5 — 1.5 — ns
tCES Chip Enable Setup Time 1.5 — 1.5 — ns
tAVS Address Advance Setup Time 1.5 — 1.5 — ns
tAH Address Hold Time 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-150 -133
Symbol Parameter Min. Max. Min. Max. Unit
tKC Cycle Time 6.7 — 7.5 — ns
tKH Clock High Pulse Width 2.5 — 2.8 — ns
tKL Clock Low Pulse Width 2.5 — 2.8 — ns
tAS Address Setup Time 1.5 — 1.5 — ns
tSS Address Status Setup Time 1.5 — 1.5 — ns
tWS Write Setup Time 1.5 — 1.5 — ns
tDS Data In Setup Time 1.5 — 1.5 — ns
tCES Chip Enable Setup Time 1.5 — 1.5 — ns
tAVS Address Advance Setup Time 1.5 — 1.5 — ns
tAH Address Hold Time 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — ns
tDH Data In Hold Time 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — ns
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions Min. Max. Unit
ISB2 Current during SNOOZE MODE ZZ ≥ Vih — 15 mA
tPDS ZZ active to input ignored — 2 cycle
tPUS ZZ inactive to input sampled 2 — cycle
tZZI ZZ active to SNOOZE current — 2 cycle
tRZZI ZZ inactive to exit SNOOZE current 0 — ns
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
READ/WRITE CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
RD1 RD2
1a
2c 2d 3a
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQHZ
ADSC initiate read
ADSP is blocked by CE inactive
t
AVH
t
AVS
Suspend Burst
Pipelined Read
2a 2b
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
WR1 WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1 WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z
1a
3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2a 2b
Integrated Silicon Solution, Inc. — 1-800-379-4774
17
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
SNOOZE MODE TIMING
Don't Care
Deselect or Read Only
Deselect or Read Only
t
RZZI
CLK
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
I
SB2
ZZ setup cycle ZZ recovery cycle
Normal
operation
cycle
t
PDS
t
PUS
t
ZZI
High-Z
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
PARPAR
PARPAR
PAR
TT
TT
T
IDENTIFICA IDENTIFICA
IDENTIFICA IDENTIFICA
IDENTIFICA
TIONTION
TIONTION
TION
61XPSXXXXXX-XXXXXX
Rating Commercial
I - Industrial
Package TQ - TQFP
B - PBGA
Speed 150 - 150 MHz
133 - 133 MHz
Density 25632 - 256K x 32
25636 - 256K x 36
51218 - 512K x 18
S - single-cycle deselect
D - double-cycle dedelect
SP - 3.3V I/O synchronous pipeline
LP - 2.5V I/O synchronous pipeline
T - Three chip selects
D - Two chip selects
Integrated Silicon Solution, Inc. — 1-800-379-4774
19
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
150 MHz IS61SPS51218T-150TQ TQFP
IS61SPS51218D-150TQ TQFP
IS61SPS51218D-150B PBGA
133 MHz IS61SPS51218T-133TQ TQFP
IS61SPS51218D-133TQ TQFP
IS61SPS51218D-133B PBGA
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
150 MHz IS61SPS51218T-150TQI TQFP
IS61SPS51218D-150TQI TQFP
133 MHz IS61SPS51218T-133TQI TQFP
IS61SPS51218D-133TQI TQFP
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
150 MHz IS61SPS25632T-150TQ TQFP
IS61SPS25632D-150TQ TQFP
IS61SPS25632D-150B PBGA
133 MHz IS61SPS25632T-133TQ TQFP
IS61SPS25632D-133TQ TQFP
IS61SPS25632D-133B PBGA
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
150 MHz IS61SPS25632T-150TQI TQFP
IS61SPS25632D-150TQI TQFP
133 MHz IS61SPS25632T-133TQI TQFP
IS61SPS25632D-133TQI TQFP
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
150 MHz IS61SPS25636T-150TQ TQFP
IS61SPS25636D-150TQ TQFP
IS61SPS25636D-150B PBGA
133 MHz IS61SPS25636T-133TQ TQFP
IS61SPS25636D-133TQ TQFP
IS61SPS25636D-133B PBGA
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
150 MHz IS61SPS25636T-150TQI TQFP
IS61SPS25636D-150TQI TQFP
133 MHz IS61SPS25636T-133TQI TQFP
IS61SPS25636D-133TQI TQFP
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D IS61LPS25632T/D
IS61SPS25636T/D IS61LPS25636T/D
IS61SPS51218T/D IS61LPS51218T/D ISSI
®
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
150 MHz IS61LPS51218T-150TQ TQFP
IS61LPS51218D-150TQ TQFP
IS61LPS51218D-150B PBGA
133 MHz IS61LPS51218T-133TQ TQFP
IS61LPS51218D-133TQ TQFP
IS61LPS51218D-133B PBGA
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
133 MHz IS61LPS51218T-133TQI TQFP
IS61LPS51218D-133TQI TQFP
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
150 MHz IS61LPS25632T-150TQ TQFP
IS61LPS25632D-150TQ TQFP
IS61LPS25632D-150B PBGA
133 MHz IS61LPS25632T-133TQ TQFP
IS61LPS25632D-133TQ TQFP
IS61LPS25632D-133B PBGA
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
133 MHz IS61LPS25632T-133TQI TQFP
IS61LPS25632D-133TQI TQFP
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
150 MHz IS61LPS25636T-150TQ TQFP
IS61LPS25636D-150TQ TQFP
IS61LPS25636D-150B PBGA
133 MHz IS61LPS25636T-133TQ TQFP
IS61LPS25636D-133TQ TQFP
IS61LPS25636D-133B PBGA
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
133 MHz IS61LPS25636T-133TQI TQFP
IS61LPS25636D-133TQI TQFP
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